Cirrus Logic, Inc.

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7851
http://www.cirrus.com

EP7211

Preliminary Data Sheet

OVERVIEW

FEATURES

(cont.)

Functional Block Diagram

Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz at 2.5 V

Performance matching 100-MHz Intel

Pentium-based PC

Socket and register compatible with CL-PS7111

Ultra low power

-- Designed for applications that require long battery life

while using standard AA/AAA batteries or rechargeable
cells

-- 170 mW at 74 MHz in the Operating State
-- 50 mW at 18 MHz in the Operating State
-- 15 mW in the Idle State (clock to the CPU stopped,

everything else running)

-- 10

µW in the Standby State (realtime clock `on',

everything else stopped)

LCD controller

-- Interfaces directly to a single-scan panel monochrome

LCD

-- Panel width size is programmable from 32 to 1024 pixels

in 16-pixel increments

-- Video frame buffer size programmable up to 128 kbytes
-- Bits per pixel programmable from 1, 2, or 4

The EP7211 is designed for ultra-low-power applica-
tions such as organizers/PDAs, two-way pagers,
smart cellular phones, and industrial hand-held infor-
mation appliances. The core-logic functionality of the
device is built around an ARM720T processor with 8
kbytes of four-way set-associative unified cache and
a write buffer. Incorporated into the ARM720T is an
enhanced memory management unit (MMU), which
allows for Microsoft Windows CE support.

The EP7211 also includes a 32-bit Y2K-compliant
Real Time Clock (RTC) and comparator.

32.768-KHZ

OSCILLATOR

PLL

INTERRUPT

CONTROLLER

POWER

MANAGEMENT

SSI1 (ADC)

DRAM

CONTROLLER

LCD

CONTROLLER

ARM7TDMI
CPU CORE

8-KBYTE

CACHE

MMU

TIMER

COUNTERS (2)

CODEC

ARM720T

INTERNAL DATA BUS

PWM

3.6864 MHZ

32.768 KHZ

EINT[13], FIQ,

MEDCHG

BATOK, EXTPWR
PWRFL, BATCHG

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (07)

BUZZER DRIVE

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

ADCCS

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

SSIRSFR

UART2

IrDA

D0D31

POR, RUN,

RESET, WAKEUP

EXPCLK, WORD,
CS[03], EXPRDY,
WRITE

MOE, MWE,
RAS[01], CAS[03]

A[027],
DRA[012]

LCD DRIVE

LED AND
PHOTODIODE

ASYNC
INTERFACE 2

GPIO

INTERNAL ADDRESS BUS

13-MHZ INPUT

ON-CHIP

BOOT ROM

ASYNC
INTERFACE 1

ON-CHIP SRAM

37.5 KBYTES

CL-PS6700

INTFC.

PB[01], CS[45]

EXPANSION

CONTROL

UART1

SSI2

APB BRIDGE

EPB BUS

RTC

FLASHING LED DRIVE

ICE-JTAG

TEST AND
DEVELOPMENT

WRITE

BUFFER

MULTIMEDIA

CODEC PORT

STATE CONTROL

MEMORY CONTROL BLOCK

LCD DMA

DC-TO-DC

DS352PP3

JUL 2001

High-Performance Ultra-Low-

Power System-on-Chip with

LCD Controller

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

DS352PP3

JUL 2001

OVERVIEW

(cont.)

FEATURES

(cont.)

Power Management

The EP7211 is designed for ultra-low-power opera-
tion. Its core operates at only 2.5 V, while its I/O has
an operating range of 2.5 V3.3 V. The device has
three basic power states:

Operating -- This state is the full performance

state. All the clocks and peripheral logic are
enabled.

Idle -- This state is the same as the Operating

State, except the CPU clock is halted while wait-
ing for an event such as a key press.

Standby -- This state is equivalent to the computer

being switched off (no display), and the main
oscillator shut down. An event such as a key
press can wake up the processor.

Memory Interfaces

There are two main external memory interfaces.

The first one is the ROM/SRAM/Flash-style interface
that has programmable wait-state timings and
includes burst-mode capability, with six chip selects
each decoding 256-Mbyte sections of addressable
space. For maximum flexibility, each bank can be
specified to be 8, 16, or 32 bits wide. This allows the
use of 8-bit-wide boot ROM options to minimize over-
all system cost. The on-chip boot ROM can be used
in product manufacturing to serially download system
code into system Flash memory. To further minimize
system memory requirements and cost, the ARM
Thumb

instruction set is supported, providing for the

ARM720T processor

-- ARM7TDMI CPU
-- 8 kbytes of four-way set-associative cache
-- MMU with 64-entry TLB (transition look aside buffer)
-- Write buffer
-- Windows

CE enabled

-- Thumb

code support enabled

DRAM controller

-- Supports both 16- and 32-bit-wide DRAMs
-- EDO support (fast page mode support for 13 MHz and

18 MHz operation only)

ROM/SRAM/FLASH memory control

-- Decodes 4, 5, or 6 separate memory segments of up to

256 Mbytes each

-- Each segment can be configured as 8, 16, or 32 bits

wide and supports page-mode access

-- Programmable access time for conventional

ROM/SRAM/Flash memory

37.5 kbytes of on-chip SRAM for fast program
execution and/or as a frame buffer

On-chip ROM; for manufacturing boot-up support

Four synchronous serial interfaces

-- ADC (SSI1) Interface: Master mode only; SPI

and

Microwire1

-compatible (128 kbps operation)

-- SSI2 Interface: Master/Slave mode; SPI/Microwire2

compatible (512 kbps operation)

-- Audio Codec Interface (64 kbps operation)
-- Multimedia Codec Port (Interfaces to Philips' UCB1100

and UCB1200 codecs) (9.216 Mbps operation)

27 bits of general-purpose I/O

-- Three 8-bit and one 3-bit GPIO port
-- Supports scanning keyboard matrix

Two UARTs (16550 type)

-- Supports bit rates up to 115.2 kbps
-- Contains two 16-byte FIFOs for TX and RX
-- UART1 supports modem control signals

SIR (up to 115.2 kbps) infrared encoder

-- IrDA (Infrared Data Association) SIR protocol encoder

can be optionally switched into TX and RX signals of
UART1

PWM interface

-- Provides two 96-kHz clock outputs with programmable

duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a DC-to-DC converter

Two timer counters

208-pin LQFP or 256-ball PBGA packages

Evaluation kit available with BOM, schematics,
sample code, and design database

Support for up to two ultra-low-power CL-PS6700
PC Card controllers

Dedicated LED flasher pin from RTC

Full JTAG boundary scan and Embedded ICE
support

SPI is a registered trademark of Motorola

Microwire is a registered trademark of National Semiconductor.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

OVERVIEW

(cont.)

DS352PP3
JUL 2001

use of high-speed 32-bit operations in 16-bit op-
codes and yielding industry-leading code density.

The second is the programmable 16- or 32-bit-wide
DRAM interface that allows direct connection of up to
two banks of DRAM, each bank containing up to 256
Mbytes. To assure the lowest possible power con-
sumption, the EP7211 supports self-refresh DRAMs,
which are placed in a low-power state by the device
when it enters the low-power Standby State. EDO
and Fast Page DRAM are supported.

A DMA address generator is also provided that
fetches video display frame buffer data for the LCD

controller from main memory (typically DRAM). The
display frame buffer start address is programmable.
In addition, the built-in LCD controller can utilize
external or internal SRAM for memory, thus eliminat-
ing the need for DRAMs.

Serial Interfaces

The EP7211 includes two 16550-type UARTs for RS-
232 serial communications, both of which have two
16-byte FIFOs for receiving and transmitting data.
The UARTs support bit rates up to 115.2 kbps. An
IrDA SIR protocol encoder/decoder can be optionally
switched into the RX/TX signals to/from one of the

LCD MODULE

KEYBOARD

BATTERY

DC-TO-DC

CONVERTERS

ADC

DIGITIZER

IR LED AND

PHOTODIODE

× RS-232

TRANSCEIVERS

ADDITIONAL I/O

CL-PS6700

PC CARD

CONTROLLER

PC CARD

SOCKET

CS[4]
PB0
EXPCLK

DD[3:0]

CL1
CL2

D[31:0]

A[27:0]

COL[7:0]

PA[7:0]

INPUT

MOE
WRITE

RAS[1]
RAS[0]

CAS[0]
CAS[1]

CAS[2]
CAS[3]

PB[7:0]

PD[7:0]

PE[2:0]

POR

PWRFL
BATOK

EXTPWR
BATCHG

RUN

WAKEUP

CS[0]
CS[1]

DRIVE[1:0]

FB[1:0]

EP721

ADCCLK

ADCCS

ADCOUT

ADCIN

SMPCLK

LEDDRV

PHDIN

RXD1/2

TXD1/2

DSR

CTS

DCD

CS[n]
WORD

CS[2]
CS[3]

×16

DRAM

×16

DRAM

×16

FLASH

×16

FLASH

×16

ROM

EXTERNAL MEMORY-
MAPPED EXPANSION

BUFFERS

AND

LATCHES

×16

ROM

×16

DRAM

×16

DRAM

POWER

SUPPLY UNIT

AND

COMPARATORS

CRYSTAL

CODEC

SSICLK

SSITXFR

SSITXDA

SSIRXDA

MOSCIN

Figure 1-1. A EP7211Based System

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information
describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained
in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express
or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This doc-
ument is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied,
reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written
consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may
be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior
written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent
of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of
their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

DS352PP3

JUL 2001

OVERVIEW

(cont.)

UARTs to enable these signals to drive an infrared
communication interface directly.

Four synchronous serial interfaces (codec, SSI1,
SSI2, and MCP) are provided. Three of them (codec,
SSI2, and MCP) are multiplexed onto a single set of
interface pins. The full-duplex codec interface allows
direct connection of a standard audio codec chip to
the EP7211, allowing storage and playback of sound.
SSI2 supports both master and slave mode. SSI1
supports master mode only. Both SSI1 and SSI2 sup-
port two industry-standard protocols (SPI

and

Microwire

) for interfacing standard devices (e.g.,

Max148/9 or AD7811/12 ADC), and for allowing
peripheral expansion (e.g., a digitizer pen). A Multi-
media Codec Port (MCP) can be used to communi-
cate with a multi-functional codec device like the
Philips

UCB1100.

Packaging

The EP7211 is available in a 208-pin LQFP package
and a 256-ball PBGA package.

System Design

As shown in system block diagram, simply adding
desired memory and peripherals to the highly
integrated EP7211 completes a low-power system
solution. All necessary interface logic is integrated
on-chip.

Development Boards

Cirrus Logic offers an evaluation and development
environment for the EP7211 in the form of the
EDB7211-2 Development Kit.

The EDB7211-2 development kit is a complete devel-
opment platform with access to the features and
capabilities of the EP7211. The kit provides the tools
required for developing and testing the design of a
highly integrated EP7211 system.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

DS352PP3
JUL 2001

TABLE OF CONTENTS

1. CONVENTIONS........................................................................................................................11

1.1

Acronyms and Abbreviations................................................................................................................... 11

1.2

Units of Measurement .............................................................................................................................12

1.3

General Conventions...............................................................................................................................12

1.4

Pin Description Conventions ...................................................................................................................12

2. PIN INFORMATION..................................................................................................................13

2.1

Pin Diagrams...........................................................................................................................................13

2.2

Pin Descriptions ......................................................................................................................................14
2.2.1

External Signal Functions...........................................................................................................15

2.3

256-Ball PBGA Ball Listing ......................................................................................................................20
2.3.1

PBGA Ground Connections .......................................................................................................25

2.4

208-Pin LQFP Pin Listing ........................................................................................................................26

2.5

JTAG Pin Ordering for 208-Pin LQFP Package ......................................................................................31

3. FUNCTIONAL DESCRIPTION.................................................................................................34

3.1

Main Functional Blocks ...........................................................................................................................35

3.2

CPU Core ................................................................................................................................................37

3.3

Interrupt Controller ..................................................................................................................................37
3.3.1

Interrupt Latencies in Different States ........................................................................................39
3.3.1.1

Operating State ..........................................................................................................39

3.3.1.2

Idle State ....................................................................................................................40

3.3.1.3

Standby State .............................................................................................................40

3.4

Memory and I/O Expansion Interface ......................................................................................................42

3.5

EP7211 Boot ROM ..................................................................................................................................43

3.6

CL-PS6700 PC Card Controller Interface ...............................................................................................44

3.7

DRAM Controller with EDO Support .......................................................................................................47

3.8

Serial Interfaces ......................................................................................................................................51
3.8.1

Codec Sound Interface...............................................................................................................52
3.8.1.1

Codec Interrupt Timing ...............................................................................................52

3.8.2

MCP Interface ............................................................................................................................53
3.8.2.1

MCP Operation ..........................................................................................................54

3.8.2.2

MCP Frame Format ...................................................................................................54

3.8.2.3

Audio and Telecom Sample Rates and Data Transfer ...............................................56

3.8.2.4

MCP FIFO Operation .................................................................................................58

3.8.2.5

MCP Codec Control Register Data Transfer ..............................................................59

3.8.3

ADC Interface -- Master Mode Only SSI1 (Synchronous Serial Interface) ...............................60

3.8.4

Master/Slave SSI2 (Synchronous Serial Interface 2) .................................................................61
3.8.4.1

Read Back of Residual Data ......................................................................................62

3.8.4.2

Support for Asymmetric Traffic ...................................................................................63

3.8.4.3

Continuous Data Transfer ..........................................................................................63

3.8.4.4

Discontinuous Clock...................................................................................................63

3.8.4.5

Error Conditions .........................................................................................................64

3.8.4.6

Clock Polarity .............................................................................................................64

3.9

LCD Controller with Support for On-Chip Frame Buffer ..........................................................................64

3.10 Internal UARTs (Two) and SIR Encoder ..................................................................................................67
3.11 Timer Counters........................................................................................................................................67

3.11.1 Free Running Mode....................................................................................................................68

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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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3.11.2 Prescale Mode ........................................................................................................................... 68

3.12 Realtime Clock ........................................................................................................................................ 68
3.13 Dedicated LED Flasher ........................................................................................................................... 68
3.14 Two PWM Interfaces ............................................................................................................................... 69
3.15 State Control............................................................................................................................................ 69
3.16 Resets ..................................................................................................................................................... 72
3.17 Clocks...................................................................................................................................................... 73

3.17.1 On-Chip PLL............................................................................................................................... 73
3.17.2 External Clock Input (13 MHz) ................................................................................................... 74

3.18 Dynamic Clock Switching When in the PLL Clocking Mode.................................................................... 75
3.19 Endianness.............................................................................................................................................. 75
3.20 Maximum EP7211-Based System ........................................................................................................... 77
3.21 Boundary Scan........................................................................................................................................ 78
3.22 In-Circuit Emulation ................................................................................................................................. 79

3.22.1 Introduction................................................................................................................................. 79
3.22.2 Functionality ............................................................................................................................... 79

4. MEMORY MAP .........................................................................................................................80

5. REGISTER DESCRIPTIONS ...................................................................................................81

5.1

Internal Registers .................................................................................................................................... 81
5.1.1

PADR Port A Data Register........................................................................................................ 85

5.1.2

PBDR Port B Data Register ....................................................................................................... 85

5.1.3

PDDR Port D Data Register ....................................................................................................... 85

5.1.4

PADDR Port A Data Direction Register ...................................................................................... 85

5.1.5

PBDDR Port B Data Direction Register......................................................................................85

5.1.6

PDDDR Port D Data Direction Register ..................................................................................... 85

5.1.7

PEDR Port E Data Register ....................................................................................................... 86

5.1.8

PEDDR Port E Data Direction Register......................................................................................86

5.2

SYSTEM Control Registers..................................................................................................................... 86
5.2.1

SYSCON1 The System Control Register 1 ................................................................................ 86

5.2.2

SYSCON2 System Control Register 2 ....................................................................................... 89

5.2.3

SYSCON3 System Control Register 3 ....................................................................................... 91

5.2.4

SYSFLG -- The System Status Flags Register ......................................................................... 92

5.2.5

SYSFLG2 System Status Register 2 .......................................................................................... 94

5.3

Interrupt Registers................................................................................................................................... 95
5.3.1

INTSR1 Interrupt Status Register 1 ............................................................................................ 95

5.3.2

INTMR1 Interrupt Mask Register 1............................................................................................. 97

5.3.3

INTSR2 Interrupt Status Register 2 ............................................................................................ 97

5.3.4

INTMR2 Interrupt Mask Register 2............................................................................................. 98

5.3.5

INTSR3 Interrupt Status Register 3 ............................................................................................ 98

5.3.6

INTMR3 Interrupt Mask Register 3............................................................................................. 99

5.4

Memory Configuration Registers............................................................................................................. 99
5.4.1

MEMCFG1 Memory Configuration Register 1............................................................................99

5.4.2

MEMCFG2 Memory Configuration Register 2..........................................................................100

5.4.3

DRFPR DRAM Refresh Period Register .................................................................................. 102

5.5

Timer/Counter Registers .......................................................................................................................103
5.5.1

TC1D Timer Counter 1 Data Register ...................................................................................... 103

5.5.2

TC2D Timer Counter 2 Data Register ...................................................................................... 103

5.5.3

RTCDR Realtime Clock Data Register..................................................................................... 103

5.5.4

RTCMR Realtime Clock Match Register .................................................................................. 103

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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JUL 2001

5.6

LEDFLSH Register................................................................................................................................104

5.7

PMPCON Pump Control Register .........................................................................................................105

5.8

CODR -- The CODEC Interface Data Register ....................................................................................106

5.9

UART Registers ....................................................................................................................................106
5.9.1

UARTDR12 UART12 Data Registers ...................................................................................106

5.9.2

UBRLCR12 UART12 Bit Rate and Line Control Registers...................................................107

5.10 LCD Registers .......................................................................................................................................108

5.10.1 LCDCON -- The LCD Control Register ...................................................................................108
5.10.2 PALLSW Least Significant Word -- LCD Palette Register....................................................... 110
5.10.3 PALMSW Most Significant Word -- LCD Palette Register ....................................................... 110
5.10.4 FBADDR LCD Frame Buffer Start Address .............................................................................. 111

5.11 SSI Register .......................................................................................................................................... 111

5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register ..................................................... 111

5.12 STFCLR Clear all `Start Up Reason' flags location ............................................................................... 113
5.13 `End Of Interrupt' Locations................................................................................................................... 113

5.13.1 BLEOI Battery Low End of Interrupt ......................................................................................... 113
5.13.2 MCEOI Media Changed End of Interrupt ................................................................................. 113
5.13.3 TEOI Tick End of Interrupt Location ......................................................................................... 113
5.13.4 TC1EOI TC1 End of Interrupt Location .................................................................................... 113
5.13.5 TC2EOI TC2 End of Interrupt Location .................................................................................... 113
5.13.6 RTCEOI RTC Match End of Interrupt ....................................................................................... 113
5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt ..................................................... 114
5.13.8 COEOI Codec End of Interrupt Location .................................................................................. 114
5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................................... 114
5.13.10 SRXEOF End of Interrupt Location .......................................................................................... 114

5.14 State Control Registers ......................................................................................................................... 114

5.14.1 STDBY Enter the Standby State Location ................................................................................ 114
5.14.2 HALT Enter the Idle State Location .......................................................................................... 114

5.15 SS2 Registers ....................................................................................................................................... 115

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ............................................................ 115
5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte .................................................. 115

5.16 MCP Register Definitions ...................................................................................................................... 115

5.16.1 MCP Control Register .............................................................................................................. 116

5.16.1.1 Audio Sample Rate Divisor (ASD) ........................................................................... 116
5.16.1.2 Telecom Sample Rate Divisor (TSD) ....................................................................... 117
5.16.1.3 Multimedia Communications Port Enable (MCE) ..................................................... 117
5.16.1.4 A/D Sampling Mode (ADM) ...................................................................................... 118
5.16.1.5 MCP Interrupt Generation ........................................................................................ 118
5.16.1.6 Telecom Transmit FIFO Interrupt Mask (TTM) ......................................................... 118
5.16.1.7 Telecom Receive FIFO Interrupt Mask (TRM) ......................................................... 118
5.16.1.8 Audio Transmit FIFO Interrupt Mask (ATM) ............................................................. 119
5.16.1.9 Audio Receive FIFO Interrupt Mask (ARM) ............................................................. 119
5.16.1.10 Loop Back Mode (LBM) ........................................................................................... 119

5.16.2 MCP Data Registers.................................................................................................................121

5.16.2.1 MCP Data Register 0 ...............................................................................................121
5.16.2.2 MCP Data Register 1 ...............................................................................................123
5.16.2.3 MCP Data Register 2 ...............................................................................................125

5.16.3 MCP Status Register ................................................................................................................127

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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5.16.3.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable

interrupt)................................................................................................................... 127

5.16.3.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt) . 127
5.16.3.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only,

maskable interrupt) .................................................................................................. 127

5.16.3.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable

interrupt)................................................................................................................... 128

5.16.3.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, non-maskable interrupt). 128
5.16.3.6 Audio Receive FIFO Overrun Status (ARO) (read/write, non-maskable interrupt)...128
5.16.3.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, non-maskable

interrupt)................................................................................................................... 128

5.16.3.8 Telecom Receive FIFO Overrun Status (TRO) (read/write, non-maskable

interrupt)................................................................................................................... 128

5.16.3.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only, non-interruptible) .................. 129
5.16.3.10 Audio Receive FIFO Not Empty Flag (ANE) (read-only, non-interruptible) .............. 129
5.16.3.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible) .............. 129
5.16.3.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, non-interruptible) .......... 129
5.16.3.13 Codec Write Completed Flag (CWC) (read-only, non-interruptible) ......................... 129
5.16.3.14 Codec Read Completed Flag (CRC) (read-only, non-interruptible).......................... 129
5.16.3.15 Audio Codec Enabled Flag (ACE) (read-only, non-interruptible).............................. 130
5.16.3.16 Telecom Codec Enabled Flag (TCE) (read-only, non-interruptible).......................... 130

6. ELECTRICAL SPECIFICATIONS......................................................................................... 133

6.1

Absolute Maximum Ratings................................................................................................................... 133

6.2

Recommended Operating Conditions ................................................................................................... 133

6.3

DC Characteristics ................................................................................................................................ 133

6.4

AC Characteristics................................................................................................................................. 135

6.5

I/O Buffer Characteristics ...................................................................................................................... 150

7. TEST MODES ........................................................................................................................ 151

7.1

Oscillator and PLL Bypass Mode ..........................................................................................................151

7.2

Oscillator and PLL Test Mode ............................................................................................................... 151

7.3

Debug/ICE Test Mode .......................................................................................................................... 152

7.4

Hi-Z (System) Test Mode...................................................................................................................... 152

7.5

Software Selectable Test Functionality................................................................................................. 152

8. PACKAGE SPECIFICATIONS.............................................................................................. 154

8.1

EP7211 256-Ball PBGA (17

× 17 × 1.53-mm Body) Dimensions ..........................................................154

8.2

208-Pin LQFP Package Outline Drawing .............................................................................................155

9. ORDERING INFORMATION ................................................................................................. 156

10. APPENDIX A: BOOT CODE................................................................................................. 157

11. INDEX..................................................................................................................................... 162

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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LIST OF TABLES

Table 2-1.

SSI/Codec/MCP Pin Multiplexing.................................................................................................... 18

Table 2-2.

256-Ball PBGA Ball Listing ............................................................................................................ 20

Table 2-3.

PBGA Balls to Connect to Ground (V

) ........................................................................................ 23

Table 2-4.

208-Pin LQFP Numeric Pin Listing ................................................................................................. 24

Table 2-5.

JTAG Pin Ordering for 208-Pin LQFP Package ............................................................................. 28

Table 3-1.

Interrupt Allocation in First Interrupt Register ................................................................................. 35

Table 3-2.

Interrupt Allocation in Second Interrupt Register ............................................................................ 36

Table 3-3.

Interrupt Allocation in Third Interrupt Register ................................................................................ 36

Table 3-4.

External Interrupt Source Latencies................................................................................................ 38

Table 3-5.

Boot Options ................................................................................................................................... 40

Table 3-6.

Chip Select Address Ranges After Boot From On-Chip Boot ROM ............................................... 40

Table 3-7.

CL-PS6700 Memory Map ............................................................................................................... 41

Table 3-8.

Space Field Decoding ..................................................................................................................... 42

Table 3-9.

Physical to DRAM Address Mapping .............................................................................................. 45

Table 3-10.

DRAM Address Mapping When Connected to an External 32-Bit DRAM Memory System ........... 46

Table 3-11.

DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System.............................................. 47

Table 3-12.

Serial Interface Options .................................................................................................................. 48

Table 3-13.

Serial-Pin Assignments................................................................................................................... 48

Table 3-14.

ADC Interface Operation Frequencies............................................................................................ 57

Table 3-15.

Peripheral Status in Different Power Management States .............................................................. 67

Table 3-16.

Effect of Endianness on Read Operations...................................................................................... 73

Table 3-17.

Effect of Endianness on Write Operations ...................................................................................... 73

Table 3-18.

Instructions Supported in JTAG Mode ............................................................................................ 75

Table 4-1.

EP7211 Memory Map ..................................................................................................................... 77

Table 5-1.

CL-PS7111-Compatible................................................................................................................... 79

Table 5-2.

Internal I/O Memory Locations (EP7211 Only) ............................................................................... 81

Table 5-3.

Port Byte Addresses in Big Endian Mode ....................................................................................... 81

Table 5-4.

Values of the Bus Width Field ......................................................................................................... 97

Table 5-5.

Values of the Wait State Field at 13 MHz and 18 MHz ................................................................... 98

Table 5-6.

Values of the Wait State Field at 36 MHz........................................................................................ 98

Table 5-7.

LED Flash Rates........................................................................................................................... 101

Table 5-8.

LED Duty Ratio ............................................................................................................................. 101

Table 5-9.

Sense of PWM control lines.......................................................................................................... 102

Table 5-10.

UART Bit Rates Running from the PLL Clock............................................................................... 104

Table 5-11.

UART Bit Rates Running from an External 13.0 MHz Clock ........................................................ 104

Table 5-12.

Grey Scale Value to Color Mapping.............................................................................................. 107

Table 5-13.

MCP Control Register ................................................................................................................... 117

Table 5-14.

MCP Data Register 0 .................................................................................................................... 120

Table 5-15.

MCP Data Register 1 .................................................................................................................... 121

Table 5-16.

MCP Data Register 2 .................................................................................................................... 123

Table 5-17.

MCP Control, Data and Status Register Locations ....................................................................... 128

Table 6-1.

DC Characteristics ........................................................................................................................ 130

Table 6-2.

AC Timing Characteristics ............................................................................................................ 132

Table 6-3.

Timing Characteristics .................................................................................................................. 133

Table 6-4.

I/O Buffer Output Characteristics .................................................................................................. 147

Table 7-1.

EP7211 Hardware Test Modes ..................................................................................................... 148

Table 7-2.

Oscillator and PLL Test Mode Signals .......................................................................................... 149

Table 7-3.

Software Selectable Test Functionality ......................................................................................... 150

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

DS352PP3

JUL 2001

LIST OF FIGURES

Figure 1-1.

A EP7211Based System................................................................................................................... 3

Figure 2-1.

208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ...............................................................13

Figure 2-2.

256-Ball Plastic Ball Grid Array Diagram .......................................................................................... 14

Figure 3-1.

EP7211 Block Diagram ..................................................................................................................... 37

Figure 3-2.

Codec Interrupt Timing ..................................................................................................................... 52

Figure 3-3.

Data Format of MCP Subframe 0 ..................................................................................................... 55

Figure 3-4.

MCP Packet Organization ................................................................................................................ 55

Figure 3-5.

Audio Codec Enable Timing ............................................................................................................. 57

Figure 3-6.

Format for the Audio and Telecom FIFOs.........................................................................................59

Figure 3-7.

SSI2 Port Directions in Slave and Master Mode............................................................................... 61

Figure 3-8.

Residual Byte Reading ..................................................................................................................... 63

Figure 3-9.

Video Buffer Mapping ....................................................................................................................... 66

Figure 3-10. State Diagram ................................................................................................................................... 72
Figure 3-11.

CLKEN Timing Entering the Standby State....................................................................................... 74

Figure 3-12. CLKEN Timing Leaving the Standby State ...................................................................................... 75
Figure 3-13. A Maximum EP7211 Based System ................................................................................................. 77
Figure 5-1.

MCP Data Register 0: MCDR0 ....................................................................................................... 122

Figure 5-2.

MCP Data Register 1: MCDR1 ....................................................................................................... 124

Figure 5-3.

MCP Data Register 2: MCDR2 ....................................................................................................... 126

Figure 5-4.

MCP Status Register: MCSR ......................................................................................................... 131

Figure 6-1.

Expansion and ROM Timing ........................................................................................................... 137

Figure 6-2.

Expansion and ROM Sequential Read Timings.............................................................................. 138

Figure 6-3.

Expansion and ROM Write Timings ................................................................................................ 139

Figure 6-4.

DRAM Read Cycles at 13 MHz and 18.432 MHz ........................................................................... 140

Figure 6-5.

DRAM Read Cycles at 36 MHz ...................................................................................................... 141

Figure 6-6.

DRAM Write Cycles at 13 MHz and 18 MHz .................................................................................. 142

Figure 6-7.

DRAM Write Cycles at 36 MHz....................................................................................................... 143

Figure 6-8.

Video Quad Word Read from DRAM at 13 MHz and 18 MHz ........................................................ 144

Figure 6-9.

Quad Word Read from DRAM at 36 MHz.......................................................................................145

Figure 6-10. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz.................................................... 146
Figure 6-11.

DRAM CAS Before RAS Refresh Cycle at 36 MHz ........................................................................ 147

Figure 6-12. LCD Controller Timings................................................................................................................... 148
Figure 6-13. SSI Interface for AD7811/2 ............................................................................................................. 148
Figure 6-14. SSI Timing Interface for MAX148/9 ................................................................................................ 149
Figure 6-15. SSI2 Interface Timings.................................................................................................................... 149

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Conventions

DS352PP3
JUL 2001

CONVENTIONS

This section presents acronyms, abbreviations, units of measurement, and conventions used in this
data book.

1.1

Acronyms and Abbreviations

The following table lists abbreviations and acronyms used in this data book.

Acronym/

Abbreviation

Definition

alternating current

A/D

analog-to-digital

ADC

analong-to-digital converter

codec

coder/decoder

CMOS

complementary metal oxide
semiconductor

CPU

central processing unit

D/A

digital-to-analog

direct current

DMA

direct-memory access

DRAM

dynamic random access memory

EPB

embedded peripheral bus

FCS

frame check sequence

FIFO

first in/first out

GPIO

general purpose I/O

ICT

in circuit test

infrared

IrDA

Infrared Data Association

JTAG

Joint Test Action Group

LCD

liquid crystal display

LED

light-emitting diode

LSB

least significant bit

Acronym/

Abbreviation

Definition

MIPS

millions of instructions per second

LQFP

low profile quad flat pack

MMU

memory management unit

MSB

most significant bit

PBGA

plastic ball grid array

PCB

printed circuit board

PDA

personal digital assistant

PIA

peripheral interface adapter

PLL

phase locked loop

PSU

power supply unit

p/u

pull-up resistor

RAM

random access memory

RISC

reduced instruction set computer

ROM

read-only memory

RTC

realtime clock

SIR

slow (9600115.2 kbps) infrared

SRAM

static random access memory

SSI

synchronous serial interface

TAP

test access port

TLB

translation look aside buffer

UART

universal asynchronous receiver
transmitter

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Conventions

DS352PP3

JUL 2001

1.2

Units of Measurement

1.3

General Conventions

Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For
example, 14h and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation
marks when in text (for example, `11' designates a binary number). Numbers not indicated by an h
or quotation marks are decimal.

Registers are referred to by acronym, as listed in the tables on the previous page, with bits listed in
brackets MSB-to-LSB separated by a colon (:) (for example, CODR[7:0]), or LSB-to-MSB
separated by a hyphen (for example, CODR[02]).

The use of `tbd' indicates values that are `to be determined', `n/a' designates `not available', and
`n/c' indicates a pin that is a `no connect'.

1.4

Pin Description Conventions

Abbreviations used for signal directions in Section 2 are listed in the following table:

Abbreviation

Direction

Input

Output

I/O

Input or Output

Symbol

Unit of Measure

degree Celsius

hertz (cycle per second)

kbits/s

kilobits per second

kbyte

kilobyte (1,024 bytes)

kHz

kilohertz

kilohm

Mbps

megabits (1,048,576 bits) per second

Mbyte

megabyte (1,048,576 bytes)

MHz

megahertz (1,000 kilohertz)

µA

microampere

µF

microfarad

µW

microwatt

µs

microsecond (1,000 nanoseconds)

milliampere

milliwatt

millisecond (1,000 microseconds)

nanosecond

volt

watt

Symbol

Unit of Measure

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

PIN INFORMATION

2.1

Pin Diagrams

Figure 2-1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

160

159

158

157

100

101

102

103

104

161
162
163
164
165
166
167
168
169
170
171
172
173
174

180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199

201
202
203
204
205
206
207
208

200

175
176
177
178
179

111

EP7211

208-Pin LQFP

(Top View)

DCH

/
N

VSSOSC

VDDOSC

MOSCIN

MOSCOUT

NURE

WAKEUP

A[6]

D[6]

A[5]

D[5]

VDDIO

VSSIO

A[4]

D[4]

A[3]

D[3]

NPWRFL

A[2]

D[2]

A[1]

A[0]

D[0]

VDDCORE

VSSIO

VDDIO

CL[2]
CL[1]

FRM

DD[2]

DD[1]
DD[0]

NRAS[1]

NCAS[3]
NCAS[2]

VDDIO

VSSIO

NCAS[0]

NMWE

NMOE

NCS[0]
NCS[1]
NCS[2]
NCS[3]

D[7

]

D[8

]

D[9

]

D[1

]

[
10]

DDIO

[
11]

D[1

]

[
12]

D[1

]

[
13]

D[1

]

DD[3]

D[1

]

D[1

]

[
17]

/DRA

[10]

DDIO

D[1

]

[
18]

/DRA

[9]

D[1

]

[
19]

/DRA

[8]

D[2

]

[
21]

/DRA

[6]

D[2

]

D[2

]

[
23]

/DRA

[4]

D[2

]

DDIO

[
24]

/DRA

[3]

[
14]

A[25]/DRA[2]

D[25]

D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]

ADCOUT
ADCCLK
DRIVE[0]

VDDIO

PD[2]

VSSIO

VSSCORE
NADCCS
ADCIN

SSIRXDA

SSIRXFR

SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]

PD[3]

[
22]

/DRA

[5]

PD[4]

VDDIO

PD[5]
PD[6]

DRIVE[1]

PD[7]

D[26]

[
15]

/DRA

[12]

D[1

]

[
16]

/DRA

[11]

NCS[4]

VDDCORE

A[26]/DRA[1]

D[2

]

TMS

[
20]

/DRA

[7]

SMPCLK

D[1

]

D[1]

VSSCORE

NRAS[0]

NCAS[1]

VSSIO

WOR

I
T

UN/CL

[
7

]

[
6

]

[
5

]

[
4

]

[
3

]

[
2

]

[1]/

RDY

[2]

DDIO

[
2

]
/
C

TFIQ

[
6

]

[
5

]

[
4

]

[
3

]

[
2

]

[
1

]

[
0

]

DDRV

[
2

]

I
N

D[2]

I
N

[
7

]

DDIO

NCS

[5]

[0]/

RDY

[1]

[
1

]

[
1]

[
0]

[
3

]

I
N

[
2]

I
N

[
1]

PE[

]
BO

[
1

]

PE[

]
BO

[
0

]

DRT

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

2.2.1

External Signal Functions

Function

Signal
Name

Signal

Description

Data bus

D[031]

I/O

32-bit system data bus for DRAM, ROM/SRAM/Flash, and memory mapped
I/O expansion

Address bus

A[014]

Least significant 15 bits of system byte address during ROM/SRAM/Flash and
expansion cycles

A[15]/

DRA[12]

A[27]/DRA[0]

13-bit multiplexed DRAM word address during DRAM cycles or address bits
16 to 27 of system byte address during ROM/SRAM/Flash and expansion
cycles
Whenever the EP7211 is in the Standby State, the external address and
data buses are driven low. The RUN signal is used internally to force these
buses to be driven low. This is done to prevent peripherals that are power-
down from draining current. Also, the internal peripheral's signals get set to

their Reset State

For additional power saving, the multiplexed DRAM address lines are output
on the high order ROM address lines where the lightest loading is expected.

Memory and

Expansion

Interface

NRAS[01]

DRAM RAS outputs to DRAM banks 0 to 1

NCAS[03]

I/O

DRAM CAS outputs for bytes 0 to 3 within 32-bit word

NMOE

DRAM, ROM/SRAM/Flash, and expansion output enable

NMWE

DRAM, ROM/SRAM/Flash, and expansion write enable

NCS[03]

Expansion channel I/O strobes; active low SRAM-like chip selects for expan-
sion

NCS[45]

Expansion channel I/O strobes; active low CS for expansion or for
CL-PS6700 select

EXPRDY

I/O

Expansion channel ready; external expansion devices drive this low to extend
the bus cycle

WRITE

Transfer direction, low during reads, high during writes from the
EP7211

WORD

Word access enable; driven high during word-wide cycles, low during byte-
wide cycles

HALFWORD

Half-Word access flag; driven high to denote upper half-word accesses

EXPCLK

I/O

Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It
runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is
used as the clock input

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

Interrupts

NMEDCHG/

BROM

Media changed input; active low, deglitched -- it is used as a general purpose
FIQ interrupt during normal operation. It is also used on power up to configure
the processor to either boot from the internal Boot ROM, or from external
memory. When low, the chip will boot from the internal Boot ROM.

NEXTFIQ

External active low fast interrupt request input

EINT3

External active high interrupt request input

NEINT[12]

Two general purpose, active low interrupt inputs

Power

Management

NPWRFL

Power fail input; active low deglitched input to force system into the Standby
State

BATOK

Main battery OK input; falling edge generates a FIQ, a low level in the Standby
State inhibits system start up; deglitched input

NEXTPWR

External power sense; must be driven low if the system is powered by an
external source

NBATCHG

New battery sense; driven low if battery voltage falls below the "no-battery"
threshold; it is a deglitched input

State Control

NPOR

Power-on reset input; active low input completely resets the entire system;
must be held active for at least two clock cycles to be detected cleanly

RUN/CLKEN

This pin is programmed to either output the RUN signal or the CLKEN signal.
The CLKENSL bit is used to configure this pin. When RUN is selected, the pin
will be high when the system is active or idle, low while in the Standby State.
When CLKEN is selected, the pin will only be driven low when in the Standby
State.

WAKEUP

Wake up deglitched input signal; rising edge forces system into the Operating
State; active after a power-on reset

NURESET

User reset input; active low deglitched input from user reset button.
This pin is also latched upon the rising edge of NPOR and read along with the
input pins NTEST[01] to force the device into special test modes.

MCP, Codec or

SSI2

Interface

(See Note)

SSICLK

I/O

MCP/Codec/SSI2 clock signal

SSITXFR

I/O

MCP/Codec/SSI2 serial data output frame/synchronization pulse output

SSITXDA

MCP/Codec/SSI2 serial data output

SSIRXDA

MCP/Codec/SSI2 serial data input

SSIRXFR

I/O

SSI2 serial data input frame/synchronization pulse

Function

Signal
Name

Signal

Description

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

ADC

Interface

(SSI1)

ADCCLK

Serial clock output

NADCCS

Chip select for ADC interface

ADCOUT

Serial data output

ADCIN

Serial data input

SMPCLK

Sample clock output

IrDA and

RS232

Interfaces

LEDDRV

Infrared LED drive output (UART1)

PHDIN

Photo diode input (UART1)

TXD[12]

RS232 UART1 and 2 TX outputs

RXD[12]

RS232 UART1 and 2 RX inputs

DSR

RS232 DSR input

DCD

RS232 DCD input

CTS

RS232 CTS input

LCD

DD[03]

I/O

LCD serial display data; pins can be used on power up to read the ID of some
LCD modules

CL1

LCD line clock

CL2

LCD pixel clock

FRM

LCD frame synchronization pulse output

LCD AC bias drive

Keyboard &

Buzzer drive
LED Flasher

COL[07]

Keyboard column drives

BUZ

Buzzer drive output

PD[0]/

LEDFLSH

LED flasher driver -- multiplexed with Port D Bit 0. This pin can provide up to
4 mA of drive current.

General

Purpose I/O

PA[07]

I/O

Port A I/O (Bit 6 for boot clock option, Bit 7 for CL-PS6700 PRDY input); also
used as keyboard row inputs

PB[0]/PRDY1

I/O

Port B I/O. All eight Port B bits can be used as GPIOs.

PB[1]/PRDY2

PB[27]

When the PC CARD1 or 2 control bits in the SYSCON2 register are de-
asserted, PB[0] and PB[1] are available for GPIO. When asserted, these port
bits are used as the PRDY signals for connected
CL-PS6700 PC Card Host Adapter devices.

PD[07]

I/O

Port D I/O

Function

Signal
Name

Signal

Description

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

NOTE:

See table below for pin assignment and direction following pin multiplexing.

* p/u = use an ~10 k pull-up

PE[0]/

BOOTSEL0

I/O

Port E I/O (3 bits only). Can be used as general purpose I/O during normal
operation.

PE[1]/

BOOTSEL1

I/O

During power-on reset, PE[0] and PE[1] are inputs and are latched by the ris-
ing edge of NPOR to select the memory width that the
EP7211 will use to read from the boot code storage device (e.g., external 8-bit-
wide Flash bank).

PE[2]/

CLKSEL

I/O

During power-on reset, PE[2] is latched by the rising edge of NPOR to select
the clock mode of operation (i.e., either the PLL or external
13 MHz clock mode).

PWM

Drives

DRIVE[01]

I/O

PWM drive outputs. These pins are inputs on power up to determine what
polarity the output of the PWM should be when active. Otherwise, these pins
are always an output.

FB[01]

PWM feedback inputs

Boundary

Scan

TDI

JTAG data in

TDO

JTAG data out

TMS

JTAG mode select

TCLK

JTAG clock

TNRST

JTAG async reset

Test

NTEST[01]

Test mode select inputs. These pins are used in conjunction with the power-on
latched state of NURESET.

Oscillators

MOSCIN

MOSCOUT

RTCIN

RTCOUT

Main 3.6864 MHz oscillator for 18.432MHz73.728 MHz PLL

Realtime clock 32.768 kHz oscillator

Table 2-1. SSI/Codec/MCP Pin Multiplexing

SSI2

Codec

MCP

Direction

Strength

SSICCLK PCMCLK

SIBCLK

I/O 1

SSITXFR

PCMSYNC

SIBSYNC

I/O

SSITXDA

PCMOUT

SIBDOUT

Output

SSIRXDA

PCMIN

SIBDIN

Input

SSIRXFR

p/u*

I/O

Function

Signal
Name

Signal

Description

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

2.3

256-Ball PBGA Ball Listing

Table 2-2. 256-Ball PBGA Ball Listing

Ball

Location

Name

Type

VDDIO

Pad power

NCS[4]

NCS[1]

NCAS[0]

NCAS[3]

DD[1]

VDDIO

Pad power

D[0]

I/O

A10

D[2]

I/O

A11

A[3]

A12

VDDIO

Pad power

A13

A[6]

A14

MOSCOUT

A15

VDDOSC

Oscillator power

A16

VSSIO

Pad ground

NCS[5]

VDDIO

Pad power

NCS[3]

NMOE

VDDIO

Pad power

NRAS[1]

DD[2]

CL[1]

VDDCORE

Core power

B10

D[1]

I/O

B11

A[2]

B12

A[4]

B13

A[5]

B14

WAKEUP

B15

VSSIO

Pad ground

B16

NURESET

VDDIO

Pad

power

EXPCLK

VSSIO

Pad ground

VDDIO

Pad power

VSSIO

Pad ground

VSSIO

Pad ground

VSSIO

Pad ground

VDDIO

Pad power

VSSIO

Pad ground

C10

VSSIO

Pad ground

C11

VSSIO

Pad ground

C12

VDDIO

Pad power

C13

VSSIO

Pad ground

C14

VSSIO

Pad ground

C15

NPOR

C16

NEXTPWR

WRITE

EXPRDY

VSSIO

Pad ground

VDDIO

Pad power

NCS[2]

NMWE

NRAS[0]

CL[2]

VSSCORE

Core ground

D10

D[4]

I/O

D11

NPWRFL

Table 2-2.

(cont.)

256-Ball PBGA Ball Listing

Ball

Location

Name

Type

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

PB[2]

VSSRTC

RTC ground

VSSRTC

RTC ground

H10

A[10]

H11

A[11]

H12

A[12]

H13

A[13]

H14

VSSIO

Pad ground

H15

D[14]

I/O

H16

D[15]

I/O

PA[3]

PA[1]

VSSIO

Pad ground

PA[2]

PA[0]

TXD[1]

CTS

VSSRTC

RTC ground

VSSRTC

RTC ground

J10

A[17]/DRA[10]

J11

A[16]/DRA[11]

J12

A[15]/DRA[12]

J13

A[14]

J14

TNRST

J15

D[16]

I/O

J16

D[17]

I/O

LEDDRV

PHDIN

VSSIO

Pad ground

DCD

Table 2-2.

(cont.)

256-Ball PBGA Ball Listing

Ball

Location

Name

Type

NTEST[1]

EINT[3]

VSSRTC

RTC ground

ADCIN

COL[4]

K10

TCLK

K11

D[20]

I/O

K12

D[19]

I/O

K13

D[18]

I/O

K14

VSSIO

Pad ground

K15

VDDIO

Pad power

K16

VDDIO

Pad power

RXD[1]

DSR

VDDIO

Pad power

NEINT[1]

PE[2]/CLKSEL

VSSRTC

RTC ground

PD[0]/LEDFLSH

I/O

VSSCORE

Core ground

COL[6]

L10

D[31]

I/O

L11

VSSRTC

RTC ground

L12

A[22]/DRA[5]

L13

A[21]/DRA[6]

L14

VSSIO

Pad ground

L15

A[18]/DRA[9]

L16

A[19]/DRA[8]

NTEST[0]

NEINT[2]

Table 2-2.

(cont.)

256-Ball PBGA Ball Listing

Ball

Location

Name

Type

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

VDDIO

Pad power

PE[0]/BOOTSEL[0]

TMS

VDDIO

Pad power

SSITXFR

I/O

DRIVE[1]

I/O

FB[0]

M10

COL[0]

M11

D[27]

I/O

M12

VSSIO

Pad ground

M13

A[23]/DRA[4]

M14

VDDIO

Pad power

M15

A[20]/DRA[7]

M16

D[21]

I/O

NEXTFIQ

PE[1]/BOOTSEL[1]

VSSIO

Pad ground

VDDIO

Pad power

PD[5]

I/O

PD[2]

I/O

SSIRXDA

I/O

ADCCLK

SMPCLK

N10

COL[2]

N11

D[29]

I/O

N12

D[26]

I/O

N13

HALFWORD

N14

VSSIO

Pad ground

N15

D[22]

I/O

N16

D[23]

I/O

Table 2-2.

(cont.)

256-Ball PBGA Ball Listing

Ball

Location

Name

Type

VSSRTC

32 K oscillator

ground

RTCOUT

VSSIO

Pad ground

VSSIO

Pad ground

VDDIO

Pad power

VSSIO

Pad ground

VSSIO

Pad ground

VDDIO

Pad power

VSSIO

Pad ground

P10

VDDIO

Pad power

P11

VSSIO

Pad ground

P12

VSSIO

Pad ground

P13

VDDIO

Pad power

P14

VSSIO

Pad ground

P15

D[24]

I/O

P16

VDDIO

Pad power

RTCIN

VDDIO

Pad power

PD[4]

I/O

PD[1]

I/O

SSITXDA

NADCCS

VDDIO

Pad

power

ADCOUT

COL[7]/PTOUT

R10

COL[3]

R11

COL[1]

R12

D[30]

I/O

R13

A[27]/DRA[0]

Table 2-2.

(cont.)

256-Ball PBGA Ball Listing

Ball

Location

Name

Type

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

2.4

208-Pin LQFP Pin Listing

Table 2-3. 208-Pin LQFP Numeric Pin Listing

Pin
No.

Signal

Type

Strength

Reset

State

Pin
No.

Signal

Type

Strength

Reset

State

NCS[5]

Out

Low

PA[3]

I/O

Input

VDDIO

Pad Pwr

PA[2]

I/O

Input

VSSIO

Pad Gnd

PA[1]

I/O

Input

EXPCLK

I/O

PA[0]

I/O

Input

WORD

Out

Low

LEDDRV

Out

Low

WRITE

Out

Low

TXD[1]

Out

High

RUN/CLKEN

I/O 1

Low

VSSIO

Pad

Gnd

High

EXPRDY

I/O

PHDIN

TXD[2]

Out

1 High

CTS

RXD[2]

RXD[1]

TDI

with p/u*

DCD

VSSIO

Pad Gnd

DSR

PB[7]

I/O

Input

NTEST[1]

With p/u*

High

PB[6]

I/O

Input

NTEST[0]

With p/u*

High

PB[5]

I/O

Input

EINT[3]

PB[4]

I/O

Input

NEINT[2]

PB[3]

I/O

Input

NEINT[1]

PB[2]

I/O

Input

NEXTFIQ

PB[1]/

PRDY[2]

I/O

Input

PE[2]/

CLKSEL

I/O

1 Input

PB[0]/

PRDY[1]

I/O

Input

PE[1]/

BOOTSEL[1]

I/O

Input

VDDIO

Pad Pwr

PE[0]/

BOOTSEL[0]

I/O

Input

TDO

Out

Tristate

VSSRTC

VDDRTC

VSSRTC

32 K Osc

Gnd

PA[7]

I/O

Input

RTCOUT

32 K Osc

PA[6]

I/O

Input

RTCIN

32 K Osc

PA[5]

I/O

Input

VDDRTC

32 K Osc

power

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

PA[4]

I/O

Input

PD[7]

I/O

Low

FB[1]

PD[6]

I/O

Low

VSSIO

Pad Gnd

PD[5]

I/O

Low

FB[0]

PD[4]

I/O

Low

COL[7]

Out

High

VDDIO

Pad Pwr

COL[6]

Out

High

TMS

with p/u*

COL[5]

Out

High

PD[3]

I/O

Low

COL[4]

Out

High

PD[2]

I/O

Low

COL[3]

Out

High

PD[1]

I/O

Low

COL[2]

Out

High

PD[0]/

LEDFLSH

I/O

Low

VDDIO

Pad Pwr

SSICLK

I/O

Input

TCLK

VSSIO

Pad Gnd

COL[1]

Out

High

SSITXFR

I/O

Low

COL[0]

Out

High

SSITXDA

Out

Low

BUZ

Out

Low

SSIRXDA

D[31]

I/O

Low

SSIRXFR

I/O

Input

D[30]

I/O

Low

ADCIN

D[29]

I/O

Low

NADCCS

Out

High

D[28]

I/O

Low

VSSCORE

VSSCO
REVDD

COREC
ore Gnd

VSSIO

Pad Gnd

VDDCORE

Core

Pwr

A[27]/DRA[0]

Out

Low

VSSIO

Pad Gnd

100

D[27]

I/O

Low

VDDIO

Pad Pwr

101

A[26]/DRA[1]

Out

Low

DRIVE[1]

I/O 1

High/

Low

102

D[26]

I/O

Low

DRIVE[0]

I/O 1

High/

Low

103

A[25]/DRA[2]

Out

Low

ADCCLK

Out

Low

104

D[25]

I/O

Low

Table 2-3. 208-Pin LQFP Numeric Pin Listing

(cont.)

Pin
No.

Signal

Type

Strength

Reset

State

Pin
No.

Signal

Type

Strength

Reset

State

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

ADCOUT

Out

105

HALFWORD

Out

Low

SMPCLK

Out

106

A[24]/DRA[3]

Out

Low

107

VDDIO

Pad Pwr

134

A[13]

Out

Low

108

VSSIO

Pad Gnd

135

D[13]

I/O

Low

109

D[24]

I/O

Low

136

A[12]

Out

Low

110

A[23]/DRA[4]

Out

Low

137

D[12]

I/O

Low

111

D[23]

I/O

Low

138

A[11]

Out

Low

112

A[22]/DRA[5]

Out

Low

139

VDDIO

Pad Pwr

113

D[22]

I/O

Low

140

VSSIO

Pad Gnd

114

A[21]/DRA[6]

Out

Low

141

D[11]

I/O

Low

115

D[21]

I/O

Low

142

A[10]

Out

Low

116

VSSIO

Pad Gnd

143

D[10]

I/O

Low

117

A[20]/DRA[7]

Out

Low

144

A[9]

Out

Low

118

D[20]

I/O

Low

145

D[9]

I/O

Low

119

A[19]/DRA[8]

Out

Low

146

A[8]

Out

Low

120

D[19]

I/O

Low

147

D[8]

I/O

Low

121

A[18]/DRA[9]

Out

Low

148

A[7]

Out

Low

122

D[18]

I/O

Low

149

VSSIO

Pad Gnd

123

VDDIO

Pad Pwr

150

D[7]

I/O

Low

124

VSSIO

Pad Gnd

151

NBATCHG

125

TNRST

152

NEXTPWR

126

A[17]/

DRA[10]

Out

Low

153

BATOK

127

D[17]

I/O

Low

154

NPOR

Schmitt

128

A[16]/

DRA[11]

Out

Low

155

NMEDCHG/

NBROM

129

D[16]

I/O

Low

156

NURESET

Schmitt

130

A[15]/

DRA[12]

Out

Low

157

VDDOSC

VSSOSC

Osc Pwr

131

D[15]

I/O

Low

158

MOSCIN

3M6864

Osc

Table 2-3. 208-Pin LQFP Numeric Pin Listing

(cont.)

Pin
No.

Signal

Type

Strength

Reset

State

Pin
No.

Signal

Type

Strength

Reset

State

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

132

A[14]

Out

Low

159

MOSCOUT

3M6864

Osc

133

D[14]

I/O

Low

160

VSSOSC

VSSOSC
VSSCOR

EOsc

Gnd

161

WAKEUP

Schmitt

Input

185

CL[1]

Out

Low

162

NPWRFL

Input

186

FRM

Out

Low

163

A[6]

Out

Low

187

Out

Low

164

D[6]

I/O

Low

188

DD[3]

I/O

Low

165

A[5]

Out

Low

189

DD[2]

I/O

Low

166

D[5]

I/O

Low

190

VSSIO

VSSIOV

DDIOPad

Gnd

167

VDDIO

Pad Pwr

191

DD[1]

I/O

Low

168

VSSIO

Pad Gnd

192

DD[0]

I/O

Low

169

A[4]

Out

Low

193

NRAS[1]

Out

High

170

D[4]

I/O

Low

194

NRAS[0]

Out

High

171

A[3]

Out

Low

195

NCAS[3]

I/O

High

172

D[3]

I/O

Low

196

NCAS[2]

I/O

High

173

A[2]

Out

Low

197

VDDIO

Pad Pwr

174

VSSIO

Pad Gnd

198

VSSIO

Pad Gnd

175

D[2]

I/O

Low

199

NCAS[1]

I/O

High

176

A[1]

Out

Low

200

NCAS[0]

I/O

2 High

177

D[1]

I/O

Low

201

NMWE

Out

High

178

A[0]

Out

Low

202

NMOE

Out

High

179

D[0]

I/O

Low

203

VSSIO

Pad Gnd

180

VSSCORE

Core

Gnd

204

NCS[0]

Out

High

181

VDDCORE

VDDCO

REVDD

RTCCor

e Pwr

205

NCS[1]

Out

High

182

VSSIO

Pad Gnd

206

NCS[2]

Out

High

183

VDDIO

Pad Pwr

207

NCS[3]

Out

High

Table 2-3. 208-Pin LQFP Numeric Pin Listing

(cont.)

Pin
No.

Signal

Type

Strength

Reset

State

Pin
No.

Signal

Type

Strength

Reset

State

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

2.5

JTAG Pin Ordering for 208-Pin LQFP Package

Table 2-4. JTAG Pin Ordering for 208-Pin LQFP Package

Pin
No.

Signal

Type

Position

Pin
No.

Signal

Type

Position

NCS[5]

Out

PHDIN

EXPCLK

I/O

CTS

WORD

Out

RXD1

WRITE

Out

DCD

RUN/CLKEN

I/O

DSR

EXPRDY

I/O

NTEST1

TXD2

Out

NTEST0

RXD2

EINT3

PB[7]

I/O

NEINT2

PB[6]

I/O

NEINT1

PB[5]

I/O

NEXTFIQ

PB[4]

I/O

PE[2]/CLKSEL

I/O

PB[3]

I/O

PE[1]/

BOOTSEL1

I/O

PB[2]

I/O

PE[0]/

BOOTSEL0

I/O

PB[1]/

PRDY2

I/O

PD[7]

I/O

PB[0]/

PRDY1

I/O

PD[6]

I/O

PA[7]

I/O

PD[5]

I/O

PA[6]

I/O

PD[4]

I/O

PA[5]

I/O

PD[3]

I/O

101

PA[4]

I/O

PD[2]

I/O

104

PA[3]

I/O

PD[1]

I/O

107

PA[2]

I/O

PD[0]/

LEDFLSH

I/O

110

PA[1]

I/O

SSICCLK

I/O

113

PA[0]

I/O

SSITXFR

I/O

116

LEDDRV

Out

SSITXDA

Out

119

TXD1

Out

SSIRXDA

121

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3
JUL 2001

SSIRXFR

Out

122

105

HALF

WORD

Out

187

ADCIN

125

106

A[24]/DRA[3]

Out

189

NADCCS

Out

126

109

D[24]

I/O

191

DRIVE1

I/O

128

110

A[23]/DRA[4]

Out

194

DRIVE0

I/O

131

111

D[23]

I/O

196

ADCCLK

Out

134

112

A[22]/DRA[5]

Out

199

ADCOUT

Out

136

113

D[22]

I/O

201

SMPLCK

Out

138

114

A[21]/DRA[6]

Out

204

FB1

140

115

D[21]

I/O

206

FB0

141

117

A[20]/DRA[7]

Out

209

COL7

Out

142

118

D[20]

I/O

211

COL6

Out

144

119

A[19]/DRA[8]

Out

214

COL5

Out

146

120

D[19]

I/O

216

COL4

Out

148

121

A[18]/DRA[9]

Out

219

COL3

Out

150

122

D[18]

I/O

221

COL2

Out

152

126

A[17]/DRA[10]

Out

224

COL1

Out

154

127

D[17]

I/O

226

COL0

Out

156

128

A[16]/DRA[11]

Out

229

BUZ

Out

158

129

D[16]

I/O

231

D[31]

I/O

160

130

A[15]/DRA[12]

Out

234

D[30]

I/O

163

131

D[15]

I/O

236

D[29]

I/O

166

132

A[14]

Out

239

D[28]

I/O

169

133

D[14]

I/O

241

A[27]/DRA[0]

Out

172

134

A[13]

Out

244

100

D[27]

I/O

174

135

D[13]

I/O

246

101

A[26]/DRA[1]

Out

177

136

A[12]

Out

249

102

D[26]

I/O

179

137

D[12]

I/O

251

103

A[25]/DRA[2]

Out

182

138

A[11]

Out

254

104

D[25]

I/O

184

141

D[11]

I/O

256

Table 2-4. JTAG Pin Ordering for 208-Pin LQFP Package

(cont.)

Pin
No.

Signal

Type

Position

Pin
No.

Signal

Type

Position

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Pin Information

DS352PP3

JUL 2001

NOTE:

1)See Table 2-1. SSI/Codec/MCP Pin Multiplexing for pin naming/functionality.

2)For each pad, the JTAG connection ordering is input, output, then enable as applicable.

142

A[10]

Out

259

176

A[1]

Out

312

143

D[10]

I/O

261

177

D[1]

I/O

314

144

A[9]

Out

264

178

A[0]

Out

317

145

D[9]

I/O

266

179

D[0]

I/O

319

146

A[8]

Out

269

184

CL2

Out

322

147

D[8]

I/O

271

185

CL1

Out

324

148

A[7]

Out

274

186

FRM

Out

326

150

D[7]

I/O

276

187

Out

328

151

NBATCHG

279

188

DD[3]

I/O

330

152

NEXTPWR

280

189

DD[2]

I/O

333

153

BATOK

281

191

DD[1]

I/O

336

154

NPOR

282

192

DD[0]

I/O

339

155

NMEDCHG/

BROM

283

193

NRAS[1]

Out

342

156

NURESET

284

194

NRAS[0]

Out

344

161

WAKEUP

285

195

NCAS[3]

I/O

346

162

NPWRFL

286

196

NCAS[2]

I/O

349

163

A[6]

Out

287

199

NCAS[1]

I/O

352

164

D[6]

I/O

289

200

NCAS[0]

I/O

355

165

A[5]

Out

292

201

NMWE

Out

358

166

D[5]

I/O

294

202

NMOE

Out

360

169

A[4]

Out

297

204

NCS[0]

Out

362

170

D[4]

I/O

299

205

NCS[1]

Out

364

171

A[3]

Out

302

206

NCS[2]

Out

366

172

D[3]

I/O

304

207

NCS[3]

Out

368

173

A[2]

Out

307

208

NCS[4]

Out

370

175

D[2]

I/O

309

Table 2-4. JTAG Pin Ordering for 208-Pin LQFP Package

(cont.)

Pin
No.

Signal

Type

Position

Pin
No.

Signal

Type

Position

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Functional Description

DS352PP3
JUL 2001

FUNCTIONAL DESCRIPTION

The EP7211 device is a single-chip embedded controller designed to be used in low cost and ultra-
low-power applications. A hand-held personal organizer and hand-held internet browser are just two
of the many potential applications of the device.

The EP7211 operates at 2.5 V and up to 74 MHz using the ARM7TDMI CPU with MMU, a write
buffer, and cache. The EP7211 device is designed to be backward compatible with Cirrus' CL-
PS7111 device. For the same functionality, this device is a drop-in upgrade -- it contains the same
pinout and register arrangement, making previous software binary-compatible, and system boards
requiring only voltage changes in most cases.There are other devices offered by Cirrus Logic
(http://www.cirrus.com) that can be used around this chip to build a complete hand-held organizer.
These include IR chipsets, still camera chipsets, audio DACs, codecs, etc.

The EP7211 contains additional functionality to the CL-PS7111 device that can be accessed through
various pin-muxing options. The additions are:

ARM720T core processor -- giving Thumb and WinCETM support and dynamically
programmable core clock speeds of 18 MHz, 36 MHz, 49 MHz, and 74 MHz

MCP -- Multimedia Codec Port to interface to the Philips' UCB1100 codec

Increased A/D data flexibility -- data width configurable between 8 to 16 bits

Increased on-chip SRAM size to 38,400 bytes; the entire display memory for a 640

240

bits/pixel can be contained within this on-chip SRAM

Dedicated LED flasher pin running from the realtime clock (RTC)

EDO DRAM support (Fast Page DRAM is only supported at 13 MHz and 18 MHz)

Full JTAG boundary scan and Embedded ICE support

The core-logic functionality is built around the ARM720T processor (i.e., an ARM7TDMI 32-bit
RISC CPU with a WinCE compatible MMU, a write buffer, and 8 kbytes of cache). At 74 MHz and
with the on-chip four-way set-associative cache, the EP7211 delivers approximately 66 Dhrystone
2.1 MIPS of sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz
Pentium-based PC.

The EP7211 can interface to up to two banks of DRAM. Each bank can be up to 256 Mbytes in size.
The DRAM interface is programmable to be 16-bit or 32-bit wide. There are also interfaces for:

Two ROM/SRAM/Flash banks each up to 256 Mbytes

Up to four expansion devices, each up to 256 Mbytes in size

An interface to up to two Cirrus Logic CL-PS6700 PC Card controller devices to support two PC
Card slots

The expansion devices could be additional ROM/SRAM/Flash as well. In addition, the EP7211
provides 38,400 bytes of on-chip SRAM that can be used for three purposes:

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Functional Description

DS352PP3

JUL 2001

Critical program storage

LCD frame buffer

General purpose data storage

The EP7211 supports a number of serial interface protocols including two high speed (115 kbps)
UARTs with RX and TX FIFOs, a codec interface with FIFO support, and two additional
synchronous serial interfaces. One of the UARTs also supports the IrDA SIR protocol.

The EP7211 also has an on-chip Boot ROM (128 bytes), which is hardware selectable on power-on
reset. This Boot ROM initializes UART1, and downloads the application-specific main boot code
into the on-chip SRAM. Once download is complete, execution jumps to the start of the on-chip
SRAM. This feature could be used in a manufacturing environment to allow the EP7211 to download
code into on-board blank Flash. [See

Section 10 Appendix A: Boot Code on page 157

]

The EP7211 design is optimized for low power dissipation, and is fabricated on a fully static 0.25
micron CMOS process. It is available in 256-ball PBGA and 208-pin LQFP packages.

3.1

Main Functional Blocks

The principle functional blocks in the EP7211 are:

ARM720T processor, which consists of the following functional sub-blocks:

ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced
multiplier, JTAG, and the Embedded ICE)

Memory management unit from the ARM700 and ARM710 processors with WinCE support; it also contains a
64-bit translation look aside buffer (TLB)

8 kbytes of unified instruction and data cache, four-way set associative cache controller

Write buffer

38,400 bytes of SRAM; full address decode is performed.

Two PC Card slots supported by an interface to one CL-PS6700 per slot

Interrupt controller

Expansion and ROM/SRAM/Flash interface giving 4, 5, or 6

256 Mbyte expansion segments

with independent wait states

DRAM controller supporting EDO, fast page and self-refresh in the Standby State, and both 16-
bit and 32-bit wide memory (Fast Page DRAM is only supported at 13 MHz and 18 MHz

27 bits of general purpose peripheral I/O -- multiplexed to provide additional functionality
where necessary

Codec sound interface with 16-byte transmit and receive FIFOs

MCP (Multimedia Codec Port) giving access to an audio codec, a telecom codec, a touchscreen
interface, four general purpose analog-to-digital converter inputs, and ten programmable digital
I/O lines

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Functional Description

DS352PP3
JUL 2001

On-chip Boot ROM programmed with serial load boot sequence

Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level greyscaler

Programmable frame buffer start address, allowing a system to be built using only external or
internal SRAM for memory, eliminating any need for DRAMs at all

Two full duplex 16C550 style UARTs with two 16-byte FIFOs

IrDA SIR Protocol controller capable of speeds up to 115.2 kbps

Two 16-bit general purpose timer counters

A 32-bit real time clock and comparator

Dedicated LED flasher pin driven from the RTC with programmable duty ratio

Two PWM interfaces

Advanced system state control and power management

Two synchronous serial interfaces for Microwire or SPI peripherals such as ADCs, one
supporting both the master and slave mode and up to 512 kbps continuous data rate, while the
other supports only the master mode with no buffering, and up to 128 kbps

Full boundary scan -- JTAG

External tracing support for debug

The main oscillator and phase locked loop (PLL) to generate twice the maximum CPU clock of
73.728 MHz from a 3.6864 MHz crystal, with an alternative external clock input (used in 13
MHz mode)

A low power 32.768 kHz oscillator

Figure 3-1. EP7211 Block Diagram shows a simplified block diagram of the EP7211. All external
memory and peripheral devices are connected to the 32-bit data bus using the external 28-bit address
bus and control signals. Bus transfer times can be extended using the EXPRDY signal to lengthen
bus cycles.

EP7211

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Functional Description

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Figure 3-1. EP7211 Block Diagram

3.2

CPU Core

The ARM7TDMI core CPU is a 32-bit RISC processor, which is connected directly to the 8-kbyte
unified cache. This cache has 512 lines of 4 words, arranged as a 4-way set associative cache. The
cache is directly connected to the ARM7TDMI CPU, and therefore caches the virtual address from
the CPU. The MMU translates the virtual address into a physical address, it contains a 64-entry
translation look aside buffer (TLB) and is post cache; that is, it only translates external memory
references (cache misses) to save power.

The ARM7TDMI CPU, the MMU, the cache, and the write buffer together make up what is called
the ARM720T processor. See the ARM720T Datasheet for a complete description of the various
logic blocks that make up the processor, as well as all internal register information.

3.3

Interrupt Controller

The ARM720T has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The
interrupt controller in the EP7211 controls interrupts from 22 different sources. Seventeen interrupt
sources are mapped to the IRQ input and five sources to the FIQ input. FIQs have a higher priority

32.768-KHZ

OSCILLATOR

PLL

INTERRUPT

CONTROLLER

POWER

MANAGEMENT

SSI1 (ADC)

DRAM

CONTROLLER

LCD

CONTROLLER

ARM7TDMI
CPU CORE

8-KBYTE

CACHE

MMU

TIMER

COUNTERS (2)

CODEC

ARM720T

INTERNAL DATA BUS

PWM

3.6864 MHZ

32.768 KHZ

EINT[13], FIQ,

MEDCHG

BATOK, EXTPWR
PWRFL, BATCHG

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (07)

BUZZER DRIVE

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

ADCCS

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

SSIRSFR

UART2

IrDA

D0D31

POR, RUN,

RESET, WAKEUP

EXPCLK, WORD,
CS[03], EXPRDY,
WRITE

MOE, MWE,
RAS[01], CAS[03]

A[027],
DRA[012]

LCD DRIVE

LED AND
PHOTODIODE

ASYNC
INTERFACE 2

GPIO

INTERNAL ADDRESS BUS

13-MHZ INPUT

ON-CHIP

BOOT ROM

ASYNC
INTERFACE 1

ON-CHIP SRAM

37.5 KBYTES

CL-PS6700

INTFC.

PB[01], CS[45]

EXPANSION

CONTROL

UART1

SSI2

APB BRIDGE

APB BUS

RTC

FLASHING LED DRIVE

ICE-JTAG

TEST AND
DEVELOPMENT

WRITE

BUFFER

MULTIMEDIA

CODEC PORT

STATE CONTROL

MEMORY CONTROL BLOCK

LCD DMA

DC-TO-DC

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than IRQs. If two interrupts within the same group (IRQ or FIQ) are active, the order in which they
are serviced must be resolved in software.

All interrupts are level sensitive; that is, they must conform to the following sequence.

1) The interrupting device (either external or internal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the interrupt mask register, then either a FIQ or an IRQ will be as-

serted by the interrupt controller. (A description for each bit in this register can be found in

Sec-

tion 5.3.1 INTSR1 Interrupt Status Register 1 on page 94

3) If interrupts are enabled the processor will jump to the appropriate address.

4) Interrupt dispatch software reads the interrupt status register to establish the source(s) of the in-

terrupt and calls the appropriate interrupt service routine(s).

5) Software in the interrupt service routine will clear the interrupt source by some action specific to

the device requesting the interrupt (e.g., reading the UART RX register).

The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be
serviced in a similar way. Alternately, it may return to the interrupt dispatch code, which can check
for any more pending interrupts and dispatch them accordingly. The "End of Interrupt" type
interrupts are latched. All other interrupt sources (e.g., external interrupt source) must be held active
until its respective service routine starts executing. See

Section 5.13

for more details.

Table 3-1

Table 3-2

and

Table 3-3

show the names and allocation of interrupts in the EP7211.

Table 3-1. Interrupt Allocation in First Interrupt Register

Interrupt

Bit in INTMR1

and INTSR1

Name

Comment

FIQ

EXTFIQ

External fast interrupt input (NEXTFIQ pin)

FIQ

BLINT

Battery low interrupt

FIQ

WEINT

Watchdog expired interrupt

FIQ

MCINT

Media changed interrupt

IRQ

CSINT

Codec sound interrupt

IRQ

EINT1

External interrupt input 1 (NEINT1 pin)

IRQ

EINT2

External interrupt input 2 (NEINT2 pin)

IRQ

EINT3

External interrupt input 3 (EINT3 pin)

IRQ

TC1OI

TC1 underflow interrupt

IRQ

TC2OI

TC2 underflow interrupt

IRQ

RTCMI

RTC compare match interrupt

IRQ

TINT

64 Hz tick interrupt

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3.3.1

Interrupt Latencies in Different States

3.3.1.1

Operating State

The ARM720T processor checks for a low level on its FIQ/IRQ inputs at the end of each instruction.
First, there is a one to two clock cycle synchronization penalty. For the case where the EP7211 is
operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one
wait state Flash memory, the worst case interrupt latency is 251 clock cycles. This corresponds to the
processor executing a STM instruction to DRAM, and where the MMU needs to fetch protection/
translation information from page tables in DRAM memory. This includes a delay for cache line fills
for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM
being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA
cycles to support a panel size of 320

240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress.

IRQ

UTXINT1

Internal UART1 transmit FIFO empty interrupt

IRQ

URXINT1

Internal UART1 receive FIFO full interrupt

IRQ

UMSINT

Internal UART1 modem status changed interrupt

IRQ

SSEOTI

Synchronous serial interface 1 end of transfer interrupt

Table 3-2. Interrupt Allocation in Second Interrupt Register

Interrupt

Bit in INTMR2

and INTSR2

Name

Comment

IRQ

KBDINT

Key press interrupt

IRQ

SS2RX

Master/slave SSI 16 bytes received

IRQ

SS2TX

Master/slave SSI 16 bytes transmitted

IRQ

UTXINT2

UART2 transmit FIFO empty interrupt

IRQ

URXINT2

UART2 receive FIFO full interrupt

Table 3-3. Interrupt Allocation in Third Interrupt Register

Interrupt

Bit in INTMR3

and INTSR3

Name

Comment

FIQ

MCPINT

MCP interface interrupt

Table 3-1. Interrupt Allocation in First Interrupt Register

(cont.)

Interrupt

Bit in INTMR1

and INTSR1

Name

Comment

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This would give a worst-case interrupt latency of about 19.3

µs for the ARM720T processor

operating at 13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is
increased by the maximum time required to pass through the deglitcher, which is approximately 61
µs (1 cycle of the 16.384 kHz clock derived from the RTC oscillator). This would create an absolute
worst case latency of approximately 80

µs. If the ARM720T is run at 36 MHz or greater and/or 32-

bit wide external memory, the 19.3

µs value will be reduced.

All the serial data transfer peripherals included in the EP7211 (except for the master-only SSI1) have
local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or
less. This assumes that the maximum data rates described in this specification are complied with. If
the OS cannot meet this requirement, there will be a risk of data over/underflow occurring.

3.3.1.2

Idle State

When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately
two clock cycles. However, there is still potentially up to 20

µs latency as described in the first

section above, unless the code is written to include at least two single cycle instructions immediately
after the write to the IDLE register (in which case the latency drops to a few microseconds). This is
important, as normally the Idle State will have been left because of a pending interrupt, which has to
be synchronized by the processor before it can be serviced.

3.3.1.3

Standby State

In the Standby State, the latency will depend on whether the system clock is shut down and if the
FASTWAKE bit in the SYSCON3 register is set. If the system is configured to run from the internal
PLL clock, then the PLL will always be shut down when in the Standby State. In this case, if the
FASTWAKE bit is cleared, then there will be a latency of between 0.125 s to 0.25 s. If the
FASTWAKE bit is set, then there will be a latency of between 250

µs to 500 µs. If the system is

running from the external clock (at 13 MHz), with the CLKENSL bit in SYSCON2 set to 0, then the
latency will also be between 0.125 s and 0.25 s to enable an external oscillator to stabilize. In the case
of a 13 MHz system where the clock is not disabled during the Standby State (CLKENSL = 1), then
the latency will be the same as described in the Idle State section above.

Whenever the EP7211 is in the Standby State, the external address and data buses are driven low.
The RUN signal is used internally to force these buses to be driven low. This is done to prevent
peripherals that are power-down from draining current. Also, the internal peripheral's signals get set
to their Reset State.

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Table 3-4

summarizes the three external interrupt sources and the effect they have on interrupt pins.

For the case of the keyboard interrupt, the following options are available and are selectable
according to bits 1 and 3 of the SYSCON2 register (refer to SYSCON2 register description for
details).

If the KBWEN bit (SYSCON2 Bit 3) is set low, then a keypress will cause a transition from a
power saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register
2 (INTMR2 bit 0) is high).

When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the
interrupt mask register. This is called the "Keyboard Direct Wakeup' mode. In this mode, the
interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register
2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off
before it entered the power saving state. If the interrupt is non-masked, then the processor will
service the interrupt.

When the KBD6 bit (SYSCON2 Bit 1) is low, all 8 of Port A inputs are OR'ed together to
produce the internal wakeup signal and keyboard interrupt request. This is the default reset
state.

When the KBD6 bit (SYSCON2 Bit 1) is high, only the lowest 6 bits of Port A are OR'ed
together to produce the internal wakeup signal and keyboard interrupt request. The two most
significant bits of Port A are available as GPIO when this bit is set high.

Table 3-4. External Interrupt Source Latencies

Interrupt

Pin

Input State

Operating

State

Latency

Idle State

Latency

Standby State Latency

NEXTFIQ

Not deglitched;
must be active for
20

µs to be

detected

Worst case
latency of 20
µs

Worst case 20
µs: if only sin-
gle cycle
instructions,
less than
1

µs

Including PLL/osc. settling time,
approx. 0.25 s when FASTWAKE
= 0, or approx. 500 µs when
FASTWAKE = 1, or = Idle State if
in 13 MHz mode with CLENSL set

NEINT12

Not deglitched

Worst case
latency of 20
µs

As above

EINT3

Not deglitched

Worst case
latency of 20
µs

As above

MEDCHG

Deglitched by
16 kHz clock; must
be active for at
least 80

µs to be

detected

Worst case
latency of 80
µs

Worst case 80
µs: if only sin-
gle cycle
instructions,
61

µs

As above (note difference if in 13
MHz mode with CLKENSL set)

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In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup
the device by using the external WAKEUP pin or another enabled interrupt source. The keyboard
interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a
combination of both.

NOTE: The keyboard interrupt is NOT deglitched.

3.4

Memory and I/O Expansion Interface

Six separate linear memory or expansion segments are decoded by the EP7211, two of which can be
reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each
segment is 256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated
to the on-chip SRAM and the on-chip ROM. The on-chip ROM space is fully decoded, and the
SRAM space is fully decoded up to the maximum size of the video frame buffer programmed in the
LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded
(i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of
the six segments can be configured to interface to a conventional SRAM-like interface, and can be
individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute
from 1 to 4 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait
state sequential access feature is designed to support burst mode ROMs. For writeable memory
devices which use the NMWE pin, zero wait state sequential accesses are not permitted and one wait
state is the minimum which should be programmed in the sequential field of the appropriate
MEMCFG register. Bus cycles can also be extended using the EXPRDY input signal.

Page mode access is accomplished by setting SQAEN = 1, which enables accesses of the form one
random address followed by three sequential addresses, etc., while keeping NCS asserted. These
sequential bursts can be up to four words long before NCS is released to allow DMA and refreshes
to take place. This can significantly improve bus bandwidth to devices such as ROMs which support
page mode. When SQAEN = 0, all accesses to the ROM/SRAM/Flash are by random access without
NCS being de-asserted between accesses. Again NCS is de-asserted after four consecutive accesses
to allow refreshes, etc.

Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC
Card slot drivers). When either of these interfaces are enabled, the corresponding chip select (NCS4
and/or NCS5) becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 Bit 5
determines the function of chip select NCS4 (i.e., CL-PS6700 interface or standard chip select
functionality); Bit 6 controls NCS5 in a similar way. There is no interaction between these bits.

For applications that require a display buffer smaller than 38,400 bytes, the on-chip SRAM can be
used as the frame buffer and no external DRAM needs to be used.

The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on
reset. These inputs are latched by the rising edge of NPOR to select the boot option.

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3.5

EP7211 Boot ROM

The 128 bytes of on-chip Boot ROM contain a instruction sequence that initializes the device and
then configures UART1 to receive 2048 bytes of serial data that will then be placed in the on-chip
SRAM. Once the download is complete, execution jumps to the start of the on-chip SRAM. This
would allow, for example, code to be downloaded to program system Flash during a product's
manufacturing process. See

Section 10 Appendix A: Boot Code on page 157

for details of the ROM

Boot Code with comments to describe the stages of execution.

Selection of the Boot ROM option is determined by the state of the NMEDCHG pin during a power
on reset. If NMEDCHG is high while NPOR is active, then the EP7211 will boot from an external
memory device connected to CS0 (normal boot mode). If NMEDCHG is low, then the boot will be
from the on-chip ROM. Note that in both cases, following the de-assertion of power on reset, the
EP7211 will be in the Standby State and requires a low-to-high transition on the external WAKEUP
pin in order to actually start the boot sequence.

The effect of booting from the on-chip Boot ROM is to reverse the decoding for all chip selects
internally.

Table 3-6

shows this decoding. The control signal for the boot option is latched by

NPOR, which means that the remapping of addresses and bus widths will continue to apply until
NPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM can be
read back from address 0x00000000 onwards, and in normal state of operation the Boot ROM
contents can be read back from address range 0x70000000.

Table 3-5. Boot Options

PE[1]

PE[0]

Boot Block(NCS0)

32-bit

8-bit

16-bit

Undefined

Table 3-6. Chip Select Address Ranges After Boot From On-Chip Boot ROM

Address Range

Chip Select

0000.00000FFF.FFFF

CS7 (Internal only)

1000.00001FFF.FFFF

CS6 (Internal only)

2000.00002FFF.FFFF

NCS5

3000.00003FFF.FFFF

NCS4

4000.00004FFF.FFFF

NCS3

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3.6

CL-PS6700 PC Card Controller Interface

Two of the expansion memory areas are dedicated to supporting up to two CL-PS6700 PC Card
controller devices. These are selected by NCS4 and NCS5 (once enabled by bits 5 and 6 of
SYSCON2). For efficient, low power operation, both address and data are carried on the lower 16
bits of the EP7211 data bus. Accesses are initiated by a write or read to or from the area of memory
allocated for NCS4 or NCS5. The memory map within each of these areas is segmented to allow
different types of PC Card accesses to take place, for attribute, I/O, and common memory space. The
CL-PS6700 internal registers are memory mapped within the address space as shown in Table 3-7.
CL-PS6700 Memory Map.

NOTE: It must be noted that, due to the operating speed of the CL-PS6700, this interface is supported only

for processor speeds of 13 and 18 MHz.

A complete description of the protocol and AC timing characteristics can be found in the CL-PS6700
Databook. A transaction is initiated by an access to the NCS4 or NCS5 area. The chip select is
asserted, and on the first clock, the upper 10 bits of the PC Card address, along with 6 bits of size,
space, and slot information are put out onto the lower 16 bits of the EP7211's data bus. Only word
(i.e., 4-byte) and single-byte accesses are supported, and the slot field is hardcoded to 11, since the
slot field is defined as a `Reserved field' by the CL-PS6700. The chip selects are used to select the
device to be accessed. The space field is made directly from the A26 and A27 CPU address bits,
according to the decode shown in Table 3-8. Space Field Decoding below. The size field is forced
to 11 if a word access is required, or 00 if a byte access is required. This avoids the need to configure
the interface after a reset. On the second clock cycle, the remaining 16 bits of the PC Card address
are multiplexed out onto the lower 16 bits of the data bus. If the transaction selected is a CL-PS6700
register transaction, or a write to the PC Card (assuming there is space available in the CL-PS6700's

5000.00005FFF.FFFF

NCS2

6000.00006FFF.FFFF

NCS1

7000.00007FFF.FFFF

NCS0

Table 3-7. CL-PS6700 Memory Map

Access Type

Addresses for CL-PS6700 Interface 1

Addresses for CL-PS6700 Interface 2

Attribute

0x400000000x43FFFFFF

0x50000000 0x53FFFFFF

I/O

0x440000000x47FFFFFF

0x540000000x57FFFFFF

Common memory

0x480000000x4BFFFFFF

0x580000000x5BFFFFFF

CL-PS6700 registers

0x4C0000000x4FFFFFFF

0x5C0000000x5FFFFFFF

Table 3-6. Chip Select Address Ranges After Boot From On-Chip Boot ROM

(cont.)

Address Range

Chip Select

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internal write buffer) then the access will continue on the following two clock cycles. During these
following two clock cycles the upper and lower halves of the word to be read or written will be put
onto the lower 16 bits of the main data bus.

The `ptype' signal on the CL-PS6700s should be connected to the EP7211's WRITE output pin.
During PC Card accesses, the polarity of this pin changes and it becomes low to signify a write and
high to signify a read. It is valid with the first half word of the address. During the second half word
of the address it is always forced high to indicate to the CL-PS6700 that the EP7211 has initiated
either the write or read.

The PRDY signals from each of the two CL-PS6700 devices are connected to Port B bits 0 and 1,
respectively. When the PC CARD1 or PC CARD2 control bits in the SYSCON2 register are de-
asserted, these port bits are available for GPIO. When asserted, these port bits are used as the PRDY
signals. When the PRDY signal is de-asserted (i.e., low), it indicates that the CL-PS6700 is busy
accessing its card. If a PC CARD access is attempted while the device is busy, the PRDY signal will
cause the EP7211's CPU to be stalled. The EP7211's CPU will have to wait for the card to become
available. DMA transfers to the LCD can still continue in the background during this period of time
(as described below). The EP7211 can access the registers in the CL-PS6700, regardless of the state
of the PRDY signal. If the EP7211 needs to access the PC CARD via the CL-PS6700, it waits until
the PRDY signal is high before initiating a transfer request. Once a request is sent, the PRDY signal
indicates if data is available.

In the case of a PC Card write, writes can be posted to the CL-PS6700 device, with the same timing
as CL-PS6700 internal register writes. Writes will normally be completed by the CL-PS6700 device
independent of the EP7211 processor activity. If a posted write times out, or fails to complete for any
other reason, then the CL-PS6700 will issue an interrupt (i.e., a WR_FAIL interrupt). In the case
where the CL-PS6700 write buffer is already full, the PRDY signal will be de-asserted (i.e., driven
low) and the transaction will be stalled pending an available slot in the buffer. In this case, the
EP7211's CPU will be stalled until the write can be posted successfully. While the PRDY signal is
de-asserted, the chip select to the CL-PS6700 will be de-asserted and the main bus will be released
so that DMA transfers to the LCD controller can continue in the background.

In the case of a PC Card read, the PRDY signal from the CL-PS6700 will be de-asserted until the
read data is ready. At this point, it will be reasserted and the access will be completed in the same
way as for a register access. In the case of a byte access, only one 16-bit data transfer will be required
to complete the access. While the PRDY signal is de-asserted, the chip select to the CL-PS6700 will

Table 3-8. Space Field Decoding

Space Field Value

PC CARD Memory Space

Attribute

I/O

Common memory

CL-PS6700 registers

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be de-asserted and the main bus will be released so that DMA transfers to the LCD controller can
continue in the background.

The EP7211 will re-arbitrate for control of the bus when the PRDY signal is reasserted to indicate
that the read or write transaction can be completed. The CPU will always be stalled until the PC Card
access is completed.

A card read operation may be split into a request cycle and a data cycle, or it may be combined into
a single request/data transfer cycle. This depends on whether the data requested from the card is
available in the prefetch buffer (internal to the CL-PS6700).

The request portion of the cycle, for a card read, is similar to the request phase for a card write
(described above). If the requested data is available in the prefetch buffer, the CL-PS6700 asserts the
PRDY signal before the rising edge of the third clock and the EP7211 continues the cycle to read the
data. Otherwise, the PRDY signal is de-asserted and the request cycle is stalled. The EP7211 may
then allow the DMA address generator to gain control of the bus, to allow LCD refreshes to continue.
When the CL-PS6700 is ready with the data, it asserts the PRDY signal. The EP7211 then arbitrates
for the bus and, once the request is granted, the suspended read cycle is resumed. The EP7211
resumes the cycle by asserting the appropriate chip select, and data is transferred on the next two
clocks if a word read (one clock if a byte read).

There is no support within the EP7211 for detecting time-outs. The CL-PS6700 device must be
programmed to force the cycle to be completed (with invalid data for a read) and generate an
interrupt if a read or write access is timed out (i.e., RD_FAIL or WR_FAIL interrupt). The system
software can then determine which access was not successfully completed by reading status registers
within the CL-PS6700.

The CL-PS6700 has support for DMA data transfers. However, DMA is supported only by software
emulation because the DMA address generator built into the EP7211 is dedicated to the LCD
controller interface. If DMA is enabled within the CL-PS6700, it will assert its PDREQ signal to
make a DMA request. This can be connected to one of the EP7211's external interrupts and be used
to interrupt the CPU so that the software can service the DMA request under program control.

Each of the CL-PS6700 devices can generate an interrupt PIRQ. The PIRQ output is open drain on
the CL-PS6700 devices, so if there are two CL-PS6700 devices they may be wire OR'ed to the same
interrupt which can be connected to one of the EP7211's active low external interrupt sources. On
the receipt of an interrupt, the CPU can read the interrupt status registers on the CL-PS6700 devices
to determine the cause of the interrupt.

All transactions are synchronized to the EXPCLK output from the EP7211 in 18.432 MHz mode or
the external 13 MHz clock. The EXPCLK should be permanently enabled, by setting the EXCKEN
bit in the SYSCON1 register, when the CL-PS6700 is used. The reason for this is that the PC Card
interface and CL-PS6700 internal write buffers need to be clocked after the EP7211 has completed
its bus cycles.

A GPIO signal from the EP7211 can be connected to the PSLEEP pin of the CL-PS6700 devices to
allow them to be put into a power saving state before the EP7211 enters the Standby State. It is

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essential that the software monitor the appropriate status registers within the CL-PS6700s to ensure
that there are no pending posted bus transactions before the Standby State is entered. Failure to do
this will result in incomplete PC Card accesses.

3.7

DRAM Controller with EDO Support

The DRAM controller in the EP7211 provides all the connections to directly interface to up to two
banks of (EDO) DRAM, and the width of the memory interface is programmable to 16-bit or 32-bit.
Both banks have to be of the same width. The 16/32-bit DRAM width selection is made based on
Bit 2 of the SYSCON2 register. Each of the two banks supported can be up to 256 Mbytes in size.
Two RAS lines and four CAS lines are provided, with one CAS line per byte lane. The DRAM
controller does not support device size programmability. Therefore, if two banks are implemented
and DRAM devices are used that would create a bank smaller than 256 Mbytes, then this would lead
to a segmented memory map. Each segmented bank will be separated by 256 Mbytes. Segments that
are smaller than the bank size will repeat within the bank. Table 3-9. Physical to DRAM Address
Mapping shows the mapping of the physical address to DRAM row and column addresses. This
mapping has been organized to support any DRAM device size from 4 Mbit to 1 Gbit with a square
row and column configuration (i.e., the number of column addresses is equal to the number of row
addresses). If a non-square DRAM is used, further fragmentation of the memory map will occur,
however the smallest contiguous segment will always be 1 Mbyte. With proper mapping of
pages/sections by the MMU, one can create contiguous memory blocks.

On boot-up, the DRAM controller is configured for operation with an 18.432 MHz internal bus
speed, and therefore, can support either fast page mode or EDO DRAM. In this case, the read data
from the DRAM is latched within the EP7211 during the high phase of the NCAS output strobes.
The DRAM must not have an access time greater than 70 ns in order to meet the 18 MHz timing
requirements. When the internal bus is operating at 36.864 MHz (i.e., for CPU clock frequencies of
36.864, 49.152, or 73.728 MHz), the DRAM controller will only operate with EDO DRAM. When
operating at 36 MHz, the EDO DRAM must not have an access time greater than 50 ns. The DRAM
cycle timings are adjusted to take advantage of the additional performance available from fast EDO
DRAM. In EDO mode, the EP7211 design relies on the DRAM data being driven to be available on
the external data bus during the entire high phase of the NCAS signal so that it can be latched towards
the end of the cycle. In Fast Page mode, the data should be latched at the rising edge of NCAS. It is
not possible to use the EP7211 with fast page mode DRAM at operating frequencies of 36 MHz or
higher.

The DRAM controller breaks all sequential access, so that the minimum page sizes defined can be
supported. All of the possible page sizes are multiples of the minimum page size, so by breaking up
accesses on minimum page sizes by default, all accesses crossing larger page boundaries are broken
up.

NOTE: This bit will be generated by the DRAM controller.

An example of the DRAM connections for a typical system can be found in Figure 3-13. A
Maximum EP7211 Based System.

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The DRAM controller contains a programmable refresh counter. The refresh rate is controlled using
the DRAM refresh period register (DRFPR).

The 16/32-bit DRAM selection is made based on Bit 2 of the SYSCON2 register. Both banks must
have the same width.

SYSCON2 0x8000 1100 Bit 2 (DRAMSZ)0 = 32-bit DRAM
1 = 16-bit DRAM

The default is 32-bit width, since the SYSCON2 register is reset to all zeros on power-up.

Table 3-11. DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System

EP7211 Size

Address

Configuration

Total Size of

Bank

Address Range of

Segment(s)

Size of

Segment(s)

4 Mbit

9 Row x 9 Column

0.5 Mbyte

n000.0000n007.FFFF

0.5 MByte

16 Mbit

10 Row x 10 Column

2 Mbytes

n000.0000n01F.FFFF

2 Mbytes

16 Mbit

12 Row x 8 Column

2 Mbytes

n000.0000n003.FFFF

n008.0000n00B.FFFF

n020.0000n023.FFFF

n028.0000n02B.FFFF

n080.0000n083.FFFF

n088.0000n08B.FFFF

n0A0.0000n0A3.FFFF

n0A8.0000n0AB.FFFF

256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes

64 Mbit

11 Row x 11 Column

8 Mbytes

n000.0000n07F.FFFF

8 Mbytes

64 Mbit

13 Row x 9 Column

8 Mbytes

n000.0000n00F.FFFF
n020.0000n02F.FFFF
n080.0000n08F.FFFF

n0A0.0000n0AF.FFFF

n200.0000n20F.FFFF
n220.0000n22F.FFFF
n280.0000n28F.FFFF

n2A0.0000n2AF.FFFF

1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte

256 Mbit

12 Row x 12 Column

32 Mbytes

n000.0000n1FF.FFFF

32 Mbytes

1 Gbit

13 Row x 13 Column

128 Mbytes

n000.0000n7FF.FFFF

128 Mbytes

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3.8

Serial Interfaces

The EP7211 offers the following serial interfaces in addition to the two UARTs.

The inputs/outputs of three of the serial synchronous interfaces (MCP, codec, and SSI2) are
multiplexed onto a single set of external interface pins. If the MCPSEL bit of SYSCON3 is low, then
either SSI2 or the codec interface will be selected to connect to the external pins. When Bit 0 of
SYSCON2 (SERSEL) is high, then the codec is connected to the external pins, when low the
master/slave SSI2 is connected to these pins. When the MCPSEL bit is set high, the MCP interface
is connected to the external pins. On power up, both the MCPSEL and SERSEL bits are reset low,
thus the master/slave SSI2 will be connected to these pins (and configured for slave mode operation
to avoid external drive clashes).

The following table contains pin definition information for the three multiplexed interfaces.

NOTE: The internal names given to each of the three interfaces are unique to help differentiate them from

each other. The sections below that describe each of the three interfaces will use their respective
unique internal pin names for clarity.

* p/u = use an 10 k pull-up

Table 3-12. Serial Interface Options

Type

Comments

Referred To As

Max. Transfer Speed

SPI/Microwire 1

Master mode only

ADC Interface

128 Kbps

SPI/Microwire 2

Master/slave mode

SSI2 Interface

512 Kbps

MCP Interface

Touchscreen, codecs, and GPIO

MCP Interface

9.216 Mbps

Codec Interface

Only for use in the PLL clock mode

Codec Interface

64 Kbps

Table 3-13. Serial-Pin Assignments

Pin No.

LQFP

External

Pin Name

SSI2

Slave Mode

(Internal Name)

SSI2

Master Mode

Codec

Internal Name

MCP

Internal Name

Strength

SSICCLK

SSICCLK = serial

bit clock; Input

Output

PCMCLK =

Output

SIBCLK =

Output

SSITXFR

SSKTXFR = TX

frame sync; Input

Output

PCMSYNC =

Output

SIBSYNC =

Output

SSITXDA

SSITXDA = TX

data; Output

Output

PCMOUT =

Output

SIBDOUT =

Output

SSIRXDA

SSIRXDA = RX

data; Input

Input

PCMIN = Input

SIBDIN = Input

SSIRXFR

SSIRXFR = RX

frame sync; Input

Output

p/u*

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3.8.1

Codec Sound Interface

The codec interface allows direct connection of a telephony type codec to the EP7211. It provides
all the necessary clocks and timing pulses and performs a parallel to serial conversion or vice versa
on the data stream to or from the external codec device. The interface is full duplex and contains two
separate data FIFOs (16 deep by 8-bits wide, one for the receive data, another for the transmit data).

Data is transferred to or from the codec at 64 kbps. The data is either written to or read from the
appropriate 16 byte FIFO. If enabled, a codec interrupt (CSINT) will be generated after every 8 bytes
are transferred (FIFO half full/empty). This means the interrupt rate will be every 1 ms, with a
latency of 1 ms.

Transmit and receive modes are enabled by asserting high both the CDENRX and CDENTX codec
enable bits in the SYSCON1 register.

NOTE: Both the CDENRX and CDENTX enable bits should be asserted in tandem for data to be transmitted

or received. The reason for this is that the interrupt generation will occur 1 ms after one of the FIFOs
is enabled. For example: If the receive FIFO gets enabled first and the transmit FIFO at a later time,
the interrupt will occur 1 ms after the receive FIFO is enabled. After the first interrupt occurs, the
receive FIFO will be half full. However, it will not be possible to know how full the transmit FIFO will
be since it was enabled at a later time. Thus, it is possible to unintentionally overwrite data already in
the transmit FIFO. See the following diagram:

Figure 3-2. Codec Interrupt Timing

3.8.1.1

Codec Interrupt Timing

After the CDENRX and CDENTX enable bits get asserted, the corresponding FIFOs become
enabled. When deasserted low, the FIFO status flags (i.e., CRXFE and CTXFF located in the
SYSFLAG register) are cleared and the FIFOs appear empty. Additionally, if the CDENTX bit is
low, the PCMOUT output is disabled. Asserting either of the two enable bits causes the sync and
interrupt generation logic to become active; otherwise they are disabled to conserve power.

CDENRX

CDENTX

CSINT

1 ms

Inte

rrupt oc

curs

terrupt o

ccu

r
s

Inte

t oc

curs

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Data is loaded into the transmit FIFO by writing to the CODR register. At the beginning of a transmit
cycle, this data is loaded into a shift/load register. Just prior to the byte being transferred out,
PCMSYNC goes high for one PCMCLK cycle. Then the data is shifted out serially to PCMOUT,
MSB first, (with the MSB valid at the same time PCMSYNC is asserted). Data is shifted on the rising
edge of the PCMCLK output.

Receiving of data is performed by taking data in serially through PCMIN, again MSB first, shifting
it through the shift/load register and loading the complete byte into the receive FIFO. Input data is
sampled on the falling edge of PCMCLK. Data is read from the CODR register.

NOTE: After data is transmitted, the speaker amplifier should be turned off to avoid audible noise. This is

needed because the EP7211 will continue to transmit data from the FIFO even though it is empty, thus
causing noise. This will occur even when receiving.

3.8.2

MCP Interface

The Multimedia Communications Port (MCP) provides an interface to the Philips UCB1100 codec.
This device has an audio codec, a telecom codec, a touch-screen interface, four general purpose ADC
inputs, and ten programmable digital I/O lines. The MCP interface is used by the device both to input
and output digital data to and from the codec, and to configure and acquire status information from
the codec's 16 registers.

The MCP produces two 64-bit subframes per frame (128 bits for both subframes in the frame) using
a bit clock and frame synchronization signal. Data is communicated full duplex via a separate
transmit and receive data line. The bit clock frequency is fixed at 9.216 Mbps for all modes except
the 13 MHz mode. For the 13 MHz mode, the bit clock frequency is fixed at 6.5 Mbps. The MCP
communicates to the codec in the first of the two subframes. The second subframe is used in high-
end applications to communicate with a second stereo codec, such as Crystal's CS4216/18, however
this feature is not supported by the MCP. Each 64-bit subframe contains seven different fields of
information. These fields include audio conversion data, telecom conversion data, data valid flags,
control register address, control register data, and read/write control. Both transmit and receive data
contains these seven fields. The transmitted frame contains data for D-to-A conversion, as well as
address, data, and control signals to write to or read from the codec's registers. The received frame
contains A-to-D samples, and the data returned from a read of a codec register.

Both the MCP and the off-chip codec contain programmable 7-bit divisors, one each for the telecom
and audio data. These values are used to divide the bit clock to generate a desired sampling
frequency. When the codec is enabled, the divisor pairs are synchronously transferred to their
respective modulus registers within the MCP and codec' and decrement using the bit clock. This
technique allows telecom and audio data to be transferred between the MPC and codec, lock-step in
sync with the sampling/conversion frequency of the codec.

The MCP contains two pairs of transmit FIFOs and two pairs of receive FIFOs, one each for audio
and telecom data. In the current implementation, the two receive FIFOs are deeper than the two
transmit FIFOs. The sizes of the audio/telecom transmit FIFOs are 8

16-bit words and of the

audio/telecom receive FIFOs are 12

16-bit words. The MCP also contains a 21-bit data register used

to transmit codec register reads and writes, as well as another 21-bit register to receive the results of

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codec register reads. Touch-screen and ADC conversions are triggered, and the digital I/O lines are
controlled using codec register writes, while the converted data and the state of digital I/O lines is
accessed using a codec register read.

3.8.2.1

MCP Operation

Following reset, the MCP logic is disabled. To enable the MCP the applications program should first
clear the emergency underflow and overflow status bits, which are set following the reset, by writing
a 1 to these register bits (during a MCSR read access). Next, the user should program the MCP
control register with the desired mode of operation using a word write. The user may choose to either
"prime" the audio and telecom transmit FIFOs by writing up to eight 16-bit values each, or allow the
FIFO service requests to interrupt the CPU and trigger an EPB transfer to fill the FIFOs. Once the
off-chip codec is programmed and data resides within the bottom entries of the audio and/or telecom
FIFOs, transmission/reception of data begins on the transmit (SIBDOUT) and receive (SIBDIN)
pins. This is synchronously controlled by the 9.216 MHz (6.5 MHz in 13 MHz mode) serial clock
(SIBCLK) and serial frame (SIBSYNC) pins.

3.8.2.2

MCP Frame Format

Each MCP data frame is 128 bits long and is divided into two subframes: 0 and 1. Subframe 0 is used
by the MCP to communicate data to and from the UCB1100. Subframe 1 is not used by the MCP,
since it is typically used to interface to high-performance stereo codecs like Crystal's CS4216/18.

After the MCP is enabled, SIBCLK begins to transition at a fixed rate of 9.216 MHz (6.5 MHz in
the 13 MHz mode) and the start of the first frame is signalled by driving the SIBSYNC pin high for
one SIBCLK period. The rising-edge of SIBSYNC coincides with the rising-edge of SIBCLK, one
clock cycle immediately before each frame start. The SIBSYNC pulse causes the MCP to transfer
any available audio and/or telecom data from their respective transmit FIFOs to a 64-bit serial shifter,
setting the appropriate audio/telecom valid flags as well. If the codec control register contains valid
data, the register value and address is placed within the appropriate fields within the shifter, and the
read/write bit is configured to indicate which type of register access is to be made. For any field that
does not have valid data available, the previous value transmitted is used. As long as the MCP is
enabled, data frames are continuously transferred, even if valid data may not be available for
transmission. The format of data transmitted and received in subframe 0 is shown in Figure 3-3.
Data Format of MCP Subframe 0. Note that the UCB1100 data sheet uses Big Endian notation to
specify the MCP frame bit positions; however, Little Endian notation is used here to remain
consistent with the rest of the device specification.

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NOTE: AV Audio Data Valid, TV Telecom Data Valid, R/W write=1 read=0, Address - codec register

address

Figure 3-3. Data Format of MCP Subframe 0

Both the MCP and the off-chip codec drive data on the rising-edge of SIBCLK and latch data on its
falling-edge. After SIBSYNC is negated, subframe 0 begins and the data within the 64-bit shifter is
driven onto the SIBDOUT pin a bit at a time, starting with MSB[63]. As each bit of data is shifted
onto the SIBDOUT pin from one side of the shifter, a bit is also shifted into the opposite end of the
shifter from the SIBDIN pin. After 64 SIBCLK cycles elapse, all data within the shifter has been
transmitted, and the shifter contains the 64-bit receive data frame. The MCP takes the data from each
field and places it in its respective receive FIFO or data register. The next 64 SIBCLK cycles make
up subframe 1. When subframe 1 is active, the clocks to all MCP resources, which are not needed,
are turned off in order to conserve power.

Table 3-4

shows the pin timing of the MCP.

Figure 3-4. MCP Packet Organization

Bit

Audio Transmit Data

Address

R/
W

00000000

T
V

Telecom Transmit Data

Control
Register Write

Audio Receive Data

Address

R/
W

00000000

T
V

Telecom Receive Data

Control
Register Read

Frame Clock Count

...

127

128

Frame N

Frame N+1

Subframe

Subframe 0

Subframe 1

SIBCLK

...

SIBSYNC

...

SIBDOUT

[63]

[62]

...

[1]

[0]

[63]

...

[0]

[63]

SIBDIN

[63]

[62]

...

[1]

Bit

[63]

...

[0]

[63]

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Note that the transmit line is pulled low any time data is not being driven onto the pin. The UCB1100
has a programming option which allows it to either tristate or drive the receive line low when data is
not driven onto SIBDIN. As shown in

Figure 3-4

, the MCP frames occur back-to-back. The

SIBSYNC pin is driven high during the last clock (128th) of the frame to indicate the start of a new
frame the following SIBCLK period. Values contained within the transmit FIFOs are loaded to the
shift register on the rising-edge of SIBSYNC.

3.8.2.3

Audio and Telecom Sample Rates and Data Transfer

The UCB1100 contains an audio and telecom codec with sample rates that can be individually
programmed, and are derived from the 9.216 MHz (6.5 MHz in 13 MHz mode) serial clock
(SIBCLK), which is supplied by the MCP interface. This is derived originally from the divided chip
clock.

For the UCB1100 audio codec, with an input clock as above, valid sample rates are derived by
dividing the serial clock first by a fixed value of 32 and then by a value from 9 to 127. For the
UCB1100 telecom codec, the sample rate is derived by dividing the serial clock first by a fixed value
of 32 and then by a value from 16 to 127. Nominal sample frequencies are 7.2 kHz for the telecom
codec and 22.05 kHz for the audio codec. For a SIBCLK of 9.216 MHz, the sample rate of the
telecom codec using a divisor of 40, is exactly correct while for the audio codec, using a divisor of
13, the sample rate error is less than +0.5%. For a SIBCLK of 6.5 MHz, the sample rate error of the
telecom codec using a divisor of 28, is less than +0.75%, while for the audio codec using a divisor
of 9 the sample rate error is less than +2.5%. The codec and the MCP both contain an audio and a
telecom sample rate counter. These counters are used to achieve conversion rate synchronization
between the codec and the MCP, so that data may be coherently transferred between the MCP and
the codec. For the remainder of this description all references are made to the audio codec for brevity;
however, all information also applies to the telecom portion of the codec and the MCP.

Before enabling the audio codec, the audio sample rate counters within the codec and the MCP must
be programmed with the same divisor value so that they have the same clock rate. The codec's audio
sample rate divisor is programmed by issuing a control register write transfer and the MCP's divisor
is programmed using the CPU by writing to the MCP's control register. Both the MCP and the
codec's audio counters are reloaded with the programmed modulus value any time the audio portion
of the codec is enabled. This can also be accomplished by performing a control register write transfer
or whenever the sample rate counters reach zero.

The MCP and the audio codec decrement their counters in lock-step with one another, both starting
on the occurrence of the first SIBSYNC pulse after the audio codec is enabled. Samples/conversions
are made each time the audio codec's counter reaches zero.

Figure 3-5

shows the timing of the audio

codec enable, as well as decrements of the MCP and audio codec's sample counter.

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Figure 3-5. Audio Codec Enable Timing

Referring to the Figure 3-5. Audio Codec Enable Timing, "Ena" within the data frame on
SIBDOUT represents a control register write to the codec to enable the input portion of the audio
codec. The register is updated with the write at the end of subframe 0, and the audio enable signal
within the codec goes high. Both the MCP and codec's audio sample rate counters then start to
decrement on the next SIBSYNC pulse. In the example, a divisor value of 3 is used, causing the
counter to decrement to zero after 96 (32

3 = 96) SIBCLK cycles occur.

If the input portion of the audio codec is enabled when the counter reaches zero, a sample and A/D
conversion is made. The converted value is then placed into the correct field of the codec's serial
shift register for transmission back to the MCP in the next data frame. If the output portion of the
audio codec is enabled, an audio data value is taken from the received data supplied by the MCP and
is used for a D/A conversion. Data used in the D/A conversion is always taken from the previous
MCP input frame. If no new data is available within the MCP's audio transmit FIFO since the last
D/A conversion, the same data is used again (causing audio distortion).

Samples and conversions occur twice as shown in Figure 3-5. Audio Codec Enable Timing.
However, while the counter is decrementing for the third time, the CPU disables the audio codec by
issuing another control register write, represented by the "Dis" data frame on SIBDOUT. The
SIBSYNC pulse following the write causes the disable to take effect, and the MCP and codec's audio
sample rate counters are stopped and reset to their modulus value.

The MCP and the codec's audio sample rate counters must be enabled coherently, so that
synchronization is achieved between the two. This is accomplished by first programming both the
MCP and codec's sample rate modulus values, then performing a codec control register write to
enable the audio sampling rate counter within the codec. The MCP automatically decodes a write to

Subframe

0 1

SIBSYNC

SIBDOUT

Ena

Dis

Audio Ena

Counters

3...................3

Samp/Conv

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the audio codec input and output enable bits and enables the MCP's audio sample rate counter at the
same time as the codec's counter to ensure synchronization.

The UCB1100 has an individual data valid bit for audio and telecom A/D samples. Whenever these
bits are set in the data frame returned from the codec to the MCP, the audio and telecom data is taken
from the frame and placed in their respective receive FIFO. There are two different modes of
operation to control the setting of the audio and telecom data valid bits. The UCB1100 uses both
modes. In the first mode, a data valid bit is set any time a frame contains "reliable" data, (i.e., the
codec is enabled and at least one A/D sample has been taken). In this mode, once the data valid bit
is set, it remains set until the codec A/D input is disabled. In the second mode, the codec only sets
the data valid bit corresponding to a new A/D sample. Once, the data is transmitted to the MCP
within a receive data frame, the data valid bit is reset to zero for subsequent data frames until a new
A/D sample is triggered.

3.8.2.4

MCP FIFO Operation

The MCP contains two 8-word deep, 16-bit audio/telecom transmit FIFOs and two 12-word deep,
16-bit audio/telecom receive FIFOs. As in the previous section, the following description refers to
the audio codec for brevity; however, all concepts apply to the telecom portion as well.

For each incoming data frame, if the audio data valid bit is set, the 16-bit audio A/D sample is
extracted and placed in the audio receive FIFO. Nevertheless, note that the MCP also supports a
mode in which the audio data valid bits are ignored, and a number of the incoming frame samples
are not stored in the receive FIFOs. For instance, this may happen after the first sample (of an
incoming frame sequence) is saved to the FIFO, and the MCP's audio sample rate counter is used to
determine when a new A/D sample has been taken and is available within the incoming frame. Audio
data is transferred from the incoming data frames to the received FIFO only if the audio enable bit is
set within the MCP's status register. A set of input and sample counter value conditions determine
whether the audio enable bits are 1 or 0.

The MCP's audio sample rate counters are used to trigger when new D/A conversions are to be
transmitted to the codec. The user should take care in ensuring sample rate counters in the MCP are
synchronized with the respective sample rate counters in the codec, as described previously. When
the audio enable status bit transitions from a 0 to a 1 within the MCP status register, the next available
entry of data is taken from the audio transmit FIFO and is placed within the correct field in the MCP's
serial shifter. This value is then continuously transferred by the MCP in each data frame to the codec.
The codec only uses the value when its audio sample rate counter decrements to zero. After the audio
D/A conversion is made, both the codec and the MCP's audio sample rate counters reload with their
modulus value. This reload triggers the audio transmit FIFO to transfer the next available entry of
data to the MCP's serial shifter. Again, this value is continuously transmitted to the codec in each
data frame until it is used in the next audio D-to-A conversion.

The width of the audio and telecom FIFOs is 16 bits. However, in the UCB1100 the audio codec's
sample/conversion data size is 12 bits and the telecom is 14 bits. Samples are left justified within the
16-bit audio and telecom data fields in the MCP frame, as well as within the transmit and receive

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FIFOs. The user must ignore the non-significant bits. Figure 3-6. Format for the Audio and
Telecom FIFOs shows the required data alignment in the for the transmit and receive audio and
telecom FIFOs.

Figure 3-6. Format for the Audio and Telecom FIFOs

3.8.2.5

MCP Codec Control Register Data Transfer

The UCB1100 contains sixteen 16-bit registers used to configure the chip, store touch-screen and
ADC samples, as well as digital I/O pin state and edge interrupt status. These registers are read and
written via the MCP's serial interface using three fields of the MCP's data frame. Referring to

Table 3-3

, bits 15:0 contain the codec register value read from or written to the off-chip codec, bits

46:43 contain the register address of the current read or write, and Bit 42 is used by the MCP to
indicate a read or write cycle to the codec. These fields are configured by the CPU by writing to MCP
Data Register 2 and are then transmitted to the off-chip codec. These fields are also received in every
data frame, transmitted to the MCP from the codec, and are placed in MCP Data Register 2
(MCDR2), which in turn can be read by the CPU. Note that the contents of the addressed register,
which are sent along with the rest of the frame data to the codec, are returned in the receive data frame
regardless of the state of the read/write bit. Thus for write cycles, both a write and a read occurs, and
for read cycles, only a read occurs.

A codec register write is performed by writing a value to the MCDR2, or Frame Control Data
Receive/Transmit Register, which contains the value to store to the codec register, the address of the
codec register, and the read/write bit set to one. Once this register is written, its contents are
transferred to the correct fields within the serial shifter on the next rising-edge of the SIBSYNC
signal. The register information is transmitted to the UCB1100 during subframe 0, and the value is
written to the selected codec register at the end of subframe 0 (during the 65th bit of the frame). The
control register value and address are also returned to the MCP and stored in MCDR2. Typically, the
read/write bit is zero in the return frame. Because the addressed register is updated at the end of
subframe 0, the data returned during the frame in which the write occurred represents the previous
contents of the register. The updated value is returned during the next data frame.

A register read is performed by writing a value to MCDR2 which contains the address of the register
and the read/write bit set to a zero. Again, the data is transferred to the serial shifter on the next rising-
edge of the SIBSYNC signal and is transmitted to the UCB1100 during subframe 0. Because the
address and read/write control bit fields occur near the beginning of the serial stream output (or, in
other words, towards the end of the subframe -- Bit 63), the codec performs the read immediately

Bit

Audio Data

Bit

Telecom Data

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after the read/write bit is received (during the 41st bit of the frame). The value contained within the
addressed register is sent back to the MCP in the same data frame.

Once the codec control register is written with a value to execute a read or write, the operation is
performed every MCP data frame until a new value is written to the register. Thus, continual reads
or writes are made to the addressed codec register until a new read or write operation is configured.

3.8.3

ADC Interface -- Master Mode Only SSI1 (Synchronous Serial Interface)

The first synchronous serial interface allows interfacing to the following peripheral devices:

In the default mode, the device is compatible with the MAXIM MAX148/9 in external clock
mode. Similar SPI or Microwire compatible devices can be connected directly to the EP7211.

In the extended mode and with negative-edge triggering selected (the ADCCON and
ADCCKNSEN bits are set, respectively, in the SYSCON3 register), this device can be interfaced
to Analog Devices' AD7811/12 chip using NADCCS as a common RFS/TFS line.

Other features of the devices, including power management, can be utilized by software and the
use of the GPIO pins.

The clock output frequency is programmable and only active during data transmissions to save
power. There are four output frequencies selectable, which will be slightly different depending
whether the device is operating in a 13 MHz mode or a 18.432 MHz73.728 MHz mode (see Table
3-14. ADC Interface Operation Frequencies). The required frequency is selected by programming
the corresponding bits 16 and 17 in the SYSCON1 register. The sample clock (SMPCLK) always
runs at twice the frequency of the shift clock (ADCCLK).

The output channel is fed by an 8-bit shift register when the ADCCON bit of SYSCON3 is clear.
When ADCCON is set, up to 16 bits of configuration command can be sent, as specified in the
SYNCIO register. The input channel is captured by a 16-bit shift register. The clock and
synchronization pulses are activated by a write to the output shift register. During transfers the
SSIBUSY (synchronous serial interface busy) bit in the system status flags register is set. When the
transfer is complete and valid data is in the 16-bit read shift register, the SSEOTI interrupt is asserted
and the SSIBUSY bit is cleared.

An additional sample clock (SMPCLK) can be enabled independently and is set at twice the transfer
clock frequency.

Table 3-14. ADC Interface Operation Frequencies

SYSCON1

Bit 17

SYSCON1

Bit 16

13.0 MHz Operation ADCCLK

Frequency (kHz)

18.43273.728 MHz Operation

ADCCLK Frequency (kHz)

4.2

16.9

67.7

135.4

128

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This interface has no local buffering capability and is only intended to be used with low bandwidth
interfaces, such as for a touch-screen ADC interface.

3.8.4

Master/Slave SSI2 (Synchronous Serial Interface 2)

A second SPI/Microwire interface with full master/slave capability is provided by the EP7211. Data
rates in slave mode are theoretically up to 512 kbps, full duplex, although continuous operation at
this data rate will give an interrupt rate of 2 kHz, which is too fast for many operating systems. This
would require a worst case interrupt response time of less than 0.5 ms and would cause loss of data
through TX underruns and RX overruns.

The interface is fully capable of being clocked at 512 kHz when in slave mode. However, it is
anticipated that external hardware will be used to frame the data into packets. Therefore, although
the data would be transmitted at a rate of 512 kbps, the sustained data rate would in fact only be 85.3
kbps (i.e., 1 byte every 750

µs). At this data rate, the required interrupt rate will be greater than the

1 ms, which is acceptable.

There are separate half-word-wide RX and TX FIFOs (16 half-words each) and corresponding
interrupts which are generated when the FIFO's are half-full or half-empty as appropriate. The
interrupts are called SS2RX and SS2TX, respectively. Register SS2DR is used to access the FIFOs.

There are five pins to support this SSI port: SSIRXDA, SSITXFR, SSICLK, SSITXDA, and
SSIRXFR. The SSICLK, SSIRXDA, SSIRXFR, and SSITXFR signals are inputs and the
SSITXDA signal is an output in slave mode. In the master mode, SSICLK, SSITXDA, SSITXFR,
and SSIRXFR are outputs and SSIRXDA is an input. Master mode is enabled by writing a one to
the SS2MAEN bit (SYSCON2[9]). When the master/slave SSI is not required, to save power it can
be disabled by writing a zero to the SS2TXEN and the SS2RXEN bits also within the system control
register 2 (SYSCON2[4] [7]). When set, these two bits independently enable the transmit and receive
sides of the interface.

The master/slave SSI is synchronous, full duplex, and capable of supporting serial data transfers
between two nodes. Although the interface is byte-oriented, data is loaded in blocks of two bytes at
a time. Each data byte to be transferred is marked by a frame sync pulse, lasting one clock period,
and located one clock prior to the first bit being transferred. Direction of the SSI2 ports, in slave
mode, is shown in Figure 3-7. SSI2 Port Directions in Slave and Master Mode.

Figure 3-7. SSI2 Port Directions in Slave and Master Mode

Slave 7211

SSIRXFR

SSITXFR

SSICLK

SSIRXDA

SSITXDA

Master 7211

SSIRXFR

SSITXFR

SSICLK

SSITXDA

SSIRXDA

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Data on the link is sent MSB first and coincides with an appropriate frame sync pulse, of one clock
in duration, located one clock prior to the first data bit sent (i.e., MSB). It is not possible to send data
LSB first.

When operating in master mode, the clock frequency is selected to be the same as the ADC
interface's (master mode only SSI1) -- that is, the frequencies are selected by the same bits 16 and
17 of the SYSCON1 register (i.e., the ADCKSEL bits). Thus, the maximum frequency in master
mode is 128 kbytes/s. The interface will support continuous transmission at this rate assuming that
the OS can respond to the interrupts within 1 ms to prevent over/underruns.

NOTE: To allow synchronization to the incoming slave clock, the interface enable bits will not take effect until

one SSICLK cycle after they are written and the value read back from SYSCON2. The enable bits
reflect the real status of the enables internally. Hence, there will be a delay before the new value pro-
grammed to the enable bits can be read back.

The timing diagram for this interface can be found in the AC Characteristics section of this
document.

3.8.4.1

Read Back of Residual Data

All writes to the transmit FIFO must be in half-words (i.e., in units of two bytes at a time). On the
receive side, it is possible that an odd number of bytes will be received. Bytes are always loaded into
the receive FIFO in pairs, so in the case of a single residual byte remaining at the end of a
transmission, it will be necessary for the software to read the byte separately. This is done by reading
the status of two bits in the SYSFLG2 register to determine the validity of the residual data. These
two bits (RESVAL, RESFRM) are both set high when a residual is valid; RESVAL is cleared on
either a new transmission or on reading of the residual bit by software. RESFRM is cleared only on
a new transmission. By popping the residual byte into the RX FIFO and then reading the status of
these bits it is possible to determine if a residual bit has been correctly read.

Figure 3-8. Residual Byte Reading illustrates this procedure. The sequence is as follows: read the
RESVAL bit, if this is a 0, no action needs to be taken. If this is a 1, then pop the residual byte into
the FIFO by writing to the SS2POP location. Then read back the two status bits RESVAL and
RESFRM. If these bits read back 01, then the residual byte popped into the FIFO is valid and can be
read back from the SS2DR register. If the bits are not 01, then there has been another transmission
received since the residual read procedure has been started. The data item that has been popped to
the top of the FIFO will be invalid and should be ignored. In this case, the correct byte will have been
stored in the most significant byte of the next half-word to be clocked into the FIFO.

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NOTE: All the writes/reads to the FIFO are done word at a time (data on the lower 16 bits is valid and upper

16 bits are ignored)...

Figure 3-8. Residual Byte Reading

Software manually pops the residual byte into the RX FIFO by writing to the SS2POP location (the
value written is ignored). This write will strobe the RX FIFO write signal, causing the residual byte
to be written into the FIFO.

3.8.4.2

Support for Asymmetric Traffic

The interface supports asymmetric traffic (i.e., unbalanced data flow). This is accomplished through
separate transmit and receive frame sync control lines. In operation, the receiving node receives a
byte of data on the eight clocks following the assertion of the receive frame sync control line. In a
similar fashion, the sending node can transmit a byte of data on the eight clocks following the
assertion of the transmit frame sync pulse. There is no correlation in the frequency of assertions of
the RX and TX frame sync control lines (SSITXFR and SSIRXFR). Hence, the RX path may bear
a greater data throughput than the TX path, or vice versa. Both directions, however, have an absolute
maximum data throughput rate determined by the maximum possible clock frequency, assuming that
the interrupt response of the target OS is sufficiently quick.

3.8.4.3

Continuous Data Transfer

Data bytes may be sent/received in a contiguous manner without interleaving clocks between bytes.
The frame sync control line(s) are eight clocks apart and aligned with the clock representing bit D0
of the preceding byte (i.e., one bit in advance of the MSB).

3.8.4.4

Discontinuous Clock

In order to save power during the idle times, the clock line is put into a static low state. The master
is responsible for putting the link into the Idle State. The Idle State will begin one clock, or more,
after the last byte transferred and will resume at least one clock prior to the first frame sync assertion.
To disable the clock, the TX section is turned off.

Residual bit valid

New RX byte received

Pop FIFO

New RX b yte
received

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In Master mode, the design does not support the discontinuous clock.

3.8.4.5

Error Conditions

RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2 register. This register
should be accessed at periodic intervals by the application software. The status register should be
read each time the RX FIFO interrupts are generated. At this time the error condition (i.e., overrun
flag) will indicate that an error has occurred but cannot convey which byte contains the error. Writing
to the SRXEOF register location clears the overrun flag. TX FIFO underflow condition is detected
and conveyed via a bit in the SYSFLG2 register, which is accessed by the application software. A
TX underflow error is cleared by writing data to be transmitted to the TX FIFO.

3.8.4.6

Clock Polarity

Clock polarity is fixed. TX data is presented on the bus on the rising edge of the clock. Data is latched
into the receiving device on the falling edge of the clock. The TX pin is held in a tristate condition
when not transmitting.

3.9

LCD Controller with Support for On-Chip Frame Buffer

The LCD controller provides all the necessary control signals to interface directly to a single panel
multiplexed LCD. The panel size is programmable and can be any width (line length) from 32 to
1024 pixels in 16 pixel increments. The total video frame buffer size is programmable up to 128
Kbytes. This equates to a theoretical maximum panel size of 1024

256 pixels in 4-bits-per-pixel

mode. The video frame buffer can be located in any portion of memory controlled by the chip selects,
or system DRAM. Its start address will be fixed at address 0x0000000 within each chip select or
DRAM bank. The start address of the LCD video frame buffer is defined in the FBADDR register
bits [3:0]. These bits become the most significant nibble of the external address bus. The default start
address is 0xC000 0000 (FBADDR = 0xC). A system can be built using no DRAM and the on-chip
SRAM (OCSR) will then serve as the LCD video frame buffer and miscellaneous data store. The
LCD video frame buffer start address should be set to 0x6 in this option. Programming of the register
FBADDR is only permitted when the LCD is disabled (this is to avoid possible cycle corruption
when changing the register contents while a LCD DMA cycle is in progress). There is no hardware
protection to prevent this. It is necessary for the software to disable the LCD controller before
reprogramming the FBADDR register. Full address decoding is provided for the OCSR, up to the
maximum video frame buffer size programmable into the LCDCON register. Beyond this, the
address is wrapped around. The frame buffer start address must not be programmed to 0x4 or 0x5 if
either CL-PS6700 interface is in use (PCMEN1 or PCMEN2 bits in the SYSCON2 register are
enabled). FBADDR should never be programmed to 0x7 or 0x8, as these are the locations for the on-
chip Boot ROM and internal registers.

The screen is mapped to the video frame buffer as one contiguous block where each horizontal line
of pixels is mapped to a set of consecutive bytes or words in the video RAM. The video frame buffer
can be accessed word wide as pixel 0 is mapped to the LSB in the buffer such that the pixels are
arranged in a Little Endian manner.

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The pixel bit rate, and hence the LCD refresh rate, can be programmed from 18.432 MHz to 576 kHz
when operating in 18.43273.728 MHz mode, or 13 MHz to 203 kHz when operating from a 13 MHz
clock. The LCD controller is programmed by writing to the LCD control register (LCDCON). The
LCDCON register should not be reprogrammed while the LCD controller is enabled.

The LCD controller also contains two 32-bit palette registers, which allow any 4-, 2-, or 1-bit pixel
value to be mapped to any of the 16 grey scale values available. The required DMA bandwidth to
support a ½ VGA panel displaying 4-bits-per-pixel data at an 80 Hz refresh rate is approximately 6.2
Mbytes/sec. Assuming the frame buffer is stored in a 32-bit wide, 50 ns EDO DRAM bank, the
maximum theoretical bandwidth available is 86 Mbytes/sec at 36.864 MHz, or 29.7 Mbytes/sec at
13 MHz. If a 16-bit wide, 50 ns EDO DRAM bank is used, this drops to 30 Mbytes/sec at 36.864
MHz; still leaving sufficient bandwidth for other memory activity.

The LCD controller uses a nine stage 32-bit wide FIFO to buffer display data. The LCD controller
requests new data when there are five words remaining in the FIFO. This means that for a ½ VGA
display at 4-bits-per-pixel and 80 Hz refresh rate, the maximum allowable DMA latency is approx.
3.2

µs (640

240

4bpp

80 Hz/8 bits/byte

5 words (=20 bytes) = 3.2

µs). The worst-case latency

is the total number of cycles from when the DMA request appears to when the first DMA data word
actually becomes available at the FIFO. DMA has the highest priority, so it will always happen next
in the system. The worst case latency will occur when the CPU is doing a STM (store multiple)
instruction of all 16 registers to DRAM, which it has to complete before the DMA can get access to
the bus. The maximum number of cycles required is 36 from the point at which the DMA request
occurs to the point at which the STM is complete (see DRAM timing diagrams), then another 6
cycles before the data actually arrives at the FIFO from the first DMA read. This creates a total of 42
cycles. Assuming the frame buffer is located in 32-bit wide, 70 ns FPM or EDO DRAM memory,
the worst case latency is almost exactly 3.2

µs, with 13 MHz page mode cycles. With each cycle

consuming ~77 ns (i.e., 1/13 MHz), the value of 3.2

µs comes from 42 cycles

77 ns/cycle = ~3.23

µs. If 16-bit wide, 70ns FPM or EDO DRAM is being used, then the worst case latency will double.
In this case, the maximum permissible display size will be halved, to approx. 320

240 pixels,

assuming the same pixel depth and refresh rate has to be maintained. If the frame buffer is to be
stored in static memory, then further calculations must be performed. If 18 MHz mode is selected,
and 32-bit wide, 70 ns FPM or EDO DRAM is being used, then the worst case latency will be 2.26
µs (i.e., 42 cycles

54 ns/cycle). If 36 MHz mode is selected, and 32-bit wide, 50 ns EDO DRAM

is being used, then the worst case latency drops down to 1.49

µs. This calculation is a little more

complex for 36 MHz mode of operation. The total number of cycles = (12

4) + 7 = 55. Thus, 55

27 ns = ~1.49

µs.

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3.10

Internal UARTs (Two) and SIR Encoder

The EP7211 contains two built-in UARTs that offers similar functionality to National
Semiconductor's 16C550A device. Both UARTs can support bit rates of up to 115.2 Kbps and
include two 16-byte FIFOs: one for receive and one for transmit.

One of the UARTs (UART1) supports the three modem control input signals CTS, DSR and DCD.
The additional RI input, and RTS and DTR output modem control lines are not explicitly supported
but can be implemented using GPIO ports in the EP7211. UART2 has only the RX and TX pins.

UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control).
Three interrupts can be generated by UART1: RX, TX, and modem status interrupts. Only two can
be generated by UART2: RX and TX. The RX interrupt is asserted when the RX FIFO becomes half
full or if the FIFO is non-empty for longer than three character length times with no more characters
being received. The TX interrupt is asserted if the TX FIFO buffer reaches half empty. The modem
status interrupt for UART1 is generated if any of the modem status bits change state. Framing and
parity errors are detected as each byte is received and pushed onto the RX FIFO. An overrun error
generates an RX interrupt immediately. All error bits can be read from the 11-bit wide data register.
The FIFOs can also be programmed to be one byte depth only (i.e., like a conventional 16450 UART
with double buffering).

The EP7211 also contains an IrDA (Infrared Data Association) SIR protocol encoder as a post-
processing stage on the output of UART1. This encoder can be optionally switched in to the TX and
RX signals of UART1, so that these can be used to drive an infrared interface directly. If the SIR
protocol encoder is enabled, the UART TXD1 line is held in the passive state and transitions of the
RXD1 line will have no effect. The IrDA output pin is LEDDRV, and the input from the photodiode
is PHDIN. Modem status lines will cause an interrupt (which can be masked) irrespective of whether
the SIR interface is being used.

Both the UARTs operate in a similar manner to the industry standard 16C550A. When CTS is
deasserted on the UART, the UART does not stop shifting the data. It relies on software to take
appropriate action in response to the interrupt generated.

Baud rates supported for both the UARTs are dependent on frequency of operation. When operating
from the internal PLL, the interface supports various baud rates from 115.2 kbps downwards. The
master clock frequency is chosen so that most of the required data rates are obtainable exactly. When
operating with a 13.0 MHz external clock source, the baud rates generated will have a slight error,
which is less than or equal to 0.75%. The rates obtainable from the 13 MHz clock include 9.6 k, 19.2
k, 38 k, 58 k and 115.2 kbps. See

Section 5.9.2

in the register programming section of this spec for

full details of the available bit rates in the 13 MHz mode.

3.11

Timer Counters

Two identical timer counters are integrated into the EP7211. These are referred to as TC1 and TC2.
Each timer counter has an associated 16-bit read/write data register and some control bits in the
system control register. Each counter is loaded with the value written to the data register

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immediately. This value will then be decremented on the second active clock edge to arrive after the
write (i.e., after the first complete period of the clock). When the timer counter under flows (i.e.,
reaches 0), it will assert its appropriate interrupt. The timer counters can be read at any time. The
clock source and mode are selectable by writing to various bits in the system control register. When
run from the internal PLL, 512 kHz and 2 kHz rates are provided. When using the 13 MHz external
source, the default frequencies will be 541 kHz and 2.115 kHz, respectively. However, only in non-
PLL mode, an optional divide by 26 frequency can be generated (thus generating a 500 kHz
frequency when using the 13 MHz source). This divider is enabled by setting the OSTB (Operating
System Timing Bit) in the SYSCON2 register (Bit 12). When this bit is set high to select the 500 kHz
mode, the 500 kHz frequency is routed to the timers instead of the 541 kHz clock. This does not
affect the frequencies derived for any of the other internal peripherals.

NOTE: When the EP7211 is in the Standby State, the timer counters are disabled.

The timer counters can operate in two modes: free running or pre-scale.

3.11.1

Free Running Mode

In the free running mode, the counter will wrap around to 0xFFFF when it under flows and it will
continue to count down. Any value written to TC1 or TC2 will be decremented on the second edge
of the selected clock.

3.11.2

Prescale Mode

In the prescale mode, the value written to TC1 or TC2 is automatically re-loaded when the counter
under flows. Any value written to TC1 or TC2 will be decremented on the second edge of the
selected clock. This mode can be used to produce a programmable frequency to drive the buzzer (i.e.,
with TC1) or generate a periodic interrupt.

3.12

Realtime Clock

The EP7211 contains a 32-bit realtime clock (RTC). This can be written to and read from in the same
way as the timer counters but it is 32 bits wide. The RTC is always clocked at 1 Hz, generated from
the 32.768 kHz oscillator. It also contains a 32-bit output match register; this can be programmed to
generate an interrupt when the time in the RTC matches a specific time written to this register. The
RTC can only be reset by an NPOR cold reset. Because the RTC data register is updated from the 1
Hz clock derived from the 32 kHz source, which is asynchronous to the main memory system clock,
the data register should always be read twice to ensure a valid and stable reading. This also applies
when reading back the RTCDIV field of the SYSCON1 register, which reflects the status of the six
LSBs of the RTC counter.

3.13

Dedicated LED Flasher

The LED flasher feature enables an external pin (PD[0]/LEDFLSH) to be toggled at a programmable
rate and duty ratio -- with the intention that the external pin is connected to an LED. This module is
driven from the RTC's 32.768 kHz oscillator and allows it to work in all running modes because no

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CPU intervention is needed once its rate and duty ratio have been configured (via the LEDFLSH
register). The LED flash rate period can be programmed for 1, 2, 3, or 4 seconds. The duty ratio can
be programmed such that the mark portion can be 1/16, 2/16, 3/16, ..., 16/16 of the full cycle. The
external pin can provide up to 4 mA of drive current.

3.14

Two PWM Interfaces

Two Pulse Width Modulator (PWM) duty ratio clock outputs are provided by the EP7211. When the
device is operating from the internal PLL, this will run at a frequency of 96 kHz. These signals are
intended for use as drives for external DC-to-DC converters in the Power Supply Unit (PSU)
subsystem. External input pins that would normally be connected to the output from comparators
monitoring the external DC-to-DC converter output are also used to enable these clocks. These are
the FB[0:1] pins. The duty ratio (and hence PWMs on time) can be programmed from 1 in 16 to 15
in 16. The sense of the PWM drive signal (active high or low) is determined by latching the state of
this drive signal during power on reset (i.e., a pull-up on the drive signal will result in a active low
drive output, and visa versa). This allows either positive or negative voltages to be generated by the
external DC-to-DC converter. PWMs are disabled by writing zeros into the drive ratio fields in the
PMPCON Pump Control register.

NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs, instead of the

FB pins. The clocks that source the PWMs are disabled when the drive ratio fields are zeroed.

3.15

State Control

The EP7211 supports the following Power Management States: Standby, Idle, and Operating.

In the description below, the RUN/CLKEN pin can be used either for the RUN functionality, or the
CLKEN functionality to allow an external oscillator to be disabled in the 13 MHz mode. Either RUN
or CLKEN functionality can be selected according to the state of the CLKENSL bit in the
SYSCON2 register.

The Standby State equates to the system being switched "off" (i.e., no display, and the main oscillator
is shut down). When the 18.43273.728 MHz mode is selected, the PLL will be shut down. In the 13
MHz mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if
required, be used to disable an external oscillator.

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In the Standby State, all the system memory and state is maintained and the system time is kept up-
to-date. The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except
for the low power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher.
The RUN signal is driven low when in the Standby State. This signal can be used externally in the
system to power down other system modules.

Whenever the EP7211 is in the Standby State, the external address and data buses are driven low.
The RUN signal is used internally to force these buses to be driven low. This is done to prevent
peripherals that are powered-down from draining current. Also, the internal peripheral's signals get
set to their Reset State.

When first powered, or reset by the NPOR (Not Power On Reset) signal, the EP7211 is forced into
the Standby State. This is known as a cold reset, and is the only completely asynchronous reset to the
EP7211. When leaving the Standby State after a cold reset, external wake up is the only way for
waking up the device. When leaving the Standby State after non-cold reset conditions (i.e., the
software has forced the device into the Standby State), the transition to the Operating State can be
caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when
entering the Standby State from the Operating State, the software will leave some interrupt sources
enabled. Once the refresh enable register bit is enabled for the DRAMs, any transition to the Standby
State will force the DRAMs to the self-refresh state before stopping the PLL or external oscillator.

Table 3-15. Peripheral Status in Different Power Management States

Address (W/B)

Operating

Idle

Standby

NPOR

RESET

NRESET

RESET

DRAM Control

SELFREF

Off

SELFREF

UARTs

Off

Reset

LCD FIFO

Reset

LCD

Off

Reset

ADC Interface

Off

Reset

SSI2 Interface

Off

Reset

MCP Interface

Off

Reset

Codec

Off

Reset

Timers

Off

Reset

RTC

LED Flasher

Reset

DC-to-DC

Off

Reset

CPU

Off

Reset

Interrupt Control

Reset

PLL/CLKEN Signal

Off

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NOTE: The CPU cannot be awakened by the TINT, WEINT, and BLINT interrupts when in the Standby State.

Typically, software writes to the Standby internal memory location to cause the transition from the
Operating State to the Standby State. Before entering the Standby State, if external I/O devices (such
as the CL-PS6700s connected to NCS[4] or NCS[5]) are in use, the software must check to ensure
that they are idle before issuing the write to the Standby State location.

Before entering the Standby State, the software must properly disable the MCP. Failing to do so will
result in higher than expected power consumption in the Standby State, as well as unpredictable
operation of the MCP. The MCP can be re-enabled after transitioning back to the Operating State.

The system can also be forced into the Standby State by hardware if the NPWRFL or NURESET
inputs are forced low. In this case the transition is synchronized with DRAM cycles to avoid any
glitches or short cycles.

The only exit from the Standby State is to the Operating State.

The system will only transition to the Operating State from the Standby State under the following
conditions: when the NPWRFL input pin is high and either the NEXTPWR input pin is low or the
BATOK input pin is high. This prevents the system from starting when the power supply is
inadequate (e.g., the main batteries are low), corresponding to a low level on NPWRFL or BATOK.

From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock
running, the EP7211 will be initialized into a state where it is ready to start and is waiting for the
CPU to start receiving its clock. The CPU will still be held in reset at this point. After the first clock
is applied, there will be a delay of about eight clock cycles before the CPU is first clocked. This is to
allow the clock to the CPU to settle.

During the Standby State, the UARTs are disabled and cannot detect any activity (e.g., start bit) on
the receiver. If this functionality is required then this can be accomplished in software by the
following method:

1) Permanently connect the RX pin to one of the active low external interrupt pins.

2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the

UART is enabled.

3) Send a preamble that consists of one start bit, 8-bits of zero, and one stop bit. This will cause the

EP7211 to wake and execute the enabled interrupt vector.

The UART will automatically be re-enabled when the processor re-enters the Operating State, and
the preamble will be received. Since the UART was not awake at the start of the preamble, the timing
of the sample point will be off-center during the preamble byte. However, the next byte transmitted
will be correctly aligned. Thus, the actual first real byte to be received by the UART will get captured
correctly.

If in the Operating State, the Idle State can be entered by writing to a special internal memory
location in the EP7211. If an interrupt or wakeup event occurs, the EP7211 will return immediately
back to the Operating Stateand execute the next instruction.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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In the Idle State, the device functions just like it does when in the Operating State. However, the CPU
clock is halted while it waits for an event such as a key press to generate an interrupt, or a rising edge
on the external WAKEUP pin. The PLL (in 18.43273.728 MHz mode) or the external 13 MHz
clock source always remains active in the Idle State.

Figure 3-10. State Diagram shows a state diagram for the EP7211.

Figure 3-10. State Diagram

3.16

Resets

There are three asynchronous resets to the EP7211, these are NPOR, NPWRFL and NURESET. If
any of these is active, a system reset is generated internally. This will clear all internal registers in
the EP7211 to zero (except the DRAM refresh period register (DRFPR), and the RTC data and match
registers, which are only cleared by an active NPOR). This ensures that the DRAM contents and
system time is preserved through a user reset or power fail condition. Any reset will also reset the
CPU and cause it to start execution at the reset vector when the EP7211 returns to the Operating
State.

Internal to the EP7211, three different signals are used to reset storage elements. These are NPOR,
NSYSRES and NSTBY. NPOR is an external signal. NSTBY is equivalent to the external RUN
signal.

NPOR (Not Power On Reset) is the highest priority reset signal. When active (low), it will reset all
storage elements in the EP7211. NPOR active forces NSYSRES and NSTBY active. NPOR will
only be active after the EP7211 is first powered up and not during any other resets. NPOR active
will clear all flags in the status register apart from the cold reset flag (CLDFLG) bit, which is set.

NSYSRES (Not System Reset) is generated internally to the EP7211 if NPOR, NPWRFL or
NURESET are active. It is the second highest priority reset signal, used to asynchronously reset
most internal registers in the EP7211. NSYSRES active forces NSTBY and RUN low. NSYSRES
is used to reset the EP7211 and force it into the Standby State with no co-operation from software.
The CPU is also reset. The memory controller will place all DRAMs in self refresh mode, thus

Standby

Operating

Idle

Interrupt or rising wakeup

Write to standby location,
power fail, or user reset

Interrupt, rising wakeup

Write to halt location

NPOR, power fail, or
user reset

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preserving the contents through a system reset. This is the reason the DRAM refresh period register
is not cleared by a system reset.

The NSTBY and RUN signals are high when the EP7211 is in the Operating or Idle States and low
when in the Standby State. The main system clock is valid when NSTBY is high. The NSTBY signal
will disable any peripheral block that is clocked from the master clock source (i.e., everything except
for the RTC). In general, a system reset will clear all registers and NSTBY will disable all peripherals
that require a main clock. The following peripherals are always disabled by a low level on NSTBY:
two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI interfaces. In
addition, when in the Standby State, the LCD controller and PWM drive are also disabled.

When operating from an external 13 MHz oscillator which has become disabled in the Standby State
by using the CLKEN signal (i.e., with CLKENSL = 0), the oscillator must be stable within 0.125 s
from the rising edge of the CLKEN signal.

3.17

Clocks

There are two clocking modes for the EP7211. Either an external clock input can be used or the on-
chip PLL. The clock source is selected by a strapping option on Port E, Pin 2 (PE[2]). If PE[2] is
high at the rising edge of NPOR (i.e., upon power-up), the external clock mode is selected. If PE[2]
is low, then the on-chip PLL mode is selected.

The architecture for the EP7211 device contains several separate sections of logic. Some of them are
the ARM720T processor, the peripherals, and the address/data bus sections. The peripherals section
has its own dedicated bus structure called the Embedded Peripheral Bus (EPB). From the
ARM720T's point of view, the peripherals are strobed devices. Each unique peripheral device does
have its own dedicated clock source supplied to it according to its clock frequency requirements.
However, when the EP7211 is in the PLL mode, the actual frequencies will be different than when
in the external clock mode. See each peripheral device section for more details. The section below
describes the clocking for both the ARM720T and address/data bus sections.

3.17.1 On-Chip PLL

The ARM720T clock can be programmed to run at 18.432 MHz, 36.864 MHz, 49.152 MHz or
73.728 MHz. The PLL frequency is fixed at twice the highest possible CPU clock frequency
(147.456 MHz). The PLL uses an external 3.6864 MHz crystal. On power-up, if the device has been
strapped to use the on-chip PLL, then the device will start up with both the ARM720T and
address/data buses configured to run at 18.432 MHz by default. After power-up, the clock frequency
can be changed by software. If the clock frequency is changed to be 36 MHz, both the ARM720T
and the address/data buses will be clocked at 36 MHz as well. When the clock frequency is selected
higher than 36 MHz, only the ARM720T gets clocked at this higher speed. The address/data will be
fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the
SYSCON3 register. The clock frequency selection does not effect the individual dedicated peripheral
clock sources. In other words, all the peripheral clocks are fixed, regardless of the PLL mode clock
speed selected for the ARM720T.

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When the PLL mode is selected, the EXPCLK pin becomes an output. This output signal can then
be used to supply a synchronized clock source to external devices (e.g., a CL-PS6700 PC Card
controller device). When in the PLL mode, PE[2] can be used as a GPIO after power-up.

NOTE: After modifying the CLKCTL[1:0] bits, the next instruction should always be a NOP.

3.17.2 External Clock Input (13 MHz)

An external 13 MHz crystal oscillator can be used to drive all of the EP7211. On power-up, if the
device has been strapped to use the external clock, the ARM720T and the address/data buses both
get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different
frequencies than in the PLL mode. In this configuration, the PLL will not be used at all. The clock
signal should be connected to the EXPCLK pin of the EP7211. In this mode, EXPCLK becomes an
input.

If the CLKENSL bit is set low, then pin CLKEN/RUN (an output pin) provides the CLKEN signal
that can be used to start and stop the external 13 MHz clock source (i.e., the oscillator) used to supply
the clock for the EP7211 and the PWM. In this case, when CLKEN is active (high), it can be used
to enable the external 13 MHz clock source, and when low, it can be used to disable it.

When the Standby State is entered in 13 MHz mode, the 13 MHz source is disabled at the EXPCLK
input pin pad until the Standby State is exited. Therefore, the external clock source does not have to
be disabled to be able to disable the clocks internally.

When in the 13 MHz mode, if the CLKENSL bit is set high, then the Standby State is exited
immediately on a wakeup event or an enabled interrupt occurring. If CLKENSL is set low, then the
EP7211 will set CLKEN high after an interrupt or wakeup event occurs, then wait for between 0.125
s and 0.25 s to allow an external oscillator time to stabilize before the clock is enabled through to the
CPU. Only a non-masked interrupt (e.g., realtime clock match), Port A event (corresponding to a
keypress), or WAKEUP signal asserted will wakeup the EP7211 out of the Standby State. The
timing is shown below for the case where CLKENSL is low:

NOTE: When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from their default value of

`00'.

Figure 3-11. CLKEN Timing Entering the Standby State

13 MHz

CLKEN

CLKEN timing while entering STDBY mode

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Figure 3-12. CLKEN Timing Leaving the Standby State

3.18

Dynamic Clock Switching When in the PLL Clocking Mode

The clock frequency used for the CPU and the buses is controlled by programming the
CLKCTL[1:0] bits in the SYSCON3 register. When this occurs, the state controller switches from
the current to the new clock frequency as soon as possible without causing a glitch on the clock
signals. The glitch-free clock switching logic waits until the clock that is currently in use and the
newly programmed clock source are both low, and then switches from the previous clock to the new
clock without a glitch on the clocks.

3.19

Endianness

The EP7211 uses a Little Endian configuration for internal registers. However, it is possible to
connect the device to a Big Endian external memory system. The bigend bit in the ARM720T control
register sets whether the EP7211 treats words in memory as being stored in Big Endian or Little
Endian format. Memory is viewed as a linear collection of bytes numbered upwards from zero. Bytes
0 to 3 hold the first stored word, bytes 4 to 7 the second, and so on. In the Little Endian scheme, the
lowest numbered byte in a word is considered to be the least significant byte of the word and the
highest numbered byte is the most significant. Byte 0 of the memory system should be connected to
data lines 7 through 0 (D[7:0]) in this scheme. In the Big Endian scheme the most significant byte of
a word is stored at the lowest numbered byte, and the least significant byte is stored at the highest
numbered byte. Therefore, Byte 0 of the memory system should be connected to data lines 31
through 24 (D[31:24]). Load and store are the only instructions affected by the Endianness.

The following tables demonstrate the behavior of the EP7211 in Big and Little Endian mode,
including the effect of performing non-aligned word accesses. The register definition section of this

EXPCLK

(int) RUN

Intr./

WAKEUP

CLKEN

T42

CLKEN timing -- coming out of STDBY

NOTE: T42 = 0.125 s to 0.25

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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specification defines the behavior of the internal EP7211 registers in the Big Endian mode in more
detail.

The NCAS[3:0] lines for DRAM should always be connected with the same byte lane irrespective
of the Endianness, such that NCAS[0] will be connected with D[7:0], and NCAS[3] with D[31:24].
Thus, in a Little Endian system, NCAS[0] will be asserted for a read/write to byte 0 of DRAM and
in a big Endian system NCAS[3] will be asserted to access byte 0 of DRAM.

NOTE: dc = don't care

Table 3-16. Effect of Endianness on Read Operations

Address

(W/B)

Data in

Memory

Byte Lanes to Memory/Ports/Registers

R0 Contents

Big Endian Memory

Little Endian Memory

7:0

15:8

23:1

31:2

7:0

15:8

23:1

31:2

Big

Endian

Little

Endian

Word + 0 (W)

11223344

Word + 1 (W)

11223344

44112233

Word + 2 (W)

11223344

33441122

Word + 3 (W)

11223344

22334411

Word + 0 (B)

11223344

00000011

00000044

Word + 1 (B)

11223344

00000022

00000033

Word + 2 (B)

11223344

00000033

00000022

Word + 3 (B)

11223344

00000044

00000011

Table 3-17. Effect of Endianness on Write Operations

Address

(W/B)

Register

Contents

Byte Lanes to Memory/Ports/Registers

Big Endian Memory

Little Endian Memory

7:0

15:8

23:16

31:24

7:0

15:8

23:16

31:24

Word + 0 (W)

11223344

Word + 1 (W)

11223344

Word + 2 (W)

11223344

Word + 3 (W)

11223344

Word + 0 (B)

11223344

Word + 1 (B)

11223344

Word + 2 (B)

11223344

Word + 3 (B)

11223344

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NOTE: Bold indicates active byte lane.

3.20

Maximum EP7211-Based System

A maximum configured system using the EP7211 is shown in Figure 3-13. A Maximum EP7211
Based System. This system assumes all the DRAMs and ROMs are 16-bit wide devices. The
keyboard may be connected to more GPIO bits than shown to allow greater than 64 keys, however
these extra pins will not be wired into the WAKEUP pin functionality.

Figure 3-13. A Maximum EP7211 Based System

LCD MODULE

KEYBOARD

BATTERY

DC-TO-DC

CONVERTERS

ADC

DIGITIZER

IR LED AND

PHOTODIODE

× RS-232

TRANSCEIVERS

ADDITIONAL I/O

CL-PS6700

PC CARD

CONTROLLER

PC CARD

SOCKET

NCS[4]
PB0
EXPCLK

DD[3:0]

CL1
CL2

D[31:0]

A[27:0]

COL[7:0]

PA[7:0]

INPUT

NMOE
WRITE

NRAS[1]
NRAS[0]

NCAS[0]
NCAS[1]

NCAS[2]
NCAS[3]

PB[7:0]

PD[7:0]

PE[2:0]

NPOR

NPWRFL

BATOK

NEXTPWR
NBATCHG

RUN

WAKEUP

NCS[0]
NCS[1]

DRIVE[1:0]

FB[1:0]

EP7

ADCCLK

NADCCS
ADCOUT

ADCIN

SMPCLK

LEDDRV

PHDIN

RXD1/2

TXD1/2

DSR

CTS

DCD

CS[n]
WORD

NCS[2]
NCS[3]

×16

DRAM

×16

DRAM

×16

FLASH

×16

FLASH

×6

ROM

EXTERNAL MEMORY-
MAPPED EXPANSION

BUFFERS

AND

LATCHES

×16

ROM

×16

DRAM

×16

DRAM

POWER

SUPPLY UNIT

AND

COMPARATORS

CRYSTAL

CODEC/SSI2/

MCP

SSICLK

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

MOSCIN

LEDFLSH

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Functional Description

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NOTE: A system can only use one of the following peripheral interfaces at any given time: SSI2, codec, or

MCP.

3.21

Boundary Scan

IEEE 1149.1 compliant JTAG is provided with the EP7211. (It should be noted that a full system
reset, BNRES[0] = '0', must be applied to the device initially.)

The INTEST function will not be supported for the EP7211.

Additional user-defined instructions exist, but these are not relevant to board-level testing. For
further information please refer to the ARM DDI 0087E ARM720T Datasheet Section 8.

As there are additional scan-chains within the ARM720T processor, it is necessary to include a scan-
chain select function -- shown as SCAN_N in Table 3-18. Instructions Supported in JTAG
Mode. To select a particular scan chain, this function must be input to the TAP controller, followed
by the 4-bit scan-chain identification code. The identification code for the boundary scan chain is
0011.

Note that it is only necessary to issue the SCAN_N instruction if the device is already in the JTAG
mode. The boundary scan chain is selected as the default on test-logic reset and any of the system
resets.

The contents of the device ID-register for the EP7211 are shown below:

This is equivalent to 0F0F0F0F Hex. Note this is the ID-code for the ARM720T processor.

Table 3-18. Instructions Supported in JTAG Mode

Instruction

Code

BYPASS

1111

IDCODE

1110

SAMPLE/PRELOAD

0011

EXTEST

0000

SCAN_N

0010

Version

Part number

Manufacturer ID

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Functional Description

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3.22

In-Circuit Emulation

3.22.1 Introduction

EmbeddedICE is an extension to the architecture of the ARM family of processors, and provides the
ability to debug cores that are deeply embedded into systems. It consists of three parts:

1) A set of extensions to the ARM core

2) The EmbeddedICE macrocell, to provide access the extensions from the outside world

3) The EmbeddedICE interface to provide communication from the EmbeddedICE macrocell and

the host computer

The EmbeddedICE macrocell is programmed, in a serial fashion, through the TAP controller on the
ARM via the JTAG interface. The EmbeddedICE macrocell is by default disabled to minimize power
usage, and must be enabled at boot-up to support this functionality.

3.22.2 Functionality

The ICEBreaker module consists of two real-time watchpoint units together with a control and status
register. One or both of the units can be programmed to halt the execution of the instructions by the
ARM processor. Execution is halted when either a match occurs between the values programmed
into the ICEBreaker and the values currently appearing on the address bus, data bus, and the various
control signals. Any bit can be masked to remove it from the comparison. Either unit can be
programmed as a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction
fetches).

Using one of these watchpoint units, an unlimited number of software breakpoints (in RAM) can be
supported by substitution of the actual code.

NOTE: The EXTERN[1:0] signals from the ICEBreaker module are not wired out in this device. This mecha-

nism is used to allow watchpoints to be dependent on an external event. This behavior can be emu-
lated in software via the ICEBreaker control registers.

A more detailed description is available in the ARM Software Development Toolkit User Guide
and Reference Manual. The ICEBreaker module and its registers are fully described in the
ARM7TDMI Datasheet, Chapters 8 and 9.

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Memory Map

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MEMORY MAP

The lower 2 GByte of the address space is allocated to ROM/SRAM/Flash and expansion space. The
0.5 Gbyte of address space from 0xC0000000 to 0xDFFFFFFF is allocated to DRAM. The
remaining 1.5 Gbyte, less 8K for internal registers, is not accessible in the EP7211. The MMU in the
EP7211 should be programmed to generate an abort exception for access to this area.

Internal peripherals are addressed through a set of internal memory locations from hex address
8000.0000 to 8000.3FFF. These are known as the internal registers in the EP7211.

Figure 4-1

shows how the 4-Gbyte address range of the ARM720T processor (as configured within

this chip) is mapped in the EP7211. The memory map shown assumes that two CL-PS6700 PC Card
controllers are connected. If this functionality is not required, then the NCS4 and NCS5 memory is
available as general ROM/SRAM/Flash/Expansion space. The Boot ROM is not fully decoded (i.e.,
the Boot code will repeat within the 256-Mbyte space from 0x70000000 to 0x80000000). The
SRAM is fully decoded up to a maximum size of 128 kbytes. Access to any location above this range
will be wrapped to within the range.

Table 4-1. EP7211 Memory Map

Address

Contents

Size

0xF000.0000

Reserved

256 Mbytes

0xE000.0000

Reserved

256 Mbytes

0xD000.0000

DRAM Bank 1

256 Mbytes

0xC000.0000

DRAM Bank 0

256 Mbytes

0x8000.4000

Unused

~1 Gbyte

0x8000.2000

0x8000.0000

Internal registers (new)

Internal registers (old)

8 kbytes

0x7000.0000

Boot ROM (NCS7)

128 bytes

0x6000.0000

SRAM (NCS6)

37.5 kbytes

0x5000.0000

PCMCIA-1 (NCS5)

4 x 64 Mbytes

0x4000.0000

PCMCIA-0 (NCS4)

4 x 64 Mbytes

0x3000.0000

Expansion (CS3)

256 Mbytes

0x2000.0000

Expansion (CS2)

256 Mbytes

0x1000.0000

ROM Bank 1 (CS1)

256 Mbytes

0x0000.0000

ROM Bank 0 (CS0)

256 Mbytes

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REGISTER DESCRIPTIONS

5.1

Internal Registers

Table 5-1. Internal I/O Memory Locations shows all internal registers in the EP7211, assuming
the CPU is configured for operation with a Little Endian memory system. Table 5-2.Port Byte
Addresses in Big Endian Mode shows the differences that occur for byte-wide access to Ports A,
B, and D with the CPU configured to operate in the Big Endian mode. All the internal registers are
inherently Little Endian (i.e., the least significant byte is attached to bits 7 to 0 of the data bus).
Hence, the system Endianness affects the addresses required for byte accesses to the internal
registers, resulting in a reversal of the byte address required to read/write a particular byte within a
register. Note that the internal registers have been split into two groups the "old" and the "new".
The old ones are the same as that used in CL-PS7111 and are there for compatibility. The new
registers are for accessing the additional functionality of the MCP interface and the LED flasher.

There is no effect on the register addresses for word accesses. Bits A0 and A1 of the internal address
bus are only decoded for Ports A, B, and D (to allow read/write to individual ports). For all other
registers, bits A0 and A1 are not decoded, so that byte reads will return the whole register contents
onto the EP7211's internal bus, from where the appropriate byte (according to the Endianness) will
be read by the CPU. For example, to read data back from the DRAM refresh period register (which
is only 8 bits wide) requires address 0x80000200 if read as a word (irrespective of Endianness), or
as a byte in the Little Endian mode, but a byte read to obtain the register contents in Big Endian mode
must output address 0x80000203. To avoid the additional complexity, it is preferable to perform all
internal register accesses as word operations, except for ports A to D which are explicitly designed
to operate with byte accesses, as well as word accesses.

An 8K segment of memory in the range 0x8000.0000 to 0x8000.3FFF is reserved for internal use in
the EP7211. Accesses in this range will not cause any external bus activity unless debug mode is
enabled. Writes to bits that are not explicitly defined in the internal area are legal and will have no
effect. Reads from bits not explicitly defined in the internal area are legal but will read undefined
values. All the internal addresses should only be accessed as 32-bit words and are always on a word
boundary, except for the PIO port registers, which can be accessed as bytes. Address bits in the range
A0 A5 are not decoded (except for Ports AD), this means each internal register is valid for 64 bytes
(i.e., the SYSFLG1 register appears at locations 0x8000.0140 to 0x8000.017C). There are some gaps
in the register map for backward compatibility reasons, but registers located next to a gap are still
only decoded for 64 bytes.

The GPIO port registers are byte-wide and can be accessed as a word but not as a half-word. These
registers additionally decode A0 and A1. All addresses are in hexadecimal notation.

NOTE: All byte-wide registers should be accessed as words (except Port A to Port D registers, which are

designed to work in both word and byte modes).
All registers bit alignment starts from the LSB of the register (i.e., they are all right shift justified).
The registers which interact with the 32 kHz clock or which could change during readback (e.g., RTC
data registers, SYSFLG register (lower 6-bits only), the TC1 and 2 data registers, port registers, inter-

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rupt status registers) should be read twice and compared to ensure that a stable value has been read
back.

Table 5-1. CL-PS7111-Compatible

Address

Name

Default RD/WR

Size

Comments

0x8000.0000

PADR

Port A data register

0x8000.0001

PBDR

Port B data register

0x8000.0002

Reserved

0x8000.0003

PDDR

Port D data register

0x8000.0040

PADDR

Port A data direction register

0x8000.0041

PBDDR

Port B data direction register

0x8000.0042

Reserved

0x8000.0043

PDDDR

Port D data direction register

0x8000.0080

PEDR

Port E data register

0x8000.00C0

PEDDR

Port E data direction register

0x8000.0100

SYSCON1

System control register 1

0x8000.0140

SYSFLG

System status flags register 1

0x8000.0180

MEMCFG1

Expansion and ROM memory configuration reg-
ister 1

0x8000.01C0

MEMCFG2

Expansion and ROM memory configuration reg-
ister 2

0x8000.0200

DRFPR

DRAM refresh period register

0x8000.0240

INTSR1

Interrupt status register 1

0x8000.0280

INTMR1

Interrupt mask register 1

0x8000.02C0

LCDCON

LCD control register

0x8000.0300

TC1D

Read/Write data to TC1

0x8000.0340

TC2D

Read/Write data to TC2

0x8000.0380

RTCDR

Realtime clock data register

0x8000.03C0

RTCMR

Realtime clock match register

0x8000.0400

PMPCON

PWM pump control register

0x8000.0440

CODR

CODEC data I/O register

0x8000.0480

UARTDR1

8W/11R

UART1 FIFO data register

0x8000.04C0

UBLCR1

UART1 bit rate and line control register

0x8000.0500

SYNCIO

Synchronous serial I/O data register for master
only SSI

0x8000.0540

PALMSW

Least significant 32-bit word of LCD palette reg-
ister

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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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0x8000.0580

PALMSW

Most significant 32-bit word of LCD palette reg-
ister

0x8000.05C0

STFCLR

Write to clear all start up reason flags

0x8000.0600

BLEOI

Write to clear battery low interrupt

0x8000.0640

MCEOI

Write to clear media changed interrupt

0x8000.0680

TEOI

Write to clear tick and watchdog interrupt

0x8000.06C0

TC1EOI

Write to clear TC1 interrupt

0x8000.0700

TC2EOI

Write to clear TC2 interrupt

0x8000.0740

RTCEOI

Write to clear RTC match interrupt

0x8000.0780

UMSEOI

Write to clear UART modem status changed
interrupt

0x8000.07C0

COEOI

Write to clear CODEC sound interrupt

0x8000.0800

HALT

Write to enter the Idle State

0x8000.0840

STDBY

Write to enter the Standby State

0x8000.0880

0x8000.0FFF

Reserved

Write will have no effect, read is undefined

0x8000.1000

FBADDR

LCD frame buffer start address

0x8000.1100

SYSCON2

System control register 2

0x8000.1140

SYSFLG2

System status register 2

0x8000.1240

INTSR2

Interrupt status register 2

0x8000.1280

INTMR2

Interrupt mask register 2

0x8000.12C0

0x8000.147F

Reserved

Write will have no effect, read is undefined

0x8000.1480

UARTDR2

8W/11R

UART2 Data Register

0x8000.14C0

UBLCR2

UART2 bit rate and line control register

0x8000.1500

SS2DR

Master/slave SSI2 data Register

0x8000.1600

SRXEOF

Write to clear RX FIFO overflow flag

0x8000.16C0

SS2POP

Write to pop SSI2 residual byte into RX FIFO

0x8000.1700

KBDEOI

Write to clear keyboard interrupt

0x8000.1800

Reserved

Do not write to this location. A write will cause
the processor to go into an unsupported power
savings state.

0x8000.1840

0x8000.1FFF

Reserved

Write will have no effect, read is undefined

Table 5-1. CL-PS7111-Compatible

(cont.)

Address

Name

Default RD/WR

Size

Comments

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3
JUL 2001

All internal registers in the EP7211 are reset (cleared to zero) by a system reset (i.e., NPOR,
NRESET, or NPWRFL signals becoming active), except for the DRAM refresh period register
(DRFPR), and the realtime clock data register (RTCDR) and match register (RTCMR), which are
only reset by NPOR becoming active. This ensures that the DRAM contents and system time
preserved through a user reset or power fail condition.

Table 5-2. Internal I/O Memory Locations (EP7211 Only)

Address

Name

Default RD/WR

Size

Comments

0x8000.2000

MCCR

MCP Control Register

0x8000.2040

MCDR0

MCP Data Register0

0x8000.2080

MCDR1

MCP Data Register1

0x8000.20C0

MCDR2

MCP Data Register2

0x8000.2100

MCSR

MCP Status Register

0x8000.2200

SYSCON3

System control register 3

0x8000.2240

INTSR3

Interrupt status register 3

0x8000.2280

INTMR3

Interrupt mask register 3

0x8000.22C0

Ledflsh

LED Flash control Register

0x8000.2300

0xBFFF.FFFF

Reserved

This area contains test registers used during
manufacturing test. Writes to this area should
never be attempted during normal operation as
this may cause unexpected behavior. Reads will
be undefined.

Table 5-3. Port Byte Addresses in Big Endian Mode

Address

Name

Default RD/WR

Size

Comments

0x8000.0003

PADR

Port A data register

0x8000.0002

PBDR

Port B data register

0x8000.0001

Reserved

0x8000.0000

PDDR

Port D data register

0x8000.0043

PADDR

Port A data direction register

0x8000.0042

PBDDR

Port B data direction register

0x8000.0041

Reserved

0x8000.0040

PDDDR

Port D data direction register

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

5.1.1

PADR Port A Data Register

ADDRESS: 0x8000.0000

Values written to this 8-bit read/write register will be output on Port A pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
A, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.2

PBDR Port B Data Register

ADDRESS: 0x8000.0001

Values written to this 8-bit read/write register will be output on Port B pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
B, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.3

PDDR Port D Data Register

ADDRESS: 0x8000.0003

Values written to this 8-bit read/write register will be output on Port D pins if the corresponding data
direction bits are set low (port output). Values read from this register reflect the external state of Port
D, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.4

PADDR Port A Data Direction Register

ADDRESS: 0x8000.0040

Bits set in this 8-bit read/write register will select the corresponding pin in Port A to become an
output, clearing a bit sets the pin to input. All bits are cleared by a system reset.

5.1.5

PBDDR Port B Data Direction Register

ADDRESS: 0x8000.0041

Bits set in this 8-bit read/write register will select the corresponding pin in Port B to become an
output, clearing a bit sets the pin to input. All bits are cleared by a system reset.

5.1.6

PDDDR Port D Data Direction Register

ADDRESS: 0x8000.0043

Bits cleared in this 8-bit read/write register will select the corresponding pin in Port D to become an
output, setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output
by default.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

The system control register is a 21-bit read/write register which controls all the general configuration
of the EP7211, as well as modes etc. for peripheral devices. All bits in this register are cleared by a
system reset. The bits in the system control register SYSCON1 are defined below.

Bit

Description

0:3

Keyboard scan: This 4-bit field defines the state of the keyboard column drives. The following table
defines these states.

TC1M: Timer counter 1 mode. Setting this bit sets TC1 to prescale mode, clearing it sets free running
mode.

TC1S: Timer counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz, clearing it sets
the clock source to 2 kHz.

TC2M: Timer counter 2 mode. Setting this bit sets TC2 to prescale mode, clearing it sets free running
mode.

TC2S: Timer counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz, clearing it sets
the clock source to 2 kHz.

UART1EN: Internal UART enable bit. Setting this bit enables the internal UART.

BZTOG: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is selected
(i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ bits for more details.

BZMOD: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin is con-
nected directly to the BZTOG bit. This is the software mode. When BZMOD = 1, the buzzer drive is in the
hardware mode. Two hardware sources are available to drive the pin. They are the TC1 or a fixed inter-
nally generated clock source. The selection of which source is used to drive the pin is determined by the
state of the BUZFREQ bit in the SYSCON2 register. If the TC1 is selected, then the buzzer output pin is
connected to the TC1 under flow bit. The buzzer output pin changes every time the timer wraps around.
The frequency depends on what was programmed into the timer. See the description of the BUZFREQ
and BZTOG bits for more details.

Keyboard Scan

Column

All driven high

All driven low

All high impedance (tristate)

Column 0 only driven high all others high impedance

Column 1 only driven high all others high impedance

Column 2 only driven high all others high impedance

Column 3 only driven high all others high impedance

Column 4 only driven high all others high impedance

Column 5 only driven high all others high impedance

Column 6 only driven high all others high impedance

Column 7 only driven high all others high impedance

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3
JUL 2001

16:17

ADCKSEL: Microwire / SPI peripheral clock speed select. This two bit field selects the frequency of the
ADC sample clock; this is twice the frequency of the synchronous serial ADC interface clock. The table
below shows the available frequencies for operation when in PLL mode. These bits are also used to select
the shift clock frequency for the SSI2 interface when set into master mode. The frequencies obtained in
13.0 MHz mode can be found in Table 3-15. ADC Interface Operation Frequencies.

DBGEN: Setting this bit will enable the debug mode. In this mode, all internal accesses are output as if
they were reads or writes to expansion memory addressed by NCS5. NCS5 will still be active in its stan-
dard address range. In addition the internal interrupt request and fast interrupt request signals to the
ARM720T processor are output on Port E, bits 1 and 2. Note that these bits must be programmed to be
outputs before this functionality can be observed. The clock to the CPU is output on Port E, Bit 0 to enable
individual accesses to be distinguished. For example, in debug mode:

NCS5 = NCS5 or internal I/O strobe

PE0 = CLK

PE1 = NIRQ

PE2 = NFIQ

LCDEN: LCD enable bit. Setting this bit enables the LCD controller.

CDENTX: Codec interface enable TX bit. Setting this bit enables the codec interface for data transmission
to an external codec device.

CDENRX: Codec interface enable RX bit. Setting this bit enables the codec interface for data reception
from an external codec device.
NOTE: Both CDENRX and CDENTX need to be enabled/disabled in TANDEM.

SIREN: HP SIR protocol encoding enable bit. This bit will have no effect if the UART is not enabled.

EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously; it is the
same speed and phase as the CPU clock and will free run all the time the main oscillator is running if this
bit is set. This bit should not be left set all the time for power consumption reasons. If the system enters the
Standby State, the EXPCLK will become undefined. If this bit is clear, EXPCLK will be active during mem-
ory cycles to expansion slots that have external wait state generation enabled only.

WAKEDIS: Setting this bit disables waking up from the Standby State, via the wakeup input.

IRTXM: IrDA TX mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means each zero
bit transmitted is represented as a pulse of width 3/16th of the bit rate period. Setting this bit means each
zero bit is represented as a pulse of width 3/16th of the period of 115,200-bit rate clock (i.e., 1.6

µsw

regardless of the selected bit rate). Setting this bit will use less power, but will probably reduce transmis-
sion distances.

Bit

Description

ADCKSEL

ADC Sample Frequency

(kHz) -- SMPCLK

ADC Clock Frequency

(kHz) -- ADCCLK

128

256

128

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

5.2.2

SYSCON2 System Control Register 2

ADDRESS: 0x8000.1100

This register is an extension of SYSCON1, containing additional control for the EP7211, for
compatibility with CL-PS7111. The bits of this second system control register are defined below.
The SYSCON2 register is reset to all 0s on power up.

SS2RXEN

PC CARD2

PC CARD1

SS2TXEN

KBWEN

DRAMSZ

KBD6

SERSEL

Reserved

BUZFREQ

CLKENSL

OSTB

Reserved

SS2MAEN

UART2EN

Bit

Description

SERSEL:The only affect of this bit is to select either SSI2 or the codec to interface to the external pins.
See the table below for the selection options.
NOTE: If the MCPSEL bit of SYSCON3 is set, then it overrides the state of the SERSEL bit, and thus the
external pins are connected to the MCP interface.

KBD6: The state of this bit determines how many of the Port A inputs are OR'ed together to create the
keyboard interrupt. When zero (the reset state), all eight of the Port A inputs will generate a keyboard inter-
rupt. When set high, only Port A bits 0 to 5 will generate an interrupt from the keyboard. It is assumed that
the keyboard row lines are connected into Port A.

DRAMSZ: Determines width of DRAM memory interface, where:0 = 32-bit DRAM and 1 = 16-bit DRAM.

KBWEN: When the KBWEN bit is high, the EP7211 will get woken from a power saving state into the
Operating State when a high signal is on one of Port A's inputs (irrespective of the state of the interrupt
mask register). This is called the Keyboard Direct Wakeup mode. In this mode, the interrupt request does
not have to get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2) Bit 0 is
low), the processor simply starts re-executing code from where it left off before it entered the power saving
state. If the interrupt is non-masked, then the processor will service the interrupt.

SS2TXEN: Transmit enable for the synchronous serial interface 2. The transmit side of SSI2 will be dis-
abled until this bit is set. When set low, this bit also disables the SSICLK pin (to save power) in master
mode, if receive side is low.

SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will be dis-
abled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2 interface will be in
a power saving state.

SERSEL Value

Selected Serial Device to

External Pins

Master/slave SSI2

Codec

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3
JUL 2001

PC CARD1: Enable for the interface to the CL-PS6700 device for PC Card slot 1. The main effect of this
bit is to reassign the functionality of Port B, Bit 0 to the PRDY input from the
CL-PS6700 devices, and to ensure that any access to the NCS4 address space will be according to the
CL-PS6700 interface protocol.

PC CARD2: Enable for the interface to the CL-PS6700 device for PC Card slot 2. The main effect of this
bit is to reassign the functionality of Port B, Bit 1 to the PRDY input from the
CL-PS6700 devices, and to ensure that any access to the NCS5 address space will be according to the
CL-PS6700 interface protocol.

UART2EN: Internal UART2 enable bit. Setting this bit enables the internal UART2.

SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be configured
for slave mode operation. When high, SSI2 will be configured for master mode operation. This bit also con-
trols the directionality of the interface pins.

OSTB: This bit (operating system timing bit) is for use only with the 13 MHz clock source mode. Normally
it will be set low, however when set high it will cause a 500 kHz clock to be generated for the timers instead
of the 541 kHz which would normally be available. The divider to generate this frequency is not clocked
when this bit is set low.

CLKENSL: CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin. When
high, the RUN signal will be output on RUN/CLKEN.

BUZFREQ: The BUZFREQ bit is used to select which hardware source will be used as the source to drive
the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the on-chip timer (TC1) is
output. When BUZFREQ = 1, a fixed frequency clock is output
(500 Hz when running from the PLL, 528 Hz in the 13 MHz external clock mode). See the BZMOD and the
BZTOG bits for more details.

Bit

Description

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

5.2.3

SYSCON3 System Control Register 3

ADDRESS: 0x8000.2200

This register is an extension of SYSCON1 and SYSCON2, containing additional control for the
EP7211. The bits of this third system control register are defined below.

Reserved

FASTWAKE

VERSN[2]R

eserved

VERSN[1]

Reserved

VERSN[0]

Reserved

ADCCKNSEN

MCPSEL

CLKCTL1

CLKCTL0

ADCCON

Bit

Description

FASTWAKE: When set, the device will wake from the Standby State within one to two cycles of a 4 kHz
clock. This bit is cleared at power up, and thus the device first starts using the default one to two cycles of
the 8 Hz clock.

5:7

VERSN[2:0]: Additional read-only version bits -- will read `000'.

ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the ADC-
CLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the opposite
edges are used.

MCPSEL: When set selects the MCP. This defaults to either the SSI or codec (i.e., MCPSEL bit is low).

ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be used for
ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO(7:0) only is
used for compatibility with the CL-PS7111. When this bit = 1, the ADC Configuration Extension field in the
SYNCIO register is used for ADC Configuration data and the value in the ADC Configuration Byte (SYN-
CIO(6:0)) selects the length of the data (8-bit to 16-bit).

1:2

CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling. The table
below lists the available options.

NOTE: To determine the number of wait states programmed refer to Table 5-4. Values of the Wait State
Field at 13 and 18MHz and Table 5-5. Values of the Wait State Field at 36 MHz. When operating at 13
MHz, the CLKCTL[1:0] bits should not be changed from the default value of `00'. Under no circumstances
should the CLKCTL bits be changed using a buffered write.

CLKCTL(1:0)

Value

Processor

Frequency

ASB and APB

Frequency

Wait State

Scaling

18.432 MHz

36.864 MHz

49.152 MHz

36.864 MHz

73.728 MHz

36.864 MHz

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3
JUL 2001

5.2.4

SYSFLG -- The System Status Flags Register

ADDRESS: 0x8000.0140

The system status flags register is a 32-bit read only register, which indicates various system
information. The bits in the system status flags register SYSFLG are defined in the following table.

7:4

DID

WUON

WUDR

DCDET

MCDR

CLDFLG

PFFLG

RSTFLG

NBFLG

UBUSY1

DCD

DSR

CTS

21:16

UTXFF1

URXFE1

RTCDIV

31:30

VERID

BOOTBIT1

BOOTBIT0

SSIBUSY

CTXFF

CRXFE

Bit

Description

MCDR: Media changed direct read. This bit reflects the INVERTED non-latched status of the media
changed input.

DCDET: This bit will be set if a non-battery operated power supply is powering the system (it is the inverted
state of the NEXTPWR input pin).

WUDR: Wake up direct read. This bit reflects the non-latched state of the wakeup signal.

WUON: This bit will be set if the system has been brought out of the Standby State by a rising edge on the
wakeup signal. It is cleared by a system reset or by writing to the HALT or STDBY locations.

4:7

DID: Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines. The state of
the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last state of these lines
before the LCD controller was enabled. These bits identify the LCD display panel fitted.

CTS: This bit reflects the current status of the clear to send (CTS) modem control input to UART1.

DSR: This bit reflects the current status of the data set ready (DSR) modem control input to UART1.

DCD: This bit reflects the current status of the data carrier detect (DCD) modem control input to UART1.

UBUSY1: UART1 transmitter busy. This bit is set while UART1 is busy transmitting data, it is guaranteed
to remain set until the complete byte has been sent, including all stop bits.

NBFLG: New battery flag. This bit will be set if a low to high transition has occurred on the NBATCHG
input, it is cleared by writing to the STFCLR location.

RSTFLG: Reset flag. This bit will be set if the RESET button has been pressed, forcing the NURESET
input low. It is cleared by writing to the STFCLR location.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the NPWRFL input pin, it is
cleared by writing to the STFCLR location.

CLDFLG: Cold start flag. This bit will be set if the EP7211 has been reset with a power on reset, it is
cleared by writing to the STFCLR location.

16:21

RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last increment of the
RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down to 1 Hz for the RTC.
The MSB is the 32 Hz output, the LSB is the 1 Hz output.

URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding
register is empty. If the FIFO is enabled the URXFE bit will be set when the RX FIFO is empty.

UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding
register is full. If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full.

CRXFE: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty.

CTXFF: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full.

SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in or out of
the synchronous serial interface, when clear data is valid to read.

BOOTBIT01: These bits indicate the default (power-on reset) bus width of the ROM interface. See the
memory configuration register for more details on the ROM interface bus width. The state of these bits
reflect the state of Port E bits 01 during power on reset, as shown in the table below.

ID: Will always read `1' for the EP7211 device.

30:31

VERID: Version ID bits. These 2 bits determine the version id for the EP7211. Will read `10' for the initial
version.

Bit

Description

PE1 (Bootbit1)

PE0 (Bootbit0)

Boot option

32-bit

8-bit

16-bit

Reserved

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3
JUL 2001

5.2.5

SYSFLG2 System Status Register 2

ADDRESS: 0x8000.1140

This register is an extension of SYSFLG1, containing status bits for backward compatibility with
CL-PS7111. The bits of the second system status register are defined below.

Reserved

CKMODE

SS2TXUF

SS2TXFF

SS2RXFE

RESFRM

RESVAL

SS2RXOF

Reserved

UBUSY2

Reserved

21:16

UTXFF2

URXFE2

Reserved

Bit

Description

UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is guaranteed
to remain set until the complete byte has been sent, including all stop bits.

URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding
register contains is empty. If the FIFO is enabled the URXFE bit will be set when the RX FIFO is empty.

UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding
register is full. If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full.

SS2RXFE: Master/slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is empty.

SS2TXUF: Master/slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to transmit when
TX FIFO is empty. This will be cleared when FIFO gets loaded with data.

SS2TXFF: Master/slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This will get
cleared when data is removed from the FIFO or the EP7211 is reset.

SS2RXOF: Master/slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a full RX FIFO
(i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one of two ways:
1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.
2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock
cycle after it is disabled)

RESVAL: Master/slave SSI2 RX FIFO residual byte present, cleared by popping the residual byte into the
SSI2 RX FIFO or by a new RX frame sync pulse.

RESFRM: Master/slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame sync pulse.

CKMODE: This bit reflects the status of the CLKSEL (Port E Bit 2) input, latched during NPOR. When low,
the PLL is running and the chip is operating in 18.43273.728 MHz mode. When high the chip is operating
from an external 13 MHz clock.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

5.3

Interrupt Registers

5.3.1

INTSR1 Interrupt Status Register 1

ADDRESS: 0x8000.0240

The interrupt status register is a 32-bit read only register. The interrupt status register reflects the
current state of the first 16 interrupt sources within the EP7211. Each bit is set if the appropriate
interrupt is active. The interrupt assignment is given below.

EINT3

EINT2

EINT1

CSINT

MCINT

WEINT

BLINT

EXTFIQ

SSEOTI

UMSINT

URXINT1

UTXINT1

TINT

RTCMI

TC2OI

TC1OI

Bit

Description

EXTFIQ: External fast interrupt. This interrupt will be active if the NEXTFIQ input pin is forced low and is
mapped to the FIQ input on the ARM720T processor.

BLINT: Battery low interrupt. This interrupt will be active if no external supply is present (NEXTPWR is
high) and the battery OK input pin BATOK is forced low. This interrupt is de-glitched with a 16 kHz clock,
so it will only generate an interrupt if it is active for longer than
61

µs. It is mapped to the FIQ input on the ARM720T processor and is cleared by writing to the BLEOI

location.
NOTE: BLINT is disabled during the Standby State.

WEINT: Watch dog expired interrupt. This interrupt will become active on a rising edge of the periodic 64
Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not been serviced for a
complete tick period). It is mapped to the FIQ input on the ARM720T processor and the TEOI location
NOTE: WEINT is disabled during the Standby State.

Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.72818.432 MHz modes).

NOTE: Watchdog timer is turned off during the Standby State.

MCINT: Media changed interrupt. This interrupt will be active after a rising edge on the NMEDCHG input
pin has been detected, This input is de-glitched with a 16 kHz clock so it will only generate an interrupt if it
is active for longer than 61

µs. It is mapped to the FIQ input on the ARM7TDMI processor and is cleared

by writing to the MCEOI location. On power-up, the Media change pin (NMEDCHG) is used as an input to
force the processor to either boot from the internal Boot ROM, or from external memory. After power-up,
the pin can be used as a general purpose FIQ interrupt pin.

CSINT: Codec sound interrupt, generated when the data FIFO has reached half full or empty (depending
on the interface direction). It is cleared by writing to the COEOI location.

EINT1: External interrupt input 1. This interrupt will be active if the NEINT1 input is active (low) it is cleared
by returning NEINT1 to the passive (high) state.

EINT2: External interrupt input 2. This interrupt will be active if the NEINT2 input is active (low) it is cleared
by returning NEINT2 to the passive (high) state.

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3
JUL 2001

EINT3: External interrupt input 3. This interrupt will be active if the EINT3 input is active (high) it is cleared
by returning EINT3 to the passive (low) state.

TC1OI: TC1 under flow interrupt. This interrupt becomes active on the next falling edge of the timer
counter 1 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the
TC1EOI location.

TC2OI: TC2 under flow interrupt. This interrupt becomes active on the next falling edge of the timer
counter 2 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the
TC2EOI location.

RTCMI: RTC compare match interrupt. This interrupt becomes active on the next rising edge of the 1 Hz
realtime clock (one second later) after the 32-bit time written to the real time clock match register exactly
matches the current time in the RTC. It is cleared by writing to the RTCEOI location.

TINT: 64 Hz tick interrupt. This interrupt becomes active on every rising edge of the internal
64 Hz clock signal. This 6 4Hz clock is derived from the 15-stage ripple counter that divides the 32.768
kHz oscillator input down to 1 Hz for the realtime clock. This interrupt is cleared by writing to the TEOI
location.
NOTE: TINT is disabled/turned off during the Standby State.

UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt source
depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the
UART1 bit rate and line control register), this interrupt will be active when there is no data in the UART1 TX
data holding register and be cleared by writing to the UART1 data register. If the FIFO is enabled this inter-
rupt will be active when the UART1 TX FIFO is half or more empty, and is cleared by filling the FIFO to at
least half full.

URXINT1: Internal UART1 receive FIFO half full interrupt. The function of this interrupt source depends on
whether the UART1 FIFO is enabled. If the FIFO is disabled this interrupt will be active when there is valid
RX data in the UART1 RX data holding register and be cleared by reading this data. If the FIFO is enabled
this interrupt will be active when the UART1 RX FIFO is half or more full or if the FIFO is non empty and no
more characters have been received for a three character time out period. It is cleared by reading all the
data from the RX FIFO.

UMSINT: Internal UART1 modem status changed interrupt. This interrupt will be active if either of the two
modem status lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI location.

SSEOTI: Synchronous serial interface end of transfer interrupt. This interrupt will be active after a com-
plete data transfer to and from the external ADC has been completed. It is cleared by reading the ADC
data from the SYNCIO register.

Bit

Description

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

5.3.2

INTMR1 Interrupt Mask Register 1

ADDRESS: 0x8000.0280

This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of
the first 16 interrupt sources within the EP7211. The four shaded interrupts all generate a fast
interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual
address 0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will
cause a jump to processor virtual address 0000.00018. Setting the appropriate bit in this register
enables the corresponding interrupt. All bits are cleared by a system reset. Please refer to the INTSR1
register for individual bit details

5.3.3

INTSR2 Interrupt Status Register 2

ADDRESS: 0x8000.1240

This register is an extension of INTSR1, containing status bits for backward compatibility with CL-
PS7111. The interrupt status register also reflects the current state of the new interrupt sources within
the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given
below.

EINT3

EINT2

EINT1

CSINT

MCINT

WEINT

BLINT

EXTFIQ

SSEOTI

UMSINT

URXINT

UTXINT

TINT

RTCMI

TC2OI

TC1OI

Reserved

SS2TX

SS2RX

KBDINT

Reserved

URXINT2

UTXINT2

Reserved

Bit

Description

KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the logical OR of
the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register.
The interrupt request is latched, and can be de-asserted by writing to the KBDEOI location.

NOTE: KBDINT is not deglitched.

SS2RX: Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is generated when
RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX FIFO is emptied or one
SSI2 clock after RX is disabled.

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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

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JUL 2001

5.3.4

INTMR2 Interrupt Mask Register 2

ADDRESS: 0x8000.1280

This register is an extension of INTMR1, containing interrupt mask bits for the backward
compatibility with the CL-PS7111. Please refer to INTSR2 for individual bit details.

5.3.5

INTSR3 Interrupt Status Register 3

ADDRESS: 0x8000.2240

This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of
the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given
below.

SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is generated
when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the FIFO with more
data or disabling the TX. One synchronization clock required when disabling the TX side before it takes
effect.

UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this interrupt source depends on
whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate and
line control register), this interrupt will be active when there is no data in the UART2 TX data holding regis-
ter and be cleared by writing to the UART2 data register. If the FIFO is enabled this interrupt will be active
when the UART2 TX FIFO is half or more empty, and is cleared by filling the FIFO to at least half full.

URXINT2: UART2 receive FIFO half full interrupt. The function of this interrupt source depends on whether
the UART2 FIFO is enabled. If the FIFO is disabled this interrupt will be active when there is valid RX data
in the UART2 RX data holding register and be cleared by reading this data. If the FIFO is enabled this
interrupt will be active when the UART2 RX FIFO is half or more full or if the FIFO is non empty and no
more characters have been received for a three character time out period. It is cleared by reading all the
data from the RX FIFO.

Reserved

Reserved Reserved

SS2TX

SS2RX

KBDINT

Reserved

URXINT2

UTXINT2

Reserved

MCPINT

Bit

Description

MCPINT: MCP interface interrupt. The cause must be determined by reading the MCP status register. It is
mapped to the FIQ interrupt on the ARM720T processor

Bit

Description

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

DS352PP3

JUL 2001

5.3.6

INTMR3 Interrupt Mask Register 3

ADDRESS: 0x8000.2280

This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new
features of the EP7211. Please refer to INTSR3 for individual bit details.

5.4

Memory Configuration Registers

5.4.1

MEMCFG1 Memory Configuration Register 1

ADDRESS: 0x8000.0180

Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (CS6) is
used internally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum
wait state operation. CS7 is used for the on-chip Boot ROM and the configuration field is hardwired
for 8-bit wide, minimum wait state operation. Data written to the configuration fields for either CS6
or CS7 will be ignored. Two of the chip selects (NCS4 and 5) can be used to access two CL-PS6700
PC CARD controller devices, and when either of these interfaces is enabled, the configuration field
for the appropriate chip select in the MEMCFG2 register is ignored. When the PC CARD1 or 2
control bit in the SYSCON2 register is disabled, then NCS4 and NCS5 are active as normal and can
be programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the
six external chip selects are active for 256 Mbytes and the timing and bus transfer width can be
programmed individually. This is accomplished by programming the six byte-width fields contained
in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in these registers are cleared by a
system reset (except for the CS6 and CS7 configurations).

The memory configuration register 1 is a 32-bit read/write register which sets the configuration of
the four expansion and ROM selects NCS0NCS3. Each select is configured with a 1-byte field
starting with expansion select 0.

Reserved

Reserved Reserved

Reserved

MCPINT

31 24

23 16

15 8

7 0

NCS3 configuration

NCS2 configuration

NCS1 configuration

NCS0 configuration

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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Register Descriptions

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5.4.2

MEMCFG2 Memory Configuration Register 2

ADDRESS: 0x8000.01C0

The memory configuration register 2 is a 32-bit read/write register which sets the configuration of
the two expansion and ROM selects NCS4NCS5. Each select is configured with a 1-byte field
starting with expansion select 4.

Each of the six non-reserved byte fields for chip select configuration in the memory configuration
registers are identical and define the number of wait states, the bus width, enable EXPCLK output
during accesses and enable sequential mode access. This byte field is defined below. This
arrangement applies to NCS03, and NCS45 when the PC CARD enable bits in the SYSCON2
register are not set. The state of these bits is ignored for the Boot ROM and local SRAM fields in the
MEMCFG2 register.

Table 5-4.Values of the Bus Width Field defines the bus width field. Note that the effect of this
field is dependent on the two BOOTBIT bits that can be read in the SYSFLG register. All bits in the
memory configuration register are cleared by a system reset and the state of the BOOTBIT bits are
determined by Port E bits 0 and 1 on the EP7211 during power-on reset. The state of PE1 and PE0
determine whether the EP7211 is going to boot from either 32-bit wide, 16-bit wide or 8-bit wide
ROMs.

31 24

23 16

15 8

7 0

(Boot ROM)

(Local SRAM)

NCS5 configuration

NCS4 configuration

5 2

1 0

CLKENB

SQAEN

Wait States Field

Bus width

Table 5-4. Values of the Bus Width Field

Bus Width

Field

BOOTBIT1

BOOTBIT0

Expansion Transfer

Mode

Port E bits 1,0 during

NPOR reset

32-bit wide bus access

Low, Low

16-bit wide bus access

Low, Low

8-bit wide bus access

Low, Low

Reserved

Low, Low

8-bit wide bus access

Low, High

Reserved

Low, High

32-bit wide bus access

Low, High

16-bit wide bus access

Low, High

16-bit wide bus access

High, Low

32-bit wide bus access

High, Low

Reserved

High, Low

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The previous table preserves compatibility with the previous devices, while allowing the previously
unused bit combinations to specify more variations of random and sequential wait states.

See the AC Electrical Specification section for more detail on bus timing.

The memory area decoded by CS6 is reserved for the on-chip SRAM, hence this does not require a
configuration field in MEMCFG2. It is automatically set up for 32-bit wide, no wait state accesses.
For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses.

Chip selects NCS4 and NCS5 are used to select two CL-PS6700 PC CARD controller devices. These
have a multiplexed 16-bit wide address/data interface, and the configuration bytes in the MEMCFG2
register have no meaning when these interfaces are enabled.

5.4.3

DRFPR DRAM Refresh Period Register

ADDRESS: 0x8000.0200

The DRAM refresh period register is an 8-bit read/write register which enables refreshes and selects
the refresh period used by the DRAM controller for its periodic CAS before RAS refresh. The value

Bit

Description

SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a quad
word boundary to take advantage of faster access times from devices that support page mode. The
sequential access will be faulted after four words, (to allow video refresh cycles to occur) even if the
access is part of a longer sequential access. In addition, when this bit is not set, non-sequential accesses
will have a single idle cycle inserted at least every four cycles so that the chip select is de-asserted period-
ically between accesses for easier debug.

CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to
the selected expansion device. This will provide a timing reference for devices that need to extend bus
cycles using the EXPRDY input. Back to back (but not necessarily page mode) accesses will result in a
continuous clock. This bit will only affect EXPCLK when the PLL is being used (i.e., in 73.72818.432MHz
mode). When operating in 13 MHz mode, the EXPCLK pin is an input so cannot be affected by this regis-
ter bit. To save power internally, it should always be set to zero when operating in 13 MHz mode.

6:0

RFSHEN

RFDIV

Table 5-6. Values of the Wait State Field at 36 MHz

(cont.)

Bit 3

Bit 2

Bit 1

Bit 0

Wait States

Random

Wait States

Sequential

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Register Descriptions

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in the DRAM refresh period register is only cleared by a power-on reset (i.e., its state is maintained
during a power fail or user reset).

5.5

Timer/Counter Registers

5.5.1

TC1D Timer Counter 1 Data Register

ADDRESS: 0x8000.0300

The timer counter 1 data register is a 16-bit read/write register which sets and reads data to TC1. Any
value written will be decremented on the next rising edge of the clock.

5.5.2

TC2D Timer Counter 2 Data Register

ADDRESS: 0x8000.0340

The timer counter 2 data register is a 16-bit read/write register which sets and reads data to TC2. Any
value written will be decremented on the next rising edge of the clock.

5.5.3

RTCDR Realtime Clock Data Register

ADDRESS: 0x8000.0380

The real time clock data register is a 32-bit read/write register, which sets and reads the binary time
in the RTC. Any value written will be incremented on the next rising edge of the 1 Hz clock. This
register is reset only by NPOR.

5.5.4

RTCMR Realtime Clock Match Register

ADDRESS: 0x8000.03C0

The Realtime Clock match register is a 32-bit read/write register, which sets and reads the binary
match time to RTC. Any value written will be compared to the current binary time in the RTC, if
they match it will assert the RTCMI interrupt source. This register is reset only by NPOR.

Bit

Description

RFSHEN: DRAM Refresh enable. Setting this bit enables periodic refresh cycles to be generated by the
EP7211 at a rate set by the RFDIV field. Setting this bit also enables self refresh mode when the EP7211
is in the Standby State.

0:6

RFDIV: This 7-bit field sets the DRAM refresh rate. The refresh period is derived from a
128 kHz clock and is given by the formula:
Frequency (kHz) = 128 / (RFDIV + 1)
i.e., RFDIV = (128 / Refresh frequency (kHz)) 1
This equation is valid for both 13 MHz and 18.43273.728 Mhz modes. The equation for frequency gives
the refresh rate for the DRAM.
The maximum refresh frequency is 64 kHz: the minimum is 1 kHz. The RFDIV field should not be pro-
grammed with zero as this will result in no refresh cycles being initiated. These values are valid for both 13
MHz and 18.43273.728 MHz modes of operation.

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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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Register Descriptions

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5.7

PMPCON Pump Control Register

ADDRESS: 0x8000.0400

The Pulse Width Modulator (PWM) pump control register is a 16-bit read/write register which sets
and controls the variable mark space ratio drives for the two PWMs. All bits in this register are
cleared by a system reset. (The top four bits are unused. They should be written as zeroes, and will
read as undefined).

The state of the output drive pins is latched during power on reset, this latched value is used to
determine the polarity of the drive output. The sense of the PWM control lines is summarized in

Table 5-9

External input pins that would normally be connected to the output from comparators monitoring the
PWM output are also used to enable these clocks. These are the FB[0:1] pins. They are read upon
power-up. When FB[0] is high, the PWM is disabled. The same applies to FB[1].

NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs, instead of the

FB pins. The clocks that source the PWMs are disable when the drive ratio fields are zeroed.

11:8

7:4

3:0

Drive 1 pump ratio

Drive 0 from AC source ratio

Drive 0 from battery ratio

Bit

Description

0:3

Drive 0 from battery: This 4-bit field controls the `on' time for the drive0 PWM pump while the system is
powered from batteries. Setting these bits to 0 disables this pump, setting these bits to 1 allows the pump
to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio etc. up to a 15:16 duty ratio. An 8:16 duty ratio results
in a square wave of 96 kHz when operating with an
18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source.

4:7

Drive 0 from AC: This 4-bit field controls the `on' time for the drive0 DC to DC pump while the system is
powered from a non-battery type power source. Setting these bits to 0 disables this pump, setting these
bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc. up to a 15:16 duty
ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz master
clock, or 101.6 kHz when operating from the 13 MHz source.
NOTE: The EP7211 monitors the power supply input pins (i.e., BATOK and NEXTPWR) to determine
which of the above fields to use.

8:11

Drive 1 pump ratio: This 4-bit field controls the `on' time for the drive1 PWM pump. Setting these bits to 0
disables this pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty
ratio, etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating
with an 18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source.

Table 5-9. Sense of PWM control lines

Initial State of Driven During

Power on Reset

Sense of Driven

Polarity of Bias

Voltage

Low

Active high

+ve

High

Active low

-ve

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Register Descriptions

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5.8

CODR -- The CODEC Interface Data Register

ADDRESS: 0x8000.0440

The CODR register is an 8-bit read/write register, to be used with the codec interface when this is
selected by the appropriate setting of Bit 0 (SERSEL) of the SYSCON2 register. Data written to or
read from this register is pushed or popped onto the appropriate 16-byte FIFO buffer. Data from this
buffer is then serialized and sent to or received from the codec sound device. When the codec is
enabled, the codec interrupt CSINT is generated repetitively at 1/8th of the byte transfer rate and the
state of the FIFOs can be read in the system flags register. The net data transfer rate to/from the codec
device is 8 kBps, giving an interrupt rate of 1 kHz.

5.9

UART Registers

5.9.1

UARTDR12 UART12 Data Registers

ADDRESS: 0x8000.0480 and 0x8000.1480

The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the
internal UARTs 1 and 2.

Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is
enabled. If not it is stored in a one byte holding register. This write will initiate transmission from
the UART.

The UART data read registers are made up of the 8-bit data byte received from the UART together
with three bits of error status. Data read from this register is popped from the 16 byte data RX FIFO,
if the FIFO is enabled. If not it is read from a one byte buffer register containing the last byte received
by the UART. Data received and error status is automatically pushed onto the RX FIFO if it is
enabled. The RX FIFO is 10-bits wide by 16 deep.

NOTE: These registers should be accessed as words

7:0

OVERR

PARERR

FRMERR

RX data

Bit

Description

FRMERR: UART framing error. This bit is set if the UART detected a framing error while receiving the
associated data byte. Framing errors are caused by non-matching word lengths or bit rates.

PARERR: UART parity error. This bit is set if the UART detected a parity error while receiving the data
byte.

OVERR: UART over-run error. This bit is set if more data is received by the UART and the FIFO is full. The
overrun error bit is not associated with any single character, and so is not stored in the FIFO, if this bit is
set the entire contents of the FIFO is invalid and should be cleared. This error bit is cleared by reading the
UARTDR register.

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Register Descriptions

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5.9.2

UBRLCR12 UART12 Bit Rate and Line Control Registers

ADDRESS: 0x8000.04C0 and 0x8000.14C0

The bit rate divisor and line control register is a 19-bit read / write register. Writing to these registers
sets the bit rate and mode of operation for the internal UARTs.

31:19

18:17

11:0

WRDLEN

FIFOEN

XSTOP

EVENPRT

PRTEN

BREAK

Bit rate

divisor

Bit

Description

0:11

Bit rate divisor: This 12-bit field sets the bit rate. If the system is operating from the PLL clock, then the bit
rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided internally by 16 to give
the bit rate. The formula to give the divisor value for any bit rate when operating from the PLL clock is: Divi-
sor = (230400/bit rate divisor) 1. A value of zero in this field is illegal when running from the PLL clock.
The tables below show some example bit rates with the corresponding divisor value. In 13 MHz mode, the
clock frequency fed to the UART is 1.8571 MHz. In this mode, zero is a legal divisor value, and will gener-
ate the maximum possible bit rate. The tables below show the bit rates available for both 18.432 MHz and
13 MHz operation.

BREAK: Setting this bit will drive the TX output active (high) to generate a break.

PRTEN: Parity enable bit. Setting this bit enables parity detection and generation

Table 5-10. UART Bit Rates Running

from the PLL Clock

Table 5-11. UART Bit Rates Running

from an External 13.0 MHz Clock

Divisor Value

Bit Rate Running

From the Pll Clock

Divisor

Value

Bit Rate at

13 Mhz

Error on

13 Mhz Value

116071

0.75%

115200

58036

0.75%

76800

38690

0.75%

57600

19345

0.75%

38400

14509

0.75%

19200

9673

0.75%

14400

2418

0.42%

9600

1196

0.28%

2400

1054

110.02

0.18%

191

1200

2094

110

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Register Descriptions

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5.10

LCD Registers

5.10.1 LCDCON -- The LCD Control Register

ADDRESS: 0x8000.02C0

The LCD control register is a 32-bit read/write register that controls the size of the LCD screen and
the operating mode of the LCD controller. Refer to the system description of the LCD controller for
more information on video buffer mapping.

The LCDCON register should only be reprogrammed when LCD controller is disabled.

EVENPRT: Even parity bit. Setting this bit sets parity generation and checking to even parity, clearing it
sets odd parity. This bit has no effect if the PRTEN bit is clear.

XSTOP: Extra stop bit. Setting this bit will cause the UART to transmit two stop bits after each data byte,
clearing it will transmit one stop bit after each data byte.

FIFOEN: Set to enable FIFO buffering of RX and TX data. Clear to disable the FIFO (i.e., set its depth to
one byte).

17:18

WRDLEN: This two bit field selects the word length according to the table below.

29:25

24:19

18:13

12:0

GSMD

GSEN

AC prescale

Pixel prescale

Line length

Video buffer size

Bit

Description

0:12

Video buffer size: The video buffer size field is a 13-bit field that sets the total number of bits x 128 (quad
words) in the video display buffer. This is calculated from the formula:

Video buffer size = (Total bits in video buffer / 128) 1

e.g., for a 640 x 240 LCD and 4-bits per pixel, the size of the video buffer = 640 x 240 x

4 = 614400 bits

Video buffer size field = (614400 / 128) 1 = 4799 or 0x12BF hex.
The minimum value allowed is 3 for this bit field.

Bit

Description

WRDLEN

Word Length

5 bits

6 bits

7 bits

8 bits

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13:18

Line length: The line length field is a 6-bit field that sets the number of pixels in one complete line. This
field is calculated from the formula:

line length = (No. pixels in line / 16) 1

e.g., for 640 x 240 LCD Line length = (640 / 16) 1 = 39 or 0x27 hex.
The minimum value that can be programmed into this register is a 1 (i.e., 0 is not a legal value).

19:24

Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel rate is
always derived from a 36.864 MHz clock and is calculated from the formula:

Pixel rate (MHz) = 36.864 / (Pixel prescale + 1)

When the EP7211 is operating at 13 MHz, pixel rate is given by the formula:

Pixel rate (MHz) = 13 / (Pixel prescale + 1)

The pixel prescale value can be expressed in terms of the LCD size by the formula:
When the EP7211 is operating @ 18.432 MHz:
Pixel prescale = (36864000 / (Refresh Rate *Total pixels in display)) 1
When the EP7211 is operating @ 13 MHz:
Pixel prescale = (13000000 / (Refresh Rate * Total pixels in display)) 1
Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker)
The value should be rounded down to the nearest whole number and zero is illegal and will result in no
pixel clock.
EXAMPLE: For a system being operated in the 18.43273.728 MHz mode, with a 640 x 240
screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals

36.864E6/(70 * 640x240) 1 = 2.428

Rounding 2.428 down to the nearest whole number equals 2.

This gives an actual pixel rate of 36.864E6 / 2+1 = 12.288 MHz

Which gives an actual refresh frequency of 12.288E6/(640x240) = 80 Hz.
NOTE: As the CL2 low pulse time is doubled after every CL1 high pulse this refresh frequency is only an
approximation, the accurate formula is 12.288E6/((640x240)+120) = 79.937 Hz.

25:29

AC prescale: The AC prescale field is a 5-bit number that sets the LCD AC bias frequency. This frequency
is the required AC bias frequency for a given manufacturer's LCD plate. This frequency is derived from the
frequency of the line clock (CL1). The m signal will toggle after n+1 counts of the line clock (CL1) where n
is the number programmed into the AC prescale field. This number must be chosen to match the manufac-
turer's recommendation. This is normally 13, but must not be exactly divisible by the number of lines in the
display.

GSEN: Grey scale enable bit. Setting this bit enables grey scale output to the LCD. When this bit is cleared
each bit in the video map directly corresponds to a pixel in the display.

GSMD: Grey scale mode bit. Clearing this bit sets the controller to 2-bits per pixel (4 grey scales), setting it
sets it to 4 bits per pixel (16 grey scales). This bit has no effect if GSEN is cleared.

Bit

Description

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Register Descriptions

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5.10.2 PALLSW Least Significant Word -- LCD Palette Register

ADDRESS: 0x8000.0580

The least and most significant word LCD palette registers make up a 64-bit read/write register which
maps the logical pixel value to a physical grey scale level. The 64-bit register is made up of 16 x 4-
bit nibbles, each nibble defines the grey scale level associated with the appropriate pixel value. If the
LCD controller is operating in two bits per pixel, only the lower 4 nibbles are valid (D15

D0 in the

least significant word).

5.10.3 PALMSW Most Significant Word -- LCD Palette Register

ADDRESS: 0x8000.0540

See PALLSW description.

The actual physical color and pixel duty ratio for the grey scale values are shown in the table above.
Note that colors 8

15 are the inverse of colors 7

0 respectively. This means that colors 7 and 8 are

identical. The steps in the grey scale are non-linear, but have been chosen to give a close
approximation to perceived linear grey scales. The is due to the eye being more sensitive to changes
in grey level close to 50% grey.

3128

2724

2320

1916

1512

118

74

30

Grey scale

value for pixel

value 7

Grey scale

value for

pixel value 6

Grey scale

value for

pixel value 5

Grey scale

value for

pixel value 4

Grey scale

value for

pixel value 3

Grey scale

value for

pixel value 2

Grey scale

value for

pixel value 1

Grey scale

value for

pixel value 0

3128

2724

2320

1916

1512

118

74

30

Grey scale

value for pixel

value 15

Grey scale

value for

pixel value

Grey scale

value for

pixel value

Grey scale

value for

pixel value

Grey scale

value for

pixel value

Grey scale

value for

pixel value

Grey scale

value for

pixel value 9

Grey scale

value for

pixel value 8

Table 5-12. Grey Scale Value to Color Mapping

Grey Scale Value

Duty Cycle

% Pixels Lit

% Step Change

11.1 %

1/9

11.1 %

8.9 %

1/5

20.0 %

6.7 %

4/15

26.7 %

6.6 %

3/9

33.3 %

6.7 %

2/5

40.0 %

5.4 %

4/9

44.4 %

5.6 %

1/2

50.0 %

0.0 %

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5.10.4 FBADDR LCD Frame Buffer Start Address

ADDRESS: 0x8000.1000

This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer
starts at location 0x0000000 within each chip select memory region. Therefore, the value stored
within the FBADDR register is only the value of the chip select where the frame buffer is located).
On reset, this will be set to 0xC for backward compatibility with the CL-PS7111. Thus the frame
buffer defaults to the start of DRAM Bank 0. The register is 4 bits wide (bits [3:0]). This register
must only be reprogrammed when the LCD is disabled (i.e., setting the LCDEN bit within
SYSCON2 low).

5.11

SSI Register

5.11.1

SYNCIO Synchronous Serial ADC Interface Data Register

ADDRESS: a0x8000.0500

SYNCIO is a 32-bit read/write register. The data written to the SYNCIO register configures the
master only SSI. In default mode, the least significant byte is serialized and transmitted out of the
synchronous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended
mode, a variable number of bits are sent from SYNCIO[31:16] as determined by the ADC
Configuration Length. The transfer clock will automatically be started at the programmed frequency
and a synchronization pulse will be issued. The ADCIN pin is sampled on every positive going clock
edge (or the falling clock edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to
the SYNCIO read register.

During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will
be asserted. In order to clear the interrupt the SYNCIO register must be read. The data read from the
SYNCIO register is the last sixteen bits shifted out of the ADC.

1/2

50.0 %

5.6 %

5/9

55.6 %

5.4 %

3/5

60.0 %

6.7 %

6/9

66.7 %

6.6 %

11/15

73.3 %

6.7 %

4/5

80.0 %

8.9 %

8/9

88.9 %

11.1 %

100 %

Table 5-12. Grey Scale Value to Color Mapping

(cont.)

Grey Scale Value

Duty Cycle

% Pixels Lit

% Step Change

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The length of the data frame can be programmed by writing to the SYNCIO register. This allows
many different ADCs to be accommodated. The device is SPI/Microwire compatible (transfers are
in multiples of 8 bits). However, to be compatible with some non-SPI/Microwire devices, the data
written to the ADC device can be anything between 8 to 16 bits. This is user-definable as defined in
the ADC Configuration Extension section of the SYNCIO register.

In the default mode, the bits in SYNCIO have the following meaning:

Whereas in extended mode, the following applies:

NOTE: The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read

bits (= 33 cycles).

31:15

12:8

7:0

Reserved

TXFRMEN

SMCKEN

Frame length

ADC Configuration Byte

12:7 6:0

Reserved

TXFRMEN

SMCKEN

Frame length

ADC Configuration

Length

ADC Configuration Extension

Bit

Description

0:7 or 0:6

ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is the 8-bit
configuration data to be sent to the ADC. When the ADCCON control bit in the SYSCON3 register = 1, this
field determines the length of the ADC configuration data held in the ADC Configuration Extension field
for sending to the ADC.

8:12 or 7:12

Frame length: The Frame Length Field is the total number of shift clocks required to complete a data
transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit + 16 bits
result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).

SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC clock fre-
quency to be output on the SMPLCK pin.

TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC configura-
tion field will be shifted out to the ADC and depending on the frame length programmed, a number of bits
will be captured from the ADC. If the SYNCIO register is written to with the TXFRMEN bit low, no ADC
transfer will take place, but the Frame length and SMCKEN bits will be affected.

16:31

ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0 this field is
ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the SYSCON3 register = 1,
this field is the configuration data to be sent to the ADC. The ADC Configuration Extension field length is
determined by the value held in the ADC Configuration Length field (SYNCIO[6:0]).

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5.12

STFCLR Clear all `Start Up Reason' flags location

ADDRESS: 0x8000.05C0

A write to this location will clear all the `Start Up Reason' flags in the system flags status register
SYSFLG. The `Start Up Reason' flags should first read to determine the reason why the chip was
started (e.g., a new battery was installed). Any value may be written to this location.

5.13

`End Of Interrupt' Locations

These locations are written to after the appropriate interrupt has been serviced. The write is
performed to clear the interrupt status bit, so that other interrupts can be serviced. Any value may be
written to these locations.

5.13.1 BLEOI Battery Low End of Interrupt

ADDRESS: 0x8000.0600

A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK
with NEXTPWR high).

5.13.2 MCEOI Media Changed End of Interrupt

ADDRESS: 0x8000.0640

A write to this location will clear the interrupt generated by a falling edge of the NMEDCHG input
pin.

5.13.3 TEOI Tick End of Interrupt Location

ADDRESS: 0x8000.0680

A write to this location will clear the current pending tick interrupt and watch dog interrupt.

5.13.4 TC1EOI TC1 End of Interrupt Location

ADDRESS: 0x8000.06C0

A write to this location will clear the under flow interrupt generated by TC1.

5.13.5 TC2EOI TC2 End of Interrupt Location

ADDRESS: 0x8000.0700

A write to this location will clear the under flow interrupt generated by TC2.

5.13.6 RTCEOI RTC Match End of Interrupt

ADDRESS: 0x8000.0740

A write to this location will clear the RTC match interrupt

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5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt

ADDRESS: 0x8000.0780

A write to this location will clear the modem status changed interrupt.

5.13.8 COEOI Codec End of Interrupt Location

ADDRESS: 0x8000.07C0

A write to this location clears the sound interrupt (CSINT).

5.13.9 KBDEOI Keyboard End of Interrupt Location

ADDRESS: 0x8000.1700

A write to this location clears the KBDINT keyboard interrupt.

5.13.10 SRXEOF End of Interrupt Location

ADDRESS: 0x8000.1600

A write to this location clears the SSI2 RX FIFO overflow status bit.

5.14

State Control Registers

5.14.1 STDBY Enter the Standby State Location

ADDRESS: 0x8000.0840

A write to this location will put the system into the Standby State by halting the main oscillator. It
will automatically switch the DRAMs into self refresh if the RFSHEN bit is set in the DRAM refresh
period register. All transitions to the Standby State are synchronized with DRAM cycles. A write to
this location while there is an active interrupt will have no effect.

NOTE: The following restrictions apply when operating with a self-refresh DRAM

Before entering the Standby State, the LCD Controller should be disabled. The LCD controller should be
enabled on exit from the Standby State.

After exiting from the Standby State, the first instruction that gets executed must be fetched from non-

DRAM.

NOTE: If the EP7211 is attempting to get into the Standby State when there is a pending interrupt request, it

will not enter into the low power mode. The instruction will get executed, but the processor will ignore
the command.

5.14.2 HALT Enter the Idle State Location

ADDRESS: 0x8000.0800

A write to this location will put the system into the Idle State by halting the clock to the processor
until an interrupt is generated. A write to this location while there is an active interrupt will have no
effect.

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5.15

SS2 Registers

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register

ADDRESS: 0x8000.1500

This is the 16-bit wide data register for the full-duplex master/slave SSI2 synchronous serial
interface. Writing data to this register will initiate a transfer. Writes need to be word writes and the
bottom 16 bits are transferred to the TX FIFO. Reads will be 32 bits as well; the low 16 bits contain
RX data and the upper 16-bits should be ignored. Although the interface is byte-oriented, data is
written in two bytes at a time to allow higher bandwidth transfer. It is up to the software to assemble
the bytes for the data stream in an appropriate manner.

All reads/writes to this register must be word reads/writes.

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte

ADDRESS: 0x8000.16C0

This is a write-only location which will cause the contents of the RX shift register to be popped into
the RX FIFO, thus enabling a residual byte to be read. The data value written to this register is
ignored. This location should be used in conjunction with the RESVAL and RESFRM bits in the
SYSFLG2 register.

5.16

MCP Register Definitions

There are five registers within the MCP, one control register, three data registers, and one status
register. The control register is used to program the audio and telecom sample rates, to mask or
unmask interrupt requests to service the MCP's FIFOs, and to select whether an on-chip or off-chip
clock is used to drive the bit rate, and to enable/disable operation. The first data register addresses
the top of the audio transmit FIFO and the bottom of the audio receive FIFO. Likewise, the second
data register addresses the top/bottom of the telecom transmit/receive FIFOs, respectively. A read
accesses the receive FIFOs, and a write the transmit FIFOs. Note that these are four physically
separate FIFOs to allow full-duplex transmission. The third data register is 21 bits and is used to
transmit read and write operations to the codec's control, data, and status registers. Values written to
the register are used in the transmit data frame, and values read are taken from the received data
frame. The status register contains bits which signal FIFO overrun and underrun errors and transmit
and receive FIFO service requests. Each of these status conditions signal an interrupt request to the
interrupt controller. The status register also flags when audio and telecom transmit FIFOs are not full,
when the audio and telecom receive FIFOs are not empty, when a codec control register read or write
is complete, and when the audio or telecom portion of the codec is enabled (no interrupt generated).

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5.16.1 MCP Control Register

ADDRESS: 0x8000.2000

The MCP control register (MCCR) contains ten different bit fields that control various functions
within the MCP.

5.16.1.1

Audio Sample Rate Divisor (ASD)

The 7-bit audio sample rate divisor (ASD) bit field is used to synchronize the MCP with the sample
rate of the audio codec. Sample rate synchronization is required such that the MCP's audio transmit
FIFO logic knows when to load a new value for D/A conversion to the MCP's serial shifter for
transmission. This field is programmed with the same value that is written to the codec's sample rate
divisor via a codec control register write. When the audio codec is enabled, the first audio transmit
value is placed in the serial output stream by the transmit FIFO, and both the MCP's and codec's
sample rate counters begin to decrement in lock-step with one another. When the audio codec's
counter decrements to zero, it uses the value transmitted to it by the MCP to perform the D/A
conversion. After the conversion is made, the MCP and codec's counters reset to their modulus
value, and the MCP's audio transmit FIFO loads the next value to the MCP's serial shifter for
transmission. This new value is then transmitted to the audio codec and is used for the next D/A
conversion, which is signaled when the sample rate counter decrements to zero again.

In principle, a total of 122 different audio sample rates can be selected, ranging from a minimum of
2.953 K samples per second to a maximum of 62.5 K samples per second (for a range of ASD values
between 6 (00000110) and 127 (11111111)). The sample rate clock generator uses the 9.216 MHz
(6.5 MHz for 13MHz mode) MCP clock, generated from a division of the chip's clock by 4, which
in turn is divided by a fixed value of 32 and then the programmable ASD value to generate the audio
sample clock, inside the CODEC.

For instance, for the Philips UCB1100 the sampling clock is automatically enabled when:

A codec control register write to the audio control register B is made (address='1000') which sets
either the audio codec input or output enable bits (Bit 14 = aud_in_ena, Bit 15 = aud_out_ena) of this
register, followed by the rising edge of the next SIBSYNC pulse, after the write has been made

Once enabled, the MCP's audio sample rate counter decrements at the programmed frequency with
a 50% duty cycle. The particular, the codec control register write outlined above causes the MCP's
audio transmit FIFO logic to transfer the next available value to the audio data field within the serial
shifter. Each time the audio sample rate counter decrements to zero, it is reloaded with its
programmed ASD modulus value, triggers the audio transmit FIFO logic to transfer the next
available value to the audio data field within the serial shifter, and continues to decrement.

Again, taking the example of the UCB1100 codec, the MCP's audio sample rate clock is
automatically disabled when: a codec control register write to the codec audio control register B is
made (address='1000') which clears both the audio codec input and output enable bits (bit 14 =
aud_in_ena, bit 15 = aud_out_ena), followed by the rising edge of the next SIBSYNC pulse after the
write has been made. The resulting audio sample clock rate, given a specific ASD value can be

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calculated using the equation below, where ASD is the decimal equivalent of the binary value
programmed within the bit-field. Note that ASD must be programmed with a value of 6 or larger.

Unpredictable results occur for ASD values smaller than 6. As mentioned elsewhere, the sample
frequency is derived from the equation:

Sample Rate = (MCP's serial clock frequency) / (32 x ASD)

Using the MCP clock of 9.216 MHz, and an ASD value of 13, a nominal audio codec sample
frequency of 22.05 kHz is achieved within an error of

±0.5%. Although the existing MCP design

includes a provisional input from an external clock and it can be programmed to accept an external
clock, this feature is not enabled in the EP7211.

5.16.1.2

Telecom Sample Rate Divisor (TSD)

The 7-bit telecom sample rate divisor (TSD) bit field is used to synchronize the MCP with the sample
rate of the telecom codec. The telecom sample rate clock is required for the same reason and works
exactly like the audio sample rate clock, except for one minor difference. The valid TSD values range
from 16 to 127 (instead of 6), allowing a total of 112 different audio sample rates to be selected,
ranging from a minimum of 2.953 K samples per second to a maximum of 23.44 K samples per
second.

The resulting telecom sample clock rate, given a specific TSD value can be calculated using the
equation below, where TSD is the decimal equivalent of the binary value programmed within the bit-
field. Although (e.g., in the UCB1100 Philips telecom codec), the telecom divisor can be
programmed with values in the range 6

-127, note that TSD must be programmed with a value of 16

or larger. Unpredictable results occur for TSD values smaller than 16. As mentioned elsewhere, the
sample frequency is derived from the equation:

Sample Rate = (MCP's serial clock frequency) / (32 x TSD)

Using a TSD modulus of 40 and the MCP's serial clock at 9.216 MHz, the exact nominal Telecom
Sample Frequency of 7.2 kHz is achieved.

5.16.1.3

Multimedia Communications Port Enable (MCE)

The MCP enable (MCE) bit is used to enable and disable all MCP operation.

When the MCP is disabled, all of its clocks are powered down to minimize power consumption. Note
that MCE is the only control bit within the MCP that is reset to a known state. It is cleared to zero to
ensure the MCP is disabled following a reset of the device.

When the MCP is enabled, SCLK begins to transition and the start of the first frame is signaled by
driving the SIBSYNC pin high for one SCLK period. The rising-edge of SIBSYNC coincides with
the rising-edge of SCLK. As long as the MCE bit is set, the MCP operates continuously, transmitting
and receiving 128 bit data frames. When the MCE bit is cleared, the MCP is disabled immediately,
causing the current frame which is being transmitted to be terminated. Clearing MCE resets the
MCP's FIFOs. However MCP data register 3, the control and the status registers are not reset. The
user must ensure these registers are properly reconfigured before re-enabling the MCP.

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5.16.1.4

A/D Sampling Mode (ADM)

The A/D sampling mode (ADM) bit selects whether the MCP takes audio and telecom data from the
incoming frame only when their respective data valid bits are set or whenever the MCP's audio and
telecom sample rate counters time-out, indicating that the data in the next incoming frame is valid.
When ADM = 0, data is taken from the incoming frame and is placed into the audio or telecom FIFO
whenever the incoming audio or telecom data valid bit is set. When ADM = 1, after the MCP is
enabled, data is taken from the incoming frame when the data valid bit is set for the first time. After
this point, the data valid bit is ignored, and samples are stored each time the audio or telecom sample
rate counters decrement to zero. This indicates that a new A/D sample was taken and will be available
in the next frame.

The UCB1100 has two different modes of operation to control the setting of the audio and telecom
data valid bits. In one mode, the codec only sets the data valid bit when a new A/D sample is
contained within the incoming data frame. Once the data is transmitted to the MCP within a receive
data frame, the data valid bit is reset to zero for subsequent data frames until a new A/D sample is
triggered and transmitted to the MCP. In this mode, the user should program ADM = 0. In the other
mode, the data valid bit is set once when the first A/D conversion is made and is placed in the receive
data frame. However, the data valid bit remains set and the MCP cannot determine when samples are
available within the incoming frame. Programming ADM = 1 prevents multiple copies of the sample
to be placed in the FIFO, only storing samples when the sample rate counter times-out.

5.16.1.5

MCP Interrupt Generation

The MCP can generate four maskable interrupts and four non-maskable interrupts, as described in
the sections below. Only one interrupt line is wired into the interrupt controller for the whole MCP.
This interrupt is the wired OR of all eight interrupts (after masking where appropriate). The software
servicing the interrupts must read the status register in the MCP to determine which source(s) caused
the interrupt. It is possible to prevent any MCP sources causing an interrupt by masking the MCP
interrupt in the interrupt controller register.

5.16.1.6

Telecom Transmit FIFO Interrupt Mask (TTM)

The telecom transmit FIFO interrupt mask (TTM) bit is used to mask or enable the telecom transmit
FIFO service request interrupt. When TTM = 0, the interrupt is masked and the state of the telecom
transmit FIFO service request (TTS) bit within the MCP status register is ignored by the interrupt
controller. When TTM = 1, the interrupt is enabled and whenever TTS is set (one) an interrupt
request is made to the interrupt controller. Note that programming TTM = 0 does not affect the
current state of TTS or the telecom transmit FIFO logic's ability to set and clear TTS; it only blocks
the generation of the interrupt request.

5.16.1.7

Telecom Receive FIFO Interrupt Mask (TRM)

The telecom receive FIFO interrupt mask (TRM) bit is used to mask or enable the telecom receive
FIFO service request interrupt. When TRM = 0, the interrupt is masked and the state of the telecom
receive FIFO service request (TRS) bit within the MCP status register is ignored by the interrupt

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controller. When TRM = 1, the interrupt is enabled and whenever TRS is set (one) an interrupt
request is made to the interrupt controller. Note that programming TRM = 0 does not affect the
current state of TRS or the telecom receive FIFO logic's ability to set and clear TRS, it only blocks
the generation of the interrupt request.

5.16.1.8

Audio Transmit FIFO Interrupt Mask (ATM)

The audio transmit FIFO interrupt mask (ATM) bit is used to mask or enable the audio transmit FIFO
service request interrupt. When ATM = 0, the interrupt is masked and the state of the audio transmit
FIFO service request (ATS) bit within the MCP status register is ignored by the interrupt controller.
When ATM = 1, the interrupt is enabled and whenever ATS is set (one) an interrupt request is made
to the interrupt controller. Note that programming ATM = 0 does not affect the current state of ATS
or the audio transmit FIFO logic's ability to set and clear ATS; it only blocks the generation of the
interrupt request.

5.16.1.9

Audio Receive FIFO Interrupt Mask (ARM)

The audio receive FIFO interrupt mask (ARM) bit is used to mask or enable the audio receive FIFO
service request interrupt. When ARM = 0, the interrupt is masked and the state of the audio receive
FIFO service request (ARS) bit within the MCP status register is ignored by the interrupt controller.
When ARM = 1, the interrupt is enabled and whenever ARS is set (one) an interrupt request is made
to the interrupt controller. Note that programming ARM = 0 does not affect the current state of ARS
or the audio receive FIFO logic's ability to set and clear ARS; it only blocks the generation of the
interrupt request.

5.16.1.10 Loop Back Mode (LBM)

The loop back mode (LBM) bit is used to enable and disable the ability of the MCP's transmit and
receive logic to communicate. When LBM = 0, the MCP operates normally. The transmit and receive
data paths are independent and communicate via their respective pins. When LBM = 1, the output of
the serial shifter (MSB) is directly connected to the input of the serial shifter (LSB) internally and
control of the SIBDOUT, SIBDIN, SIBCLK, and SIBSYNC pins are given to the peripheral pin
control (PPC) unit.

The following figure shows the bit locations corresponding to the ten different control bit fields
within the MCP control register. Note that the MCE bit is the only control bit which is reset to a
known state to ensure the MCP is disabled following a reset of the device. The reset state of all other
control bits is unknown and must be initialized before enabling the MCP. Writes to reserved bits are
ignored and reads return zeros.

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Address: 0x 8000 2000

MCP Control Register: MCCR

Read/Write

Bit

Reserved

LBM

ARM

ATM

TRM

TTM

ADM

ECS

MCE

Reset

Bit

Res.

TSD

Res.

ASD

Reset

Table 5-13. MCP Control Register

Bit

Name

Description

ASD

Audio Sample Rate Divisor
Value (from 6 to 127) used to match the sample rate of the audio codec within the UCB1100 to time
when audio D/A data should be supplied by the audio transmit FIFO.
Sample Rate = (MCP Serial Clock Frequency) /(32 x ASD)

Reserved

148

TSD

Telecom Sample Rate Divisor
Value (from 16 to 127) used to match the sample rate of the telecom codec within the UCB1100 to time
when telecom D/A data should be supplied by the telecom transmit FIFO.
Sample Rate = (MCP Serial Clock Frequency) /(32 x TSD)

Reserved

MCE

Multimedia Communications Port Enable
0 -- MCP operation disabled, control of the SIBDIN, SIBDOUT, SIBCLK, and SIBSYNC pins given to
the SSI2/codec/MCP pin mulitiplexing logic to assign I/O pins 60-64 to another block.
1 -- MCP operation enabled
Note that by default, the SSI/CODEC have precedence over the MCP in regard to the use of the I/O
pins. Nevertheless, when Bit 3 (MCPSEL) of register SYSCON3 is set to 1, then the above mentioned
MCP ports are connected to I/O pins 6064.

Reserved (Always write to zero.)

ADM

A/D Data Sampling Mode
0 -- Audio and telecom receive data is stored to their respective FIFOs whenever their receive data
valid bits are valid.
1 -- Audio and telecom receive data is stored when the receive data valid bit is set the first time, and
from that point on whenever the MCP's audio and telecom sample rate counters time-out.

TTM

Telecom Transmit FIFO Interrupt Mask
0 -- Telecom transmit FIFO half-full or less condition does not generate an interrupt (TTS bit ignored).
1 -- Telecom transmit FIFO half-full or less condition generates an interrupt (state of TTS sent to inter-
rupt controller).

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5.16.2 MCP Data Registers

The MCP contains three data registers: MCDR0 addresses the top entry of the audio transmit FIFO
and bottom entry of the audio receive FIFO; MCDR1 addresses the top and bottom entry of the
telecom transmit and receive FIFOs, respectively; and MCDR2 is used to perform reads and writes
to any of the codec's sixteen registers via the MCP's serial interface.

5.16.2.1

MCP Data Register 0

ADDRESS: 0x8000.2040

When MPC Data Register 0 (MCDR0) is read, the bottom entry of the audio receive FIFO is
accessed. As data is removed by the MCP's receive logic from the incoming data frame, it is placed
into the top entry of the audio receive FIFO and is transferred down an entry at a time until it reaches
the last empty location within the FIFO. Data is removed by reading MCDR0, which accesses the
bottom entry of the audio FIFO. After MCDR0 is read, the bottom entry is invalidated, and all
remaining values within the FIFO automatically transfer down one location.

When MCDR0 is written, the top-most entry of the audio transmit FIFO is accessed. After a write,
data is automatically transferred down to the lowest location within the transmit FIFO which does
not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by
the transmit logic, is loaded into the correct position within the 64-bit transmit serial shifter, then
serially shifted out onto the SIBDOUT pin during subframe 0.

Audio data is 12-bits wide and must be left justified by the user before writing them to the transmit
FIFO (MSB of audio data corresponds to bit 16 of transmit FIFO). The lower four bits of the FIFO
which are aligned within the 16-bit value are also written to MCDR0 for transmission. Nevertheless,

TRM

Telecom Receive FIFO Interrupt Mask
0 -- Telecom receive FIFO half-full or more condition does not generate an interrupt (TRS bit ignored).
1 -- Telecom receive FIFO half-full or more condition generates an interrupt (state of TRS sent to inter-
rupt controller).

ATM

Audio Transmit FIFO Interrupt Mask
0 -- Audio transmit FIFO half-full or less condition does not generate an interrupt (ATS bit ignored).
1 -- Audio transmit FIFO half-full or less condition generates an interrupt (state of ATS sent to interrupt
controller).

ARM

Audio Receive FIFO Interrupt Mask
0 -- Audio receive FIFO half-full or more condition does not generate an interrupt (ARS bit ignored).
1 -- Audio receive FIFO half-full or more condition generates an interrupt (state of ARS sent to inter-
rupt controller).

LBM

Loop Back Mode
0 -- Normal serial port operation enabled
1 -- Output of serial shifter is connected to input of serial shifter internally and control of SIBDIN, SIBD-
OUT, SCLK, and SIBSYNC pins is given to the PPC unit.

3124

Reserved

Table 5-13. MCP Control Register

(cont.)

Bit

Name

Description

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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

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Register Descriptions

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JUL 2001

5.16.2.2

MCP Data Register 1

ADDRESS: 0x8000.2080

When MPC Data Register 1 (MCDR1) is read, the bottom entry of the telecom receive FIFO is
accessed. As data is removed by the MCP's receive logic from the incoming data frame, it is placed
into the top entry of the telecom receive FIFO and is transferred down an entry at a time until it
reaches the last empty location within the FIFO. Data is removed by reading MCDR1, which
accesses the bottom entry of the telecom FIFO. After MCDR1 is read, the bottom entry is
invalidated, and all remaining values within the FIFO automatically transfer down one location.

When MCDR1 is written, the top-most entry of the telecom transmit FIFO is accessed. After a write,
data is automatically transferred down to the lowest location within the transmit FIFO which does
not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by
the transmit logic. It is then loaded into the correct position within the 64-bit transmit serial shifter
then serially shifted out onto the SIBDOUT pin during subframe 0.

Telecom data is 14-bits wide and must be left justified by the user before writing them to the transmit
FIFO (MSB of telecom data corresponds to bit 16 of transmit FIFO). The lower two bits of the FIFO
which are aligned within the 16-bit value are also written to MCDR1 for transmission. The UCB1100
automatically forces bits 0 and 1 to zero before transmitting the value to the MCP. The user must
right justify received telecom data before using it.

Table 5-14. MCP Data Register 0

Bit

Name

Description

Reserved for future enhancements
Read -- Data returned, but UCB1100 currently zero fills these four bits
Write -- MCP's transmit logic sends these bits, even though they are ignored by the UCB1100

154

Audio

Data

Transmit/Receive Audio FIFO Data
Read -- Bottom of Audio Receive FIFO data
Write -- Top of Audio Transmit FIFO data

3116

Reserved

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123

Register Descriptions

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JUL 2001

The following figure shows MCDR1. Note that the transmit and receive telecom FIFOs are cleared
when the device is reset, or by writing a zero to MCE (MCP disabled). Also, note that writes to
reserved bits are ignored and reads return zeros.

Figure 5-2. MCP Data Register 1: MCDR1

Address: 0x 8000 200C

MCP Data Register 1: MCDR1

Read/Write

Bit

Reserved

Reset

Bit

Bottom of Telecom Receive FIFO

Reset

Read Access

Bit

Reserved

Reset

Bit

Top of Telecom Transmit FIFO

Reset

Write Access

Table 5-15. MCP Data Register 1

Bit

Name

Description

Reserved for future enhancements
Read -- Data returned, but UCB1100 currently zero fills these two bits
Write -- MCP's transmit logic sends these bits, even though they are ignored by the UCB1100

152

Telecom

Data

Transmit/Receive Telecom FIFO Data
Read -- Bottom of Telecom Receive FIFO data
Write -- Top of Telecom Transmit FIFO data

3116

Reserved

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Register Descriptions

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JUL 2001

5.16.2.3

MCP Data Register 2

ADDRESS: 0x8000.20C0

MCDR2 contains 21 bits and is used to perform reads and writes to any of the UCB1100's sixteen
registers. MCDR2 contains three separate fields: MCDR2[15:0] is the 16-bit register data field,
MCDR2[16] is a 1-bit read/write control bit, and MCDR2[20:17] is the 4-bit register address field.
A value written to MCDR2 is placed in the correct position within the 64-bit subframe 0, is
transmitted to the off-chip codec, and is used to perform a read or write operation to the addressed
codec register. Note that the contents of the addressed register are always returned in the receive data
frame and placed in the MCDR2 registers regardless of the state of the read/write bit. Thus, for write
cycles, both a write and a read occurs, and for read cycles, only a read occurs. When MCDR2 is read,
the value returned from the last read or write operation which was completed to the codec is returned.

A register write is performed by writing the correct value to each of the three fields within MCDR2
using one 16- or 32-bit write, ensuring that the read/write bit is set. Its contents are then transferred
to the correct fields within the serial shifter on the next rising-edge of the SIBSYNC signal, and then
to the codec via the SIBDOUT pin during subframe 0. The value within MCDR2[15:0] is written to
the selected codec register at the end of subframe 0 (during the 65th bit of the frame). The data
written to the control register and its address are returned to the MCP during the next data frame, and
are placed back within MCDR2, with the read/write bit reset to zero. For a write operation, since the
addressed register is written at the end of subframe 0, the data returned during the frame in which the
write occurred represents the previous contents of the register. The updated value is returned during
the next data frame.

A register read is performed by writing the address of the register to read while clearing the
read/write bit to zero within MCDR2. Again, the data is transferred to the serial shifter on the next
rising-edge of the SIBSYNC signal and is transmitted to the UCB1100 during subframe 0. Because
the address and read/write control bit fields are placed near the beginning of the serial stream output,
the codec performs the read immediately after the read/write bit is received (during the 41st bit of
the frame) and the value contained within the addressed register is sent back to the MCP in the same
data frame, and is placed within MCDR2.

Once MCDR2 is written with a value to execute a read or write, the operation is performed every
MCP data frame until a new value is written to the register. Thus continuous reads or writes are made
to the addressed codec register until a new read or write operation is configured.

The following figure shows the location of MCP data register 2. Note that the reset state of all
MCDR2 bits is unknown, writes to reserved bits are ignored and reads return zeros.

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Register Descriptions

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Figure 5-3. MCP Data Register 2: MCDR2

Address: 0x 8000 2010

MCP Data Register 2: MCDR2

Read/Write

Bit

Reserved

Erg Address R/W

Reset

Bit

Data Value Returned by a Codec Register Read or Write

Reset

Read Access

Bit

Reserved

Erg Address R/W

R/W

Reset

Bit

Data Value to be Written to the Addressed Codec Register

Reset

Write Access

Table 5-16. MCP Data Register 2

Bit

Name

Description

150

Codec Register
Read/Write Data

Codec Register Read/Write Data
Read -- If a codec write was last performed, contains data of previous register access, next
frame contains the data which was written. If a codec read was last performed, contains data
from the read register
Write -- Used to specify what data to write to the addressed register, ignored for a codec
register read

R/W

Read/Write
Read -- Returns a zero
Write -- Used to control whether the addressed register is read or written
(write = 1, read = 0)

2017

Codec Register
Read/Write
Address

Codec Register Read/Write Address
Read -- If a codec write was last performed, contains address of previous register access,
next frame contains the address of the write. If a codec read was last performed, contains
address of the register read
Write -- Used to address a register to perform a read or write

3121

Reserved

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Register Descriptions

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5.16.3 MCP Status Register

ADDRESS: 0x8000.2100

The MCP Status Register (MCSR) contains bits which signal FIFO overrun and underrun errors and
FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.
The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not
empty, when a codec control register read or write is complete, and when the audio or telecom
portion of the codec is enabled (no interrupt generated).

Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags.
Status bits are referred to as "sticky" (once set by hardware, they must be cleared by software).
Writing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set and
cleared by hardware, and writes have no effect. Additionally some bits which cause interrupts have
corresponding mask bits in the control register and are indicated in the section headings below. Note
that the user has the ability to mask all MCP interrupts by clearing the MCP bit within the interrupt
controller mask register INTMR3.

5.16.3.1

Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)

The audio transmit FIFO service request flag (ATS) is a read-only bit which is set when the audio
transmit FIFO is nearly empty and requires service to prevent an underrun. ATS is set any time the
audio transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it
has five or more entries of valid data. When the ATS bit is set, an interrupt request is made unless
the audio transmit FIFO interrupt request mask (ATM) bit is cleared. After the CPU fills the FIFO
such that four or more locations are filled within the audio transmit FIFO, the ATS flag (and the
service request and/or interrupt) is automatically cleared.

5.16.3.2

Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt)

The audio receive FIFO service request flag (ARS) is a read-only bit which is set when the audio
receive FIFO is nearly filled and requires service to prevent an overrun. ARS is set any time the audio
receive FIFO has six or more entries of valid data (half full or more), and cleared when it has five or
fewer (less than half full) entries of data. When the ARS bit is set, an interrupt request is made unless
the audio receive FIFO interrupt request mask (ARM) bit is cleared. After six or more entries are
removed from the receive FIFO, the TRS flag (and the service request and/or interrupt) is
automatically cleared.

5.16.3.3

Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable
interrupt)

The telecom transmit FIFO service request flag (TTS) is a read-only bit which is set when the
telecom transmit FIFO is nearly empty and requires service to prevent an underrun. TTS is set any
time the telecom transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared
when it has five or more entries of valid data. When the TTS bit is set, an interrupt request is made
unless the telecom transmit FIFO interrupt request mask (TTM) bit is cleared. After the CPU fills the

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Register Descriptions

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FIFO such that four or more locations are filled within the telecom transmit FIFO, the TTS flag (and
the service request and/or interrupt) is automatically cleared.

5.16.3.4

Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable
interrupt)

The telecom receive FIFO service request flag (TRS) is a read-only bit which is set when the telecom
receive FIFO is nearly filled and requires service to prevent an overrun. TRS is set any time the
telecom receive FIFO has six or more entries of valid data (half full or more), and cleared when it
has five or fewer (less than half full) entries of data. When the TRS bit is set, an interrupt request is
made unless the telecom receive FIFO interrupt request mask (TRM) bit is cleared. After six or more
entries are removed from the receive FIFO, the TRS flag (and the service request and/or interrupt) is
automatically cleared.

5.16.3.5

Audio Transmit FIFO Underrun Status (ATU) (read/write, non-maskable interrupt)

The audio transmit FIFO underrun status bit (ATU) is set when the audio transmit logic attempts to
fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the audio
transmit logic continuously transmits the last valid audio value which was transmitted before the
underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the audio
transmit logic uses the new value within the FIFO for transmission. When the ATU bit is set, an
interrupt request is made.

5.16.3.6

Audio Receive FIFO Overrun Status (ARO) (read/write, non-maskable interrupt)

The audio receive FIFO overrun status bit (ARO) is set when the audio receive logic attempts to
place data into the audio receive FIFO after it has been completely filled. Each time a new piece of
data is received, the set signal to the ARO status bit is asserted, and the newly received data is
discarded. This process is repeated for each new sample received until at least one empty FIFO entry
exists. When the ARO bit is set, an interrupt request is made.

5.16.3.7

Telecom Transmit FIFO Underrun Status (TTU) (read/write, non-maskable
interrupt)

The telecom transmit FIFO underrun status bit (TTU) is set when the telecom transmit logic attempts
to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the
telecom transmit logic continuously transmits the last valid telecom value which was transmitted
before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the
bottom, the telecom transmit logic uses the new value within the FIFO for transmission. When the
TTU bit is set, an interrupt request is made.

5.16.3.8

Telecom Receive FIFO Overrun Status (TRO) (read/write, non-maskable
interrupt)

The telecom receive FIFO overrun status bit (TRO) is set when the telecom receive logic places data
into the telecom receive FIFO after it has been completely filled. Each time a new piece of data is
received, the set signal to the TRO status bit is asserted, and the newly received sample is discarded.

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Register Descriptions

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This process is repeated for each new piece of data received until at least one empty FIFO entry
exists. When the TRO bit is set, an interrupt request is made.

5.16.3.9

Audio Transmit FIFO Not Full Flag (ANF) (read-only, non-interruptible)

The audio transmit FIFO not full flag (ANF) is a read-only bit which is set whenever the audio
transmit FIFO contains one or more entries which do not contain valid data and is cleared when the
FIFO is completely full. This bit can be polled when using programmed I/O to fill the audio transmit
FIFO. This bit does not request an interrupt.

5.16.3.10

Audio Receive FIFO Not Empty Flag (ANE) (read-only, non-interruptible)

The audio receive FIFO not empty flag (ANE) is a read-only bit which is set when ever the audio
receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any
valid data. This bit can be polled when using programmed I/O to remove remaining data from the
receive FIFO. This bit does not request an interrupt.

5.16.3.11

Telecom Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible)

The telecom transmit FIFO not full flag (TNF) is a read-only bit which is set when ever the telecom
transmit FIFO contains one or more entries which do not contain valid data. It is cleared when the
FIFO is completely full. This bit can be polled when using programmed I/O to fill the telecom
transmit FIFO. This bit does not request an interrupt.

5.16.3.12

Telecom Receive FIFO Not Empty Flag (TNE) (read-only, non-interruptible)

The telecom receive FIFO not empty flag (TNE) is a read-only bit which is set when ever the telecom
receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any
valid data. This bit can be polled when using programmed I/O to remove remaining data from the
receive FIFO. This bit does not request an interrupt.

5.16.3.13

Codec Write Completed Flag (CWC) (read-only, non-interruptible)

The codec write completed (CWC) flag is set after the following sequence occurs:

1) A register write command is issued to the codec by writing to MCDR2.

2) The write command is sent to the codec via subframe 0.

3) The data value is latched within the addressed codec register at the beginning of subframe 1 (the

65th bit of the frame).

4) The address and value which was written is returned to the MCP via the next subframe 0.

5) The returned value is latched in MCDR2.

CWC is automatically cleared when MCDR2 is read or written. This bit does not request an interrupt.

5.16.3.14

Codec Read Completed Flag (CRC) (read-only, non-interruptible)

The codec read completed (CRC) flag is set after the following sequence occurs:

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Register Descriptions

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1) A register read command is issued to the codec by writing to MCDR2.

2) The read command is sent to the codec via subframe 0.

3) The data value contained within the addressed codec register is loaded into the codec's serial shift

4) The address and value which was read is returned to the MCP via the same subframe 0.

5) The returned value is latched in MCDR2.

CRC is automatically cleared when MCDR2 is read or written. This bit does not request an interrupt.

5.16.3.15

Audio Codec Enabled Flag (ACE) (read-only, non-interruptible)

The audio codec enabled (ACE) flag indicates when the audio codec input and/or output is enabled.
This in turn indicates that the audio sample rate counter is enabled. This flag is set after the following
sequence occurs:

1) A register write command is issued to Audio Control Register B (register 8), and either bit 14 or

15 is set (aud_in_ena or aud_out_ena) by writing to MCDR2.

2) The write command is sent to the codec via subframe 0.

3) The data value is latched within codec register 8.

4) SIBSYNC is asserted to indicate the start of the next frame.

ACE is automatically cleared using the same sequence, with the exception that bit 14 and 15 are
cleared, disabling both the input and output path of the audio codec. This bit does not request an
interrupt.

5.16.3.16

Telecom Codec Enabled Flag (TCE) (read-only, non-interruptible)

The telecom codec enabled (TCE) flag indicates when the telecom codec input and/or output is
enabled. This in turn indicates that the telecom sample rate counter is enabled. This flag is set after
the following sequence occurs:

1) A register write command is issued to Telecom Control Register B (register 6), and either bit 14

or 15 is set (tel_in_ena or tel_out_ena) by writing to MCDR2.

2) The write command is sent to the codec via subframe 0.

3) The data value is latched within codec register 6.

4) SIBSYNC is asserted to indicate the start of the next frame.

TCE is automatically cleared using the same sequence, with the exception, that bit 14 and 15 are
cleared, disabling both the input and output path of the telecom codec. This bit does not request an
interrupt.

The following figure shows the bit locations corresponding to the status and flag bits within the MCP
status register. MCSR contains a collection of read/write, read-only, interruptible, and non-
interruptible bits (refer to the bit descriptions above). Writes to read-only bits have no effect. The

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Register Descriptions

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user must clear set status bits before enabling the MCP. Note that writes to reserved bits are ignored
and reads return zeros.

Figure 5-4. MCP Status Register: MCSR

Address: 0x 8000 2018

MCP Status Register: MCSR

Read/Write &

Read-Only

Bit

Reserved

Reset

Bit

TCE

ACE

CRC

CWC

TNE

TNF

ANE

ANF

TRO

TTU

ARO

ATU

TRS

TTS

ARS

ATS

Reset

Table 5-17. MCP Control, Data and Status Register Locations

Bit

Name

Description

ATS

Audio Transmit FIFO Service Request Flag (read-only)
0 -- Audio transmit FIFO is more than half full (five or more entries filled) or MCP disabled
1 -- Audio transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is
enabled, interrupt request signaled if not masked
(if ATM = 1)

ARS

Audio Receive FIFO Service Request (read-only)
0 -- Audio receive FIFO is less than half full (five or fewer entries filled) or MCP disabled
1 -- Audio receive FIFO is half full or more (six or more entries filled) and MCP operation is
enabled, interrupt request signaled if not masked (if ARM = 1)

TTS

Telecom Transmit FIFO Service Request Flag (read-only)
0 -- Telecom transmit FIFO is more than half full or less (four or fewer entries filled) or MCP
disabled.
1 -- Telecom transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is
enabled, interrupt request signaled if not masked
(if TTM = 1)

TRS

0 -- Telecom receive FIFO is less than half full (five or fewer entries filled) or MCP disabled.
1 -- Telecom receive FIFO is half full or more (six or more entries filled) and MCP operation is
enabled, interrupt request signalled if not masked (if TRM = 1)

ATU

Audio Transmit FIFO Underrun
0 -- Audio transmit FIFO has not experienced an underrun
1 -- Audio transmit logic attempted to fetch data from transmit FIFO while it was empty, request
interrupt

ARO

Audio Receive FIFO Overrun
0 -- Audio receive FIFO has not experienced an overrun
1 -- Audio receive logic attempted to place data into receive FIFO while it was full, request
interrupt

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Register Descriptions

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TTU

Telecom Transmit FIFO Underrun
0 -- Telecom transmit FIFO has not experienced an underrun
1 -- Telecom transmit logic attempted to fetch data from transmit FIFO while it was empty,
request interrupt

TRO

Telecom Receive FIFO Overrun
0 -- Telecom receive FIFO has not experienced an overrun
1 -- Telecom receive logic attempted to place data into receive FIFO while it was full, request
interrupt

ANF

Audio Transmit FIFO Not Full (read-only)
0 -- Audio transmit FIFO is full
1 -- Audio transmit FIFO is not full

ANE

Audio Receive FIFO Not Empty (read-only)
0 -- Audio receive FIFO is empty
1 -- Audio receive FIFO is not empty

TNF

Telecom Transmit FIFO Not Full (read-only)
0 -- Telecom transmit FIFO is full
1 -- Telecom transmit FIFO is not full

TNE

Telecom Receive FIFO Not Empty (read-only)
0 -- Telecom receive FIFO is empty
1 -- Telecom receive FIFO is not empty

CWC

Codec Write Completed (read-only)
0 -- A write to a codec register has not completed since the last time this bit was cleared
1 -- A write to a codec register has been transmitted and has updated the register

CRC

Codec Read Completed (read-only)
0 -- The value read from the addressed codec register has not been returned to MCDR2
1 -- The value read from the addressed codec register is now in MCDR2

ACE

Audio Codec Enabled (read-only)
0 -- The audio codec input and output is disabled (bits 14 and 15 are 0 in Audio codec Control
Reg B)
1 -- Audio codec input and/or output is enabled (bits 14 and/or 15 is 1 in Audio codec Control
Reg B)

TCE

Telecom Codec Enabled
0 -- The telecom codec input and output is disabled (bits 14 and 15 are 0 in Telecom codec
Cntl Reg B)
1 -- Telecom codec input and/or output is enabled (bits 14 and/or 15 is 1 in Telecom codec Cntl
Reg B)

31-16

Reserved

Table 5-17. MCP Control, Data and Status Register Locations

(cont.)

Bit

Name

Description

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Electrical Specifications

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ELECTRICAL SPECIFICATIONS

6.1

Absolute Maximum Ratings

6.2

Recommended Operating Conditions

6.3

DC Characteristics

All characteristics are specified at V

= 2.5 volts and V

= 0 volts over an operating temperature

of 0°C to +70°C for all frequencies of operation. The current consumption figures relate to typical
conditions at 2.5 V, 18.432 MHz operation with the PLL switched `on'.

DC Core, PLL, and RTC Supply Volt-
age

2.9 V

DC I/O Supply Voltage (Pad Ring)

3.6 V

DC Pad Input Current

±10 mA/pin; ±100 mA cum-
mulative

Storage Temperature, No Power

°C to +125°C

DC core, PLL, and RTC Supply Volt-
age

2.5 V

± 0.2 V

DC I/O Supply Voltage (Pad Ring)

2.3V - 3.6V

DC Input/Output Voltage

OI/O supply voltage

Operating Temperature

°C to +70°C

Table 6-1. DC Characteristics

Symbol

Parameter

Min

Max

Unit

Conditions

VIH

CMOS input high voltage

1.7

+ 0.3

= 2.5 V

VIL

CMOS input low voltage

-0.3

0.8

= 2.5 V

VT+

Schmitt trigger positive going
threshold

1.6 (Typ)

2.0

VT-

Schmitt trigger negative going
threshold

0.8

1.2 (Typ)

Vhst

Schmitt trigger hysteresis

0.1

0.4

VIL to VIH

VOH

CMOS output high voltageOut-
put drive 1
Output drive 2

0.2

2.5
2.5

V
V
V

IOH = 0.1 mA
OH = 4 mA
OH = 12 mA

VOL

CMOS output low voltageOut-
put drive 1
Output drive 2

0.3
0.5
0.5

V
V
V

IOL = 0.1 mA
OL = 4 mA
OL = 12 mA

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NOTE: All power dissipation values can be derived from taking the particular IDD current and multiplying by

2.5 V.

The RTC of the EP7211 should be brought up at room temperature. This is required because the RTC
OSC will NOT function properly if it is brought up at 40

°C. Once operational, it will continue to oper-

ate down to 40

°C.

A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic.
This is to allow the I/O to be compatible with 3.3 V powered external logic (e.g., 3.3 V DRAMs).

Pull-up current = 50 µA typical at V

= 3.3 volts.

IIN

Input leakage current

µA

VIN = V

or GND

IOZ

Output tri-state leakage current*

100

µA

VOUT = V

or GND

CIN

Input capacitance

COUT

Output capacitance

CI/O

Transceiver capacitance

IDD

startup

Startup current consumption

µA

Initial 100 ms from power up, 32
kHz oscillator not stable, POR
signal at VIL, all other I/O static,
VIH = V

± 0.1 V, VIL = GND ±

0.1 V

IDD

standby

Standby current consumption

µA

Just 32 kHz oscillator running,
all other I/O static, VIH = V

0.1 V, VIL = GND ± 0.1 V

IDD

idle

Idle current consumption
At 13 MHz
At 18 MHz
At 36 MHz

4.2

Both oscillators running, CPU
static, LCD refresh active, VIH =
V

± 0.1 V, VIL = GND ± 0.1 V

IDD

operating

Operating current consumption
At 13 MHz
At 18 MHz
At 36 MHz
At 49 MHz
At 74 MHz

14
20
40
50
68

All system active, running typi-
cal program

DDstandby

Standby supply voltage

TBD

Minimum standby voltage for
state retention and RTC opera-
tion only

Table 6-1. DC Characteristics

(cont.)

Symbol

Parameter

Min

Max

Unit

Conditions

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Electrical Specifications

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6.4

AC Characteristics

All characteristics are specified at V

= 2.3 to 2.7 volts and V

= 0 volts over an operating

temperature of 0

°C to +70°C. Those characteristics marked with a # will be significantly different

for 13 MHz mode because the EXPCLK is provided as an input rather than generated internally.
These timings are estimated at present. The timing values are referenced to 1/2 V

Table 6-2. AC Timing Characteristics

Symbol

Parameter

13 MHz

18/36 MHz

Units

Min

Max

Min

Max

Falling CS to data bus Hi-Z

Address change to valid write data

DATA in to falling EXPCLK setup time

0 #

DATA in to falling EXPCLK hold time

10 #

EXPRDY to falling EXPCLK setup time

0 #

Falling EXPCLK to EXPRDY hold time

10 #

Rising NMWE to data invalid hold time

Sequential data valid to falling NMWE setup time

Row address to falling NRAS setup time

T10

Falling NRAS to row address hold time

T11

Column address to falling NCAS setup time

T12

Falling NCAS to column address hold time

T13

Write data valid to falling NCAS setup time

T14

Write data valid from falling NCAS hold time

T15

LCD CL2 low time

3,475

T16

LCD CL2 high time

3,475

T17

LCD falling CL2 to rising CL1 delay

T18

LCD falling CL1 to rising CL2

3,475

T19

LCD CL1 high time

3,475

T20

LCD falling CL1 to falling CL2

200

6,950

200

6,950

T21

LCD falling CL1 to FRM toggle

300

10,425

300

10,425

T22

LCD falling CL1 to M toggle

T23

LCD rising CL2 to display data change

T24

Falling EXPCLK to address valid

33 #

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

135

Electrical Specifications

DS352PP3
JUL 2001

T25

Data valid to falling NMWE for non sequential access
only

T31

SSICLK period (slave mode)

512

kHz

T32

SSICLK high

925

1025

925

1025

T33

SSICLK low

925

1025

925

1025

T34

SSICLK rise/fall time

T35

SSICLK rising to RX and/or TX frame sync

528

T36

SSICLK rising edge to frame sync low

448

T37

SSICLK rising edge to TX data valid

T38

SSIRXDA data set-up time

T39

SSIRXDA data hold time

T40

SSITXFR and/or SSIRXFR period

750

Table 6-3. Timing Characteristics

Symbol

Characteristics

13 MHz

18 MHz

36 MHz

Units

Min

Max

Min

Max

Min

Max

NCSRD

Negative strobe (NCS[05]) zero wait
state read access time

120

NCSWR

Negative strobe (NCS[05]) zero wait
state write access time

120

EXBST

Sequential expansion burst mode
read access time

DRAM cycle time

230

150

RAC

Access time from RAS

110

RAS precharge time

110

CAS

CAS pulse width

CAS precharge in page mode

Page mode cycle time

CSR

CAS set-up time for auto refresh

RAS

RAS pulse width

110

80 *

50*

Table 6-2. AC Timing Characteristics

(cont.)

Symbol

Parameter

13 MHz

18/36 MHz

Units

Min

Max

Min

Max

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

137

Electrical Specifications

DS352PP3
JUL 2001

Figure 6-2. Expansion and ROM Sequential Read Timings

NOTES:

1) t

EXBST

= 35 ns at 36.864 MHz

70 ns at 18.432 MHz
120 ns at 13.0 MHz
(Value for 36.864 MHz assumes 1 wait state.)

Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz and 77 ns at 13 MHz), by either driving
EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock
period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY,
but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential access

wait state field is used to determine the number of wait states, and no idle cycles are inserted
between successive non-sequential ROM/expansion cycles. This improves performance so the
SQAEN bit should always be set where possible.

EXPCLK

NCS[5:0]

NMOE

A[27:4]

D[31:0]

EXPRDY

Bus held

WORD

A[3:0]

Data in

(;%67

(;5'

7 7

Sequential page mode read cycles with minimum wait

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

138

Electrical Specifications

DS352PP3

JUL 2001

Figure 6-3. Expansion and ROM Write Timings

NOTES:

1) t

EXWR

= 35 ns at 36.864 MHz

70 ns at 18.432 MHz
120 ns at 13.0 MHz

Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving
EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock
period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY,
but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential access

3) Zero wait states for sequential writes is not permitted for memory devices which use NMWE pin, as

this cannot be driven with valid timing under zero wait state conditions.

EXPCLK

NCS[5:0]

NMWE

A[27:0]

D[31:0]

EXPRDY

WORD

Bus held

Write data

1&6:5

$':5

Consecutive expansion write cycles with minimum wait states

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

150

Test Modes

DS352PP3

JUL 2001

TEST MODES

The EP7211 supports a number of hardware activated test modes, these are activated by the pin
combinations shown in the Table 7-1. EP7211 Hardware Test Modes. All latched signals will only
alter test modes while NPOR is low, their state is latched on the rising edge of NPOR. This allows
these signals to be used normally during various test modes.

Within each test mode, a selection of pins is used as multiplexed outputs or inputs to provide/monitor
the test signals unique to that mode.

7.1

Oscillator and PLL Bypass Mode

This mode is selected by NTEST0 = 1, NTEST1 = 0.

In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator
pins become the direct external oscillator inputs bypassing the oscillator and PLL. MOSCIN must be
driven by a 36.864 MHz clock source and RTCIN by a 32.768 kHz source.

7.2

Oscillator and PLL Test Mode

This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 0

This test mode will enable the main oscillator and it will output various buffered clock and test
signals derived from the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the EP7211
will be static and isolated from the oscillators, with the exception of the 6-bit ripple counter used to
generate 576 kHz and the real time clock divide chain. Port A is used to drive the inputs of the PLL
directly, and the various clock and PLL outputs are monitored on the COL pins. Table 7-2.

Table 7-1. EP7211 Hardware Test Modes

Test Mode

Latched

NMEDCHG

Latched

PE0

Latched

PE1

Latched

NURESET

NTEST0

NTEST1

Normal operation
(32-bit boot)

Normal operation
(8-bit boot)

Normal operation
(16-bit boot)

Alternative test ROM boot

Oscillator / PLL bypass

Oscillator / PLL test mode

ICE Mode

System test (all HiZ)

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

151

Test Modes

DS352PP3
JUL 2001

Oscillator and PLL Test Mode Signals defines the EP7211 signal pins used in this test mode. This
mode is only intended to allow test of the oscillators and PLL.

Note that these inputs are inverted before being passed to the PLL to ensure that the default state of
the port (all zero) maps onto the correct default state of the PLL (TSEL = 1, XTALON = 1, PLLON
= 1, D0 = 0, D1 = 1, PLLBP = 0). This state will produce the correct frequencies as shown in Table
7-2. Oscillator and PLL Test Mode Signals. Any other combinations are for testing the oscillator
and PLL and should not be used in-circuit.

7.3

Debug/ICE Test Mode

This mode is selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 1.

Selection of this mode enables the debug mode of the ARM720T. By default, this is disabled which
saves approximately 3% on power.

7.4

Hi-Z (System) Test Mode

This mode selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 0.

This test mode asynchronously disables all output buffers on the EP7211. This has the effect of
removing the EP7211 from the PCB so that other devices on the PCB can be in-circuit tested. The
internal state of the EP7211is not altered directly by this test mode.

7.5

Software Selectable Test Functionality

When Bit 11 of the SYSCON register is set high, internal peripheral bus register accesses are output
on the main address and data buses as though they were external accesses to the address space
addressed by CS5. Hence, CS5 takes on a dual role, it will be active as the strobe for internal accesses
and for any accesses to the standard address range for CS5. Additionally, in this mode, the internal

Table 7-2. Oscillator and PLL Test Mode Signals

Signal

I/O

Pin

Function

TSEL *

PA5

PLL test mode

XTLON *

PA4

Enable to oscillator circuit

PLLON *