Advance Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright

Cirrus Logic, Inc.
http://www.cirrus.com

CS8416

192 kHz Digital Audio Interface Receiver

Features

Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible receiver
+3.3 V Analog Supply(VA)
+3.3 V to +5.0 V Digital Interface Supply (VL)
+3.3 V Digital Supply (VD)
8:2 S/PDIF Input MUX
AES/SPDIF input pins selectable in hardware
mode
3 General Purpose Outputs (GPO) allow signal
routing
Selectable signal routing to GPO pins
S/PDIF to TX inputs selectable in hardware mode
Flexible 3-wire serial digital output port
32 kHz to 192 kHz sample frequency range
Low jitter clock recovery
Pin and microcontroller read access to Channel
Status and User data
SPI or I

C control port Software Mode and

standalone Hardware Mode
Differential cable receiver
On-chip Channel Status data buffer memories
Auto-detection of compressed audio input
streams
Decodes CD Q sub-code
OMCK System Clock Mode

General Description

The CS8416 is a monolithic CMOS device which re-
ceives and decodes one of 8 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3 interface standards. The CS8416 has a serial dig-
ital audio output port and comprehensive control ability
through a selectable control port in Software Mode or
through selectable pins in Hardware Mode. Channel sta-
tus data are assembled in buffers, making read access
easy.

GPO pins may be assigned to route a variety of signals
to output pins

A low jitter clock recovery mechanism yields a very clean
recovered clock from the incoming AES3 stream.

Stand-alone operation allows systems with no microcon-
troller to operate the CS8416 with dedicated output pins
for channel status data.

Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and au-
tomotive audio systems.

ORDERING INFORMATION

CS8416-CS

28-pin SOIC

-10 to +70°C

CS8416-CZ

28-pin TSSOP

-10 to +70°C

CS8416-IS

28-pin SOIC

-40 to +85°C

CS8416-IZ

28-pin TSSOP

-40 to +85°C

Clock &
Data
Recovery

Misc.
Control

Serial
Audio
Output

Receiver

AES3
S/PDIF
Decoder

Control
Port &
Registers

RXN

RXP1

OLRCK
OSCLK
SDOUT

RST

SDA/
CDOUT

SCL/
CCLK

AD1/
CDIN

AD0/
CS

VA+ AGND FILT

VL + DGND

RMCK

RXP2
RXP3
RXP4
RXP5
RXP6
RXP7

8:2

MUX

OMCK

GPO0
GPO1
AD2/GPO2

RXP0

VD+

n:3

MUX

De-emphasis

Filter

C & U bit

Data Buffer

AUG `02

DS578PP2

CS8416

DS578PP2

TABLE OF CONTENTS

1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5

Power and Thermal Characteristics.......................................................................................... 5
Absolute Maximum Ratings ...................................................................................................... 5
Digital Characteristics ............................................................................................................... 6
Switching Characteristics - Serial Audio Ports.......................................................................... 7
Switching Characteristics - Control Port - SPI Mode ................................................................ 8
Switching Characteristics - Control Port- I

C format................................................................. 9

2 TYPICAL CONNECTION DIAGRAMS .................................................................................... 10
3 GENERAL DESCRIPTION ...................................................................................................... 12

3.1 AES3 and S/PDIF Standards Documents ........................................................................ 12

4 SERIAL AUDIO OUTPUT PORT ............................................................................................. 13

4.1 Slip/Repeat Behavior ....................................................................................................... 13
4.2 AES11 Behavior .............................................................................................................. 14

5 S/PDIF RECEIVER .................................................................................................................. 16

5.1 8:2 S/PDIF Input Multiplexer ............................................................................................ 16
5.2 PLL, Jitter Attenuation, and Clock Switching ................................................................... 16

5.2.1 OMCK System Clock Mode ................................................................................ 17
5.2.2 PLL External Components .................................................................................. 17

5.3 Error Reporting and Hold Function .................................................................................. 17
5.4 Channel Status Data Handling ......................................................................................... 18
5.5 User Data Handling .......................................................................................................... 18

5.5.1 Non-Audio Auto-Detection .................................................................................. 18

6 CONTROL PORT DESCRIPTION AND TIMING ..................................................................... 20

6.1 SPI Mode ......................................................................................................................... 20
6.2 I

C Mode .......................................................................................................................... 21

6.3 General Purpose Outputs ................................................................................................ 22
6.4 Interrupts .......................................................................................................................... 22

7 CONTROL PORT REGISTER SUMMARY ............................................................................. 23
8 CONTROL PORT REGISTER BIT DEFINITIONS ................................................................... 25

8.1 Control0 (00h) ................................................................................................................... 25
8.2 Control1 (01h) ................................................................................................................... 25

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
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marks or service marks of their respective owners.

CS8416

DS578PP2

8.3 Control2 (02h)................................................................................................................... 26
8.4 Control3 (03h)................................................................................................................... 26
8.5 Control4 (04h)................................................................................................................... 27
8.6 Serial Audio Data Format (05h) ........................................................................................ 27
8.7 Receiver Error Mask (06h) .............................................................................................. 29
8.8 Interrupt Mask (07h) ......................................................................................................... 29
8.9 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h) ................................................ 29
8.10 Receiver Channel Status (0Ah) ..................................................................................... 30
8.11 Format Detect Status (0Bh) ............................................................................................ 30
8.12 Receiver Error (0Ch) ..................................................................................................... 31
8.13 Interrupt 1 Status (0Dh) ................................................................................................. 32
8.14 Q-Channel Subcode (0Eh - 17h) .................................................................................... 32
8.15 OMCK/RMCK Ratio (18h) .............................................................................................. 33
8.16 Channel Status Registers (19h - 22h) ............................................................................ 33
8.17 IEC61937 PC/PD Burst preamble (23h - 26h)................................................................ 33
8.18 CS8416 I.D. and Version Register (7Fh) ........................................................................ 33
8.19 Memory Address Pointer (MAP) ..................................................................................... 34

9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................ 35
10 HARDWARE MODE .............................................................................................................. 37

10.1 Serial Audio Port Formats ............................................................................................. 37

11 PIN DESCRIPTION - HARDWARE MODE ........................................................................... 38

11.1 Hardware Mode Function Selection .............................................................................. 40
11.2 Hardware Mode Settings (Defaults & Controls) ............................................................. 40

12 APPLICATIONS .................................................................................................................... 42

12.1 Reset, Power Down and Start-up .................................................................................. 42
12.2 ID Code and Revision Code .......................................................................................... 42
12.3 Power Supply, Grounding, and PCB layout ................................................................... 42

13 PACKAGE DIMENSIONS ..................................................................................................... 43
14 APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS .............. 45

14.1 AES3 Receiver External Components ........................................................................... 45
14.2 Isolating Transformer Requirements ............................................................................. 45

15 APPENDIX B: CHANNEL STATUS BUFFER MANAGEMENT .......................................... 47

15.1 AES3 Channel Status (C) Bit Management ................................................................... 47
15.2 Accessing the E buffer ................................................................................................... 47

15.2.1 Serial Copy Management System (SCMS) ....................................................... 47

CS8416

DS578PP2

LIST OF FIGURES

Figure 1. Audio Port Master Mode Timing....................................................................................... 7
Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 7
Figure 3. SPI Mode Timing.............................................................................................................. 8
Figure 4. I2C Mode Timing.............................................................................................................. 9
Figure 5. Typical Connection Diagram - Software Mode............................................................... 10
Figure 6. Typical Connection Diagram - Hardware Mode ............................................................. 11
Figure 7. AES3 Data Format ......................................................................................................... 14
Figure 8. Serial Audio Output Example Formats........................................................................... 15
Figure 9. C/U data outputs ............................................................................................................ 19
Figure 10. De-emphasis filter ........................................................................................................ 19
Figure 11. Control Port Timing In SPI Mode ................................................................................. 20
Figure 12. Control Port Timing in I

C Mode .................................................................................. 21

Figure 13. Hardware Mode Data Flow .......................................................................................... 37
Figure 14. Professional Input Circuit ............................................................................................. 46
Figure 15. Transformerless Professional Input Circuit .................................................................. 46
Figure 16. Consumer Input Circuit ................................................................................................ 46
Figure 17. S/PDIF MUX Input Circuit ............................................................................................ 46
Figure 18. TTL/CMOS Input Circuit............................................................................................... 46
Figure 19. Channel Status Data Buffer Structure .......................................................................... 47
Figure 20. Flowchart for Reading the E Buffer .............................................................................. 47

LIST OF TABLES

Table 1. Delays by Frequency Values ................................................................................................. 14
Table 2. External PLL Component Values........................................................................................... 17
Table 3. GPO Pin Configurations ........................................................................................................ 22
Table 4. Hardware Mode Serial Audio Format Select ......................................................................... 41

CS8416

DS578PP2

1 CHARACTERISTICS AND SPECIFICATIONS

POWER AND THERMAL CHARACTERISTICS

(AGND, DGND = 0 V, all voltages with respect to ground)

Notes: 1. Assumes that no digital inputs are left floating. It is recommended that all digital inputs be driven high

or low at all times.

2. `-CS' and `-CZ' parts are specified to operate over -10° C to 70° C but are tested at 25° C only.

3. `-IS' and `-IZ' parts are tested over the full -40° C to 85° C temperature range.

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND = 0 V, all voltages with respect to ground)

Notes: 4. Transient currents of up to 100mA will not cause SCR latch-up.

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply Voltage

VA+

3.13

3.3

3.46

VD+

3.13

3.3

3.46

VL+

3.13

3.3

5.5

Supply Current at 48 KHz frame rate

5.7

5.9

2.8

Supply Current at 192 KHz frame rate

(

Note 1

)

9.4

7.8

Supply Current in Power Down

Ambient Operating Temperature: `-CS' & `-CZ'

(Note 2)

`-IS' & `-IZ'

(Note 3)

-10°
-40°

25°

70°
85°

°C

Parameter

Symbol

Min

Max

Unit

Power Supply Voltage

VD+, VA+, VL+

Volts

Input Current, Any Pin Except Supplies
(

Note 4

)

-10

Input Voltage

-0.3

+.03

Volts

Ambient Operating Temperature

CS8416-C

CS8416-I

-10°
-40°

70°
85°

°C
°C

CS8416

DS578PP2

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

= 25 °C for suffixes `CS' & 'CZ', T

= -40 to 85 °C for `IS' & `IZ' ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.5

V, Inputs: Logic 0 = 0 V, Logic 1 = VL+; C

= 20 pF)

Notes: 5. In Software mode the active edges of OSCLK are programmable.

6. In Software mode the polarity of OLRCK is programmable.

7. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK

has changed.

8. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.

Parameter

Symbol

Min

Typ

Max

Units

OSCLK Active Edge to SDOUT Output Valid

(Note 5

)

dpd

Master Mode

RMCK to OSCLK active edge delay

(

Note 5

)

smd

RMCK to OLRCK delay

(

Note 6

)

lmd

OSCLK and OLRCK Duty Cycle

Slave Mode

OSCLK Period

sckw

OSCLK Input Low Width

sckl

OSCLK Input High Width

sckh

OSCLK Active Edge to OLRCK Edge

(

Notes 5,6,7

)

lrckd

OSCLK Edge Setup Before OSCLK Active-Edge

(

Notes 5,6,8

)

lrcks

Figure 1. Audio Port Master Mode Timing

Figure 2. Audio Port Slave Mode and Data Input Timing

sckh

sckl

sckw

tdpd

SDOUT

(input)

lrcks

lrckd

OSCLK

OLRCK

O S C L K

O L R C K

(o u tp u t)

R M C K

s m d

lm d

(o utp ut)

CS8416

DS578PP2

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

= 25 °C for suffixes `CS' &'CZ', T

= -40 to 85°C for `IS' & `IZ' ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 to 5.5V,

Inputs: Logic 0 = 0 V, Logic 1 = VL+; C

= 20 pF)

Notes: 9. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is

dictated by the timing requirements necessary to access the Channel Status memory. Access to the
control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate
is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible
conditions.

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For f

sck

<1 MHz.

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

(

Note 9

)

sck

6.0

MHz

CS High Time Between Transmissions

csh

1.0

µs

CS Falling to CCLK Edge

css

CCLK Low Time

scl

CCLK High Time

sch

CDIN to CCLK Rising Setup Time

dsu

CCLK Rising to DATA Hold Time

(

Note 10

)

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

Fall Time of CDOUT

Rise Time of CCLK and CDIN

(

Note 11

)

100

Fall Time of CCLK and CDIN

(

Note 11

)

100

t r2

t f2

t dsu

t dh

t sch

t scl

CCLK

CDIN

t css

t pd

CDOUT

t csh

Figure 3. SPI Mode Timing

CS8416

DS578PP2

3 GENERAL DESCRIPTION

The CS8416 is a monolithic CMOS device which
receives and decodes audio data according to the
AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter-
face standards.

The CS8416 utilizes an 8:2 multiplexer to select
between eight inputs for decoding and to allow an
input signal to be routed to an output of the
CS8416. Input data is either differential or single-
ended. A low jitter clock is recovered from the in-
coming data using a PLL. The decoded audio data
is output through a configurable, 3-wire output
port. The channel status and Q-channel subcode
portion of the user data are assembled in registers
and may be accessed through an SPI or I

C port.

Three General Purpose Output (GPO) pins are pro-
vided to allow a variety of signals to be accessed
under software control. In hardware mode, dedicat-
ed pins are used to select audio stream inputs for
decoding and transmission to a dedicated TX pin.
Hardware mode also allows direct access to chan-
nel status and user data output pins.

Figure 5

and

Figure 6

show the power supply and

external connections to the CS8416 when config-
ured for software and hardware modes. Please note

that all I/O pins, including RXN and RXP[7:0], op-
erate at the VL+ voltage.

3.1

AES3 and S/PDIF Standards
Documents

This document assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advis-
able to have current copies of the AES3, IEC60958,
and IEC61937 specifications on hand for easy ref-
erence.

The latest AES3 standard is available from the Au-
dio Engineering Society or ANSI at

www.aes.org

or at

www.ansi.org

. Obtain a copy of the latest

IEC60958/61937 standard from ANSI or from the
International

Electrotechnical

Commission

www.iec.ch

. The latest EIAJ CP-1201 standard is

available from the Japanese Electronics Bureau.

Application Note 22: Overview of Digital Audio In-
terface Data Structures contains a useful tutorial
on digital audio specifications, but it should not be
considered a substitute for the standards.

The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as reprint 3518.

CS8416

DS578PP2

4 SERIAL AUDIO OUTPUT PORT

A 3-wire serial audio output port is provided. The
port can be adjusted to suit the attached device set-
ting the control registers. The following parameters
are adjustable: master or slave, serial clock fre-
quency, audio data resolution, left or right justifica-
tion of the data relative to left/right clock, optional
one-bit cell delay of the first data bit, the polarity of
the bit clock, and the polarity of the left/right clock.
By setting the appropriate control bits, many for-
mats are possible.

Figure 8

shows a selection of common output for-

mats, along with the control bit settings. A special
AES3 direct output format is included, which al-
lows the serial output port access to the V, U, and
C bits embedded in the serial audio data stream.
The P bit, which would normally be a parity bit, is
replaced by a Z bit, which is used to indicate the
start of each block. The received channel status
block start signal is also available as the RCBL pin
in hardware mode and through a GPO pin in soft-
ware mode.

In master mode, the left/right clock (OLRCK) and
the serial bit clock (OSCLK) are outputs, derived
from the recovered RMCK clock. In slave mode,
OLRCK and OSCLK are inputs. OLRCK is nor-
mally synchronous to the appropriate master clock,
but OSCLK can be asynchronous and discontinu-
ous if required. By appropriate phasing of OLRCK
and control of the serial clocks, multiple CS8416's
can share one serial port. OLRCK should be con-
tinuous, but the duty cycle can be less than the
specified typical value of 50% if enough serial
clocks are present in each phase to clock all the data
bits. When in slave mode, the serial audio output
port cannot be set for right-justified data. The
CS8416 allows immediate mute of the serial audio
output port audio data by the MUTESAO bit of
Control Register 1.

4.1

Slip/Repeat Behavior

When using the serial audio output port in slave
mode with an OLRCK input that is asynchronous
to the incoming AES3 data, the interrupt bit OSLIP
(bit 5 in the Interrupt 1 Status register, 0Dh) is pro-
vided to indicate when repeated or dropped sam-
ples occur. Refer to

Figure 7

for a AES3 data

format diagram.

When the serial output port is configured as slave,
depending on the relative frequency of OLRCK to
the input AES3 data (Z/X) preamble frequency, the
data will be slipped or repeated at the output of the
CS8416.

After a fixed delay from the Z/X preamble (a few
periods of the internal clock, which is running at
256Fs), the circuit will look back in time until the
previous Z/X preamble:

1) If during that time, the internal data buffer was

not updated, then a slip has occurred. Data from
the previous frame will be output and OSLIP
will be set to 1. Due to the OSLIP bit being
"sticky," it will remain 1 until the register is
read. It will then be reset until another slip/re-
peat condition occurs.

2) If during that time the internal data buffer did

not update between two positive or negative
edges (depending on OLRPOL) of OLRCK,
then a repeat has occurred. In this case the buff-
er data was updated twice, so the part has lost
one frame of data. This event will also trigger
OSLIP to be set to 1. Due to the OSLIP bit be-
ing "sticky," it will remain 1 until the register is
read. It will then be reset until another slip/re-
peat condition occurs.

3) If during that time, it did see a positive edge on

OLRCK (or negative edge if the SOLRPOL is
set to 1) then no slip or repeat has happened.
Due to the OSLIP bit being "sticky," it will re-
main in its previous state until either the regis-
ter is read or a slip/repeat condition occurs.

CS8416

DS578PP2

If the user reads OSLIP as soon as the event trig-
gers, over a long period of time the rate of occur-
ring INT will be equal to the difference in
frequency between the input AES data and the
slave serial output LRCK. The CS8416 uses a hys-
teresis window when a slip/repeat event occurs.
The slip/repeat is triggered when an edge of OL-
RCK passes a window size from the beginning of
the Z/X preamble. Without the hysteresis window,
jitter on OLRCK with a frequency very close to Fs
could slip back and forth, causing multiple slip/re-
peat events. The CS8416 uses a hysteresis window
to ensure that only one slip/repeat happens even
with jitter on OLRCK.

4.2

AES11 Behavior

When OLRCK is configured as a master, the posi-
tive or negative edge of OLRCK (depending on the
setting of SOLRPOL in register 05h) will be within
-1.0%(1/Fs) to 1.1%(1/Fs) from the start of the pre-
amble X/Z. In master mode, the latency through the
part is dependent on the input sample frequency.
The delay through the part from the beginning of
the preamble to the active edge of OLRCK for the
various sample frequencies is given in

Table 1

. In

master mode without the de-emphasis filter en-
gaged, the latency of the audio data will be 3
frames.

When OLRCK is configured as a slave any syn-
chronized input within +/-28%(1/Fs) from the pos-
itive or negative edge of OLRCK (depending on
the setting of SOLRPOL in register 05h) will be
treated as being sampled at the same time. Since the
CS8416 has no control of the OLRCK in slave
mode, the latency of the data through the part will
be a multiple of 1/Fs plus the delay between OL-
RCK and the preambles.

Both of these conditions are within the tolerance
range set forth in the AES11 standard.

Channel A

Data

Channel B

Data

Channel A

Data

Channel B

Data

Channel A

Data

Channel B

Data

Frame 191

Frame 0

Frame 1

Preambles

OLRCK (in slave mode)

Figure 7. AES3 Data Format

Fs (kHz)

Delay (ns)

96.6

44.1

78.6

74.6

60.6

50.6

192

TBD

Table 1. Delays by Frequency Values

CS8416

DS578PP2

5 S/PDIF RECEIVER

The CS8416 includes an AES3/SPDIF digital au-
dio receiver. The AES3 receiver accepts and de-
codes audio and digital data according to the AES3,
IEC60958 (S/PDIF), and EIAJ CP-1201 interface
standards. The receiver consists of an analog differ-
ential input stage, driven through analog input pins
RXP0 to RXP7 and a common RXN, a PLL based
clock recovery circuit, and a decoder which sepa-
rates the audio data from the channel status and
user data.

Software Mode

The first 5 bytes of both channels status block is
stored in dedicated registers. Channel A status data
is stored in control port registers 19h to 1Dh. Chan-
nel B status data is stored in control port registers
1Eh to 22h.

Q Subcode data is stored in control port registers
0Eh to 17h.

PC Burst preamble is stored in control port regis-
ters 23h and 24h. PD Burst preamble is stored in
control port registers 25h and 26h.

U and C data may be selected for output on GPO
pins.

External components are used to terminate and iso-
late the incoming data cables from the CS8416.
These components are detailed in Appendix A.

Hardware Mode

U and C bits are output on pins 18 and 19 respec-
tively. See Section

"Hardware Mode Function Se-

lection" on page 40

and

"Hardware Mode Settings

(Defaults & Controls)" on page 40

to configure

these pins.

5.1

8:2 S/PDIF Input Multiplexer

The CS8416 employs a 8:2 S/PDIF input multi-
plexer to accommodate up to eight channels of in-
put digital audio data. Digital audio data may be
single- ended or differential. Differential inputs uti-
lize RXP[0-7] and a shared RXN. Single ended sig-

nals are accommodated by using RXP inputs and
AC coupling RXN to ground.

All inputs to the CS8416 8:2 input multiplexer
should be coupled through a capacitor. The recom-
mended capacitor value is 0.01uF to 0.1uF. The
recommended dielectrics are COG or X7R.

Software Mode

The multiplexer select line control is accessed
through bits RXSEL[2:0] in control port register 4.
The multiplexer defaults to RXP0.

The second output of the input multiplexer is used
to provide the selected input as a source to be out-
put on a GPO pin via the internal TX pin. This pass
through signal is selected by TXSEL[2:0] in con-
trol port register 04h. The single-ended signal is re-
solved to full-rail, but is not de-jittered before it is
output.

Hardware Mode

In hardware mode the input to the decoder is select-
ed by dedicated pins, RXSEL[1:0].

The pass through signal is selected by dedicated
pins, TXSEL[1:0] for output on the dedicated TX
pin.

Selectable inputs are restricted to RXP0 to RXP3
for both the receiver and the TX output pin. These
inputs are selected by RXSEL[1:0] and TX-
SEL[1:0] respectively.

General

Unused multiplexer inputs should be left floating
or grounded.

The input voltage range for the input multiplexer is
set by the I/O power supply pin, VL+. The input
voltage of the RXP and RXN pins is also set by the
level of VL+.

5.2

PLL, Jitter Attenuation, and Clock
Switching

An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream.

CS8416

DS578PP2

There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is
important. For this reason, the PLL has been de-
signed to have good jitter attenuation characteris-
tics. In addition, the PLL has been designed to only
use the preambles of the AES3 or S/PDIF stream to
provide lock update information to the PLL. This
results in the PLL being immune to data dependent
jitter affects because the AES3 or S/PDIF pream-
bles do not vary with the data.

In applications where jitter must be minimized,
special attention should be given to reducing the
noise on the analog power supply and ground for
the PLL filter components. Connecting the filter
components directly to AGND will help decrease
jitter.

The PLL has the ability to lock onto a wide range
of input sample rates with no external component
changes.

5.2.1

OMCK System Clock Mode

A special clock switching mode is available that al-
lows the OMCK clock input to replace RMCK
when the PLL becomes unlocked.

In Software mode this feature is enabled by setting
SWCLK bit in Control1 register to a "1".

In Hardware Mode this feature is always active.

Clock switching is accomplished without spurious
transitions or glitches on RMCK.

OSCLK and OLRCK are derived from the OMCK
input when the clock has been switched and the se-
rial port is in master mode.

When the PLL loses lock, the frequency of the
VCO drops to ~500 kHz. When this system clock
mode is not enabled, the OSCLK and OLRCK will
be based on the VCO when the PLL is not locked

5.2.2

PLL External Components

The PLL behavior is affected by the external filter
component values.

Figure 5

and

Figure 6

show the

recommended configuration of the two capacitors
and one resistor required. There are two sets of
component values recommended, depending on the
sample rate of the application. (See

Table 2

.) The

default set, called "fast", accommodates input sam-
ple rates of 96 KHz to 192 Hz with no component
changes. It has the highest corner frequency jitter
attenuation curve, and takes the shortest time to
lock. The alternate component set, called "medi-
um" allows the lowest input sample rate to be 32
kHz, and increases the lock time of the PLL. Lock
times are worst case for an Fs transition from un-
locked state to locking to 192 kHz.

It is important to treat the PLL FLT pin as a low
level analog input. It is suggested that the ground
end of the PLL filter be returned directly to the
AGND pin independently of the digital ground
plane.

5.3

Error Reporting and Hold Function

Software Mode

While decoding the incoming AES3 data stream,
the CS8416 can identify several kinds of error, in-
dicated in the Receiver Error register (0Ch).

The errors indicated are:

1) QCRC CRC error in Q subcode data

2) CCRC CRC error in channel status data

3) UNLOCK PLL is not locked to incoming data

stream

4) V Data Validity bit is set

5) CONF Input data stream is near error condi-

tion due to jitter degradation

6) BIP Biphase encoding error

7) PAR Parity error in incoming data

Range

(kHz)

Rflt

Cflt

Crip

Settling

Time

32 - 192

1 K

220 nF

10 nF

11ms

medium

96 - 192

3 K

22 nF

1 nF

4ms

fast

Table 2. External PLL Component Values

CS8416

DS578PP2

The error bits are "sticky"; they are set on the first

occurrence of the associated error and will remain
set until the user reads the register through the con-
trol port. This enables the register to log all un-
masked errors that occurred since the last time the
register was read.

As a result of the bits "stickiness", it is necessary to
perform two reads on these registers to see if the er-
ror condition still exists.

The Receiver Error Mask register (06h) allows
masking of individual errors. The bits in this regis-
ter default to 00h and serve as masks for the corre-
sponding bits of the Receiver Error register. If a
mask bit is set to 1, the error is unmasked, which
implies the following: its occurrence will be report-
ed in the receiver error register, induce a pulse on
RERR, invoke the occurrence of a RERR interrupt,
and affect the current audio sample according to the
status of the HOLD bits. The exceptions are the
QCRC and CCRC errors, which do not affect the
current audio sample, even if unmasked.

The HOLD bits allow a choice of:

Holding the previous sample

Replacing the current sample with zero (mute)

Not changing the current audio sample

RERR The logical OR of all unmasked receiver
error bits, not `sticky". RERR may be selected for
output on a GPO pin.

NVERR Non-Validity Receiver error

Hardware Mode

In Hardware mode the user may choose between
NVERR or RERR by pulling the NV/RERR pin
low or high respectively.

5.4

Channel Status Data Handling

Software Mode

The first 5 bytes of the Channel Status block are de-
coded into the Receiver Channel Status Registers

19h - 22h. Registers 19h - 1Dh contain the A chan-
nel status data. Registers 1Eh - 22h contain the B
channel status data.

The EMPH, C, and U bits may be selected on GPO
pins by appropriately setting the GPOxSEL bits in
control port registers 02h and 03h.

The encoded channel status bits which indicate
sample word length are decoded according to
AES3-1992 or IEC 60958. The number of auxiliary
bits are reported in bits 7 to 4 of the Receiver Chan-
nel Status register.

Appendix B describes the overall handling of
Channel Status and User data.

5.5

User Data Handling

Received User data may also be output to the U pin
under the control of a control register bit. VLRCK
(a virtual word clock, available through GPO pins,
that can used to frame the C/U output) and OLRCK
in serial port master mode can be made available to
qualify the U data output in software mode.

Figure 9

illustrates the timing. In hardware mode,

only OLRCK in master mode is available to qualify
the U output. If the incoming user data bits have
been encoded as Q- channel subcode, the data is de-
coded, buffered, and presented in 10 consecutive
register locations. An interrupt may be enabled to
indicate the decoding of a new Q-channel block,
which may be read through the control port.

5.5.1

Non-Audio Auto-Detection

An AES3 data stream may be used to convey non-
audio data, thus it is important to know whether the
incoming AES3 data stream is digital audio or not.
This information is typically conveyed in channel
status bit 1 (AUDIO), which is extracted automati-
cally by the CS8416. However, certain non-audio
sources, such as AC-3 or MPEG encoders, may not
adhere to this convention, and the bit may not be
properly set. The CS8416 AES3 receiver can detect
such non-audio data through the use of an autode-
tect module. The autodetect module is similar to

CS8416

DS578PP2

autodetect software used in Cirrus Logic DSPs. If
the AES3 stream contains sync codes in the proper
format for IEC61937 or DTS data transmission, an
internal AUTODETECT signal will be asserted. If
the sync codes no longer appear after a certain
amount of time, autodetection will time-out and
AUTODETECT will be de-asserted until another
format is detected. In Hardware Mode, the AUDIO
pin is the logical OR of AUTODETECT and the re-
ceived channel status bit 1. In Software mode the
AUDIO pin is available through the GPO pins. Al-
so, the specific data or audio format found by the

autodetect module is available in register 0Bh. Ad-
ditionally, the Pc/Pd burst preambles are available
in registers 23h-26h. If non-audio data is detected,
the data is still processed exactly as if it were nor-
mal audio. The exception is the use of de-emphasis
auto-select feature which will bypass the de-em-
phasis filter if the input stream is detected to be
non-audio. It is up to the user to mute the outputs as
required.

RCBL
out

VLRCK

C, U
Output

RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, available through GPO pins, that can used to frame the C/U ouput.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If the serial audio output port is in master mode, VLRCK = OLRCK.
C, U transitions are aligned within 1% of VLRCK period to VLRCK edges

Figure 9. C/U data outputs

Figure 10. De-emphasis filter

-10

3.183

Frequency,
KHz

T1 =
50us

10.61

Gain,
dB

T2
=15us

CS8416

DS578PP2

6 CONTROL PORT DESCRIPTION

AND TIMING

The control port is used to access the registers, al-
lowing the CS8416 to be configured for the desired
operational modes and formats. In addition, Chan-
nel Status and User data may be read through the
control port. The operation of the control port may
be completely asynchronous with respect to the au-
dio sample rates. However, to avoid potential inter-
ference problems, the control port pins should
remain static if no operation is required.

The control port has 2 modes: SPI and I

C, with the

CS8416 acting as a slave device in both modes. SPI
mode is selected if there is a high to low transition
on the AD0/CS pin, after the RST pin has been
brought high. I

C mode is selected by connecting

the AD0/CS pin to VL+ or DGND, thereby perma-
nently selecting the desired AD0 bit address state.

6.1

SPI Mode

In SPI mode, CS is the CS8416 chip select signal,
CCLK is the control port bit clock (input into the
CS8416 from the microcontroller), CDIN is the in-
put data line from the microcontroller, CDOUT is
the output data line to the microcontroller. Data is
clocked in on the rising edge of CCLK and out on
the falling edge.

Figure 11

shows the operation of the control port in

SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which should be low to write. The
next eight bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next eight bits are the data
which will be placed into the register designated by
the MAP. During writes, the CDOUT output stays
in the Hi-Z state. It may be externally pulled high
or low with a 47 K

resistor, if desired.

There is a MAP auto increment capability, enabled
by the INCR bit in the MAP register. If INCR is a
zero, the MAP will stay constant for successive
read or writes. If INCR is set to a 1, the MAP will
auto increment after each byte is read or written, al-
lowing block reads or writes of successive regis-
ters. In the autoincrement mode, the MAP is
incremented in a linear fashion. Allowance must be
made for unused registers.

To read a register, the MAP has to be set to the cor-
rect address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The MAP auto increment bit (INCR)
may be set or not, as desired. To begin a read, bring
CS low, send out the chip address and set the

M A P

MSB

LSB

DATA

b y te 1

b y te n

R/W

A D D R E S S

C H IP

ADDRESS

C H IP

C D IN

C C L K

C D O U T

MSB

LSB MSB

LSB

0010000

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 11. Control Port Timing In SPI Mode

CS8416

DS578PP2

read/write bit (R/W) high. The next falling edge of
CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.

The auto increment function is strictly linear. This
may result in operations on undefined registers.
Reads from undefined registers will produce inde-
terminate results. Writing to undefined registers
will be ignored.

6.2

C Mode

In I

C mode, SDA is a bidirectional data line. Data

is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in

Figure 12

. There is no CS pin. Each individual

CS8416 is given a unique address. Pins AD0 and
AD1 form the two least significant bits of the chip
address and should be connected to VL+ or DGND

as desired. The GPO2 pin is used to set the AD2 bit
by connecting a 47K resistor from the GPO2 pin to
VL+ or to DGND. The state of the pin is sensed
while the CS8416 is being reset. The upper 4 bits of
the 7-bit address field are fixed at 0010. To com-
municate with a CS8416, the chip address field,
which is the first byte sent to the CS8416, should
match 0010 followed by the settings of the GPO2,
AD1, and AD0. The eighth bit of the address is the
R/W bit. If the operation is a write, the next byte is
the Memory Address Pointer (MAP) which selects
the register to be read or written. If the operation is
a read, the contents of the register pointed to by the
MAP will be output. Setting the auto increment bit
in MAP allows successive reads or writes of con-
secutive registers. Each byte is separated by an ac-
knowledge bit. The ACK bit is output from the
CS8416 after each input byte is read, and is input to
the CS8416 from the microcontroller after each
transmitted byte.

SDA

SCL

0010

AD2-0

R/W

Start

ACK

DATA7-0

ACK

DATA7-0

ACK

Stop

Note 2

Note 1

Note 3

Figure 12. Control Port Timing in I

C Mode

Notes: 1. AD2 is derived from a resistor attached to the

GPO2

pin.

AD1 and AD0 are determined by the state of the corresponding pins.

2. If operation is a write, this byte contains the Memory Address Pointer, MAP.
3. If operation is a read, the last bit of the read should be NACK (high).

CS8416

DS578PP2

6.3

General Purpose Outputs

Three General Purpose outputs are provided to allow the equipment designer flexibility in configuring the
CS8416.

Fourteen signals are available to be routed to the GPOs.

GPO pins may be configured to provide the following data:

Notes: 13. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ F

= 48 kHz.

6.4

Interrupts

The CS8416 has a comprehensive interrupt capa-
bility. The INT pin may be set to be active low, ac-
tive high or active low with no active pull-up
transistor. This last mode is used for active low,
wired-OR hook- ups, with multiple peripherals
connected to the microcontroller interrupt input
pin.

Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off through mask register
bits. In addition, each source may be set to rising
edge, falling edge, or level sensitive. Combined
with the option of level sensitive or edge sensitive
modes within the microcontroller, many different
configurations are possible, depending on the
needs of the equipment designer.

Function

Code

Definition

0000

AES/SPDIF input selected by TXSEL[2:0]

EMPH

0001

State of EMPH bit in incoming stream. Same polarity as EMPHb bit.

INT

0010

CS8416 interrupt

0011

Channel status bit

0100

User data bit

RERR

0101

Receiver Error

NVERR

0110

Non-Validity Receiver Error

RCBL

0111

Receiver Channel Status Block

96KHZ

1000

Input F

88.1

AUDIO

1001

Non-audio indicator for decoded input stream

VLRCK

1010

Virtual LRCK

GND

1011

Fixed low Level

VDD

1100

VDD fixed high level

HRMCK

1101

X 512 (

Note 13

)

Codes 1110 to 1111 - Reserved

Table 3. GPO Pin Configurations

CS8416

DS578PP2

7 CONTROL PORT REGISTER SUMMARY

Addr (HEX)

R/W

Function

R/W

Control 0

TRUNC

Reserved Reserved

R/W

Control1

SWCLK

MUTSAO

INT1

INT0

HOLD1

HOLD0

RMCKF

CHS

R/W

Control2

DETCI

EMPH_C

NTL2

EMPH_C

NTL1

EMPH_C

NTL0

GPO0SE

R/W

Control3

GPO1SE

GPO2SE

R/W

Control4

RUN

RXD

RXSEL2

RXSEL1

RXSEL0

TXSEL2

TXSEL1

TXSEL0

R/W

Serial Audio Data Format

SOMS

SOSF

SORES1

SORES0

SOJUST

SODEL

SOSPOL

SOLR-

POL

R/W

Receiver Error Mask

QCRCM

CCRCM

UNLOCK

CONFM

BIPM

PARM

R/W

Interrupt Mask

PCCHM

OSLIPM

DETCM

CCHM

RERRM

QCHM

FCHM

R/W

Interrupt Mode MSB

PCCH1

OSLIP1

DETC1

CCH1

RERR1

QCH1

FCH1

R/W

Interrupt Mode LSB

PCCH0

OSLIP0

DETC0

CCH0

RERR0

QCH0

FCH0

Receiver Channel Status

AUX3

AUX2

AUX1

AUX0

PRO

COPY

ORIG

EMPH

Audio Format Detect

PCM

IEC61937

DTS_LD

DTS_CD

Reserved

DGTL_SI

96KHZ

Receiver Error

QCRC

CCRC

UNLOCK

CONF

BIP

PAR

Interrupt Status

PCCH

OSLIP

DETC

CCH

RERR

QCH

FCH

Q-Channel Subcode

[0:7]

CON-

TROL

CON-

TROL

CON-

TROL

CON-

TROL

ADDRES

[8:15]

TRACK

[16:23]

INDEX

[24:31]

MINUTE

[32:39]

SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND

[40:47]

FRAME

[48:55]

ZERO

[56:63]

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

ABS

MINUTE

[64:71]

ABS SEC-

OND

ABS SEC-

OND

ABS SEC-

OND

ABS SEC-

OND

ABS SEC-

OND

ABS SEC-

OND

ABS SEC-

OND

ABS SEC-

OND

[72:79]

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

ABS

FRAME

OMCK_RMCK Ratio

ORR7

ORR6

ORR5

ORR4

ORR3

ORR2

ORR1

ORR0

Channel A Status

AC0[7]

AC0[6]

AC0[5]

AC0[4]

AC0[3]

AC0[2]

AC0[1]

AC0[0]

Channel A Status

AC1[7]

AC1[6]

AC1[5]

AC1[4]

AC1[3]

AC1[2]

AC1[1]

AC1[0]

Channel A Status

AC2[7]

AC2[6]

AC2[5]

AC2[4]

AC2[3]

AC2[2]

AC2[1]

AC2[0]

Channel A Status

AC3[7]

AC3[6]

AC3[5]

AC3[4]

AC3[3]

AC3[2]

AC3[1]

AC3[0]

Channel A Status

AC4[7]

AC4[6]

AC4[5]

AC4[4]

AC4[3]

AC4[2]

AC4[1]

AC4[0]

Channel B Status

BC0[7]

BC0[6]

BC0[5]

BC0[4]

BC0[3]

BC0[2]

BC0[1]

BC0[0]

Channel B Status

BC1[7]

BC1[6]

BC1[5]

BC1[4]

BC1[3]

BC1[2]

BC1[1]

BC1[0]

Channel B Status

BC2[7]

BC2[6]

BC2[5]

BC2[4]

BC2[3]

BC2[2]

BC2[1]

BC2[0]

Channel B Status

BC3[7]

BC3[6]

BC3[5]

BC3[4]

BC3[3]

BC3[2]

BC3[1]

BC3[0]

Channel B Status

BC4[7]

BC4[6]

BC4[5]

BC4[4]

BC4[3]

BC4[2]

BC4[1]

BC4[0]

Burst Preamble PC Byte 0

PC0[7]

PC0[6]

PC0[5]

PC0[4]

PC0[3]

PC0[2]

PC0[1]

PC0[0]

CS8416

DS578PP2

INT[1:0] - Interrupt output pin (INT) control

Default = `00'

00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Thus it is not recom-

mended to multiplex INT onto GPO2 in I

C control port mode since an external resistor is re-

quired on GPO2 to specify the AD2 bit of the chip address.

11 Reserved

CHS Sets which channel's C data is decoded in the Receiver Channel Status register

0 A channel

1 B channel

8.3

Control2 (02h)

DETCI D to E status transfer inhibit

Default = `0'

0 Allow update

1 Inhibit update

Emph_CNTL[2:0] De-emphasis filter control

Default = 000

000 De-emphasis filter off

001 32 KHz setting

010 44.1 KHz setting

011 48 KHz

100 50us/15us de-emphasis filter auto-select on. Coefficients(32, 44.1 or 48 KHz or no de-empha-
sis filter at all) match the pre-emphasis and sample frequency indicators in the channel status bits of
Channel A. Thus it is impossible to have de-emphasis applied to one channel but not the other. Also
it turns off the de-emphasis filter if the audio data is detected to be non-linear data.

GPO0SEL[3:0]  GPO0 Source select. See GPO section in main text for settings table.

Default = 0000

8.4

Control3 (03h)

DETCI

EMPH_CNTL2 EMPH_CNTL1 EMPH_CNTL0

GPO0SEL3

GPO0SEL2

GPO0SEL1

GPO0SEL0

GPO1SEL3

GPO1SEL2

GPO1SEL1

GPO1SEL0

GPO2SEL3

GPO2SEL2

GPO2SEL1

GPO2SEL0

CS8416

DS578PP2

8.7

Receiver Error Mask (06h)

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a
mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver
error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio
sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning
that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not
affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits
behave differently from the other bits: they do not affect the current audio sample even when un-
masked. This register defaults to 00h.

8.8

Interrupt Mask (07h)

The bits of this register serve as a mask for the

Interrupt Status register

. If a mask bit is set to 1, the

error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask
bit is set to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal
or the status register. The bit positions align with the corresponding bits in

Interrupt Status register

This register defaults to 00h.

The INT signal may be selected to appear on the GPO pins.

8.9

Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)

The two Interrupt Mode registers form a 2-bit code for each

Interrupt Status register

function. There

are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge
active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge
active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active
mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active
level(Active High or Low) only depends on the INT[1:0] bits. These registers default to 00h.

00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved

QCRCM

CCRCM

UNLOCKM

CONFM

BIPM

PARM

PCCHM

OSLIPM

DETCM

CCHM

RERRM

QCHM

FCHM

PCCH1

OSLIP1

DETC1

CCH1

RERR1

QCH1

FCH1

PCCH0

OSLIP0

DETC0

CCH0

RERR0

QCH0

FCH0

CS8416

DS578PP2

8.10

Receiver Channel Status (0Ah)

The bits in this register can be associated with either channel A or B of the received data. The desired
channel is selected with the CHS bit of the Control1 register.

AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, de-
coded according to IEC60958 and AES3.

0000 - Auxiliary data is not present
0001 - Auxiliary data is 1 bit long
0010 - Auxiliary data is 2 bits long
0011 - Auxiliary data is 3 bits long
0100 - Auxiliary data is 4 bits long
0101 - Auxiliary data is 5 bits long
0110 - Auxiliary data is 6 bits long
0111 - Auxiliary data is 7 bits long
1000 - Auxiliary data is 8 bits long
1001 - 1111 Reserved

PRO - Channel status block format indicator

0 - Received channel status block is in consumer format
1 - Received channel status block is in professional format

COPY - SCMS copyright indicator

0 - Copyright asserted
1 - Copyright not asserted If the category code is set to General in the incoming AES3 stream, copy-
right will always be indicated by COPY, even when the stream indicates no copyright.

ORIG - SCMS generation indicator, decoded from the category code and the L bit.

0 - Received data is 1st generation or higher
1 - Received data is original
Note: COPY and ORIG will both be set to 1 if incoming data is flagged as professional or if the receiver
is not in use.

EMPH Indicates whether the input audio data has been pre-emphasized. Also indicates turning
on of the de-emphasis filter during de-emphasis auto-select mode.

0 50us/15us pre-emphasis indicated
1 50us/15us pre-emphasis not indicated

8.11

Format Detect Status (0Bh)

Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive.

PCM Uncompressed PCM data was detected

IEC61937 IEC61937 data was detected

DTS_LD DTS_LD data was detected

AUX3

AUX2

AUX1

AUX0

PRO

COPY

ORIG

EMPH

PCM

IEC61937

DTS_LD

DTS_CD

Reserved

DGTL_SIL

96KHZ

CS8416

DS578PP2

DTS_CD DTS_CD data was detected

Reserved This bit may change state depending on the input audio data.

DGTL_SIL Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bit

audio data on both channels.

96KHZ if input sample rate is

48 KHz, outputs a "0". Outputs a "1" if the sample rate is 88.1 KHz.

Otherwise output indeterminate.

8.12

Receiver Error (0Ch)

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occur-
rence of the error, and will stay high until the register is read. Reading the register resets all bits to 0,
unless the error source is still true. Bits that are masked off in the receiver error mask register will
always be 0 in this register.

QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries

0 - No error
1 - Error

CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries,
valid in Pro mode

0 - No error
1 - Error

UNLOCK - PLL lock status bit. Updated on CS block boundaries.

0 - PLL locked
1 - PLL out of lock

V - Received AES3 Validity bit status. Updated on sub-frame boundaries.

0 - Data is valid and is normally linear coded PCM audio
1 - Data is invalid, or may be valid compressed audio

CONF - Confidence bit. Updated on sub-frame boundaries.

0 - No error
1 - Confidence error. This indicates that the received data eye opening is less than half a bit period,
indicating a poor link that is not meeting specifications.

BIP - Bi-phase error bit. Updated on sub-frame boundaries.

0 - No error
1 - Bi-phase error. This indicates an error in the received bi-phase coding.

PAR - Parity bit. Updated on sub-frame boundaries.

0 - No error
1 - Parity error

QCRC

CCRC

UNLOCK

CONF

BIP

PAR

CS8416

DS578PP2

8.13

Interrupt 1 Status (0Dh)

For all bits in this register, a "1" means the associated interrupt condition has occurred at least once
since the register was last read. A "0" means the associated interrupt condition has NOT occurred
since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode
is set to level and the interrupt source is still true. Status bits that are masked off in the associated
mask register will always be "0" in this register.

PCCH PC burst preamble change.

Indicates that the PC byte has changed from its previous value. The user has TBD frames to read
new value before it can potentially be overwritten again. If the IEC61937 bit in the Format Detect Sta-
tus register goes high, it will cause a PCCH interrupt even if the PC byte hasn't changed since the last
time the IEC61937 bit went high.

OSLIP - Serial audio output port data slip interrupt

When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data
source, This bit will go high every time a data sample is dropped or repeated.

DETC - D to E C-buffer transfer interrupt.

The source for this bit is true during the D to E buffer transfer in the C bit buffer management process.

C_CHANGE -Indicates that the current 10 bytes of channel status is different from the previous

10 bytes. (5 bytes per channel)

RERR - A receiver error has occurred.

The Receiver Error register may be read to determine the nature of the error which caused the inter-
rupt.

QCH A new block of Q-subcode is available for reading. The data must be read within 588 AES3

frames after the interrupt occurs to avoid corruption of the data by the next block.

FCH  Format Change: Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL

bits in the Format Detect Status register transition from 0 to 1. When these bits in the Format
Detect Status register transition from 1 to 0, an interrupt will not be generated.

8.14

Q-Channel Subcode (0Eh - 17h)

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 0Eh is Q[0]
while bit 0 of address 0Eh is Q[7]. Similarly bit 0 of address 17h corresponds to Q[79].

PCCH

OSLIP

DETC

CCH

RERR

QCH

FCH

CONTROL

ADDRESS

TRACK

INDEX

MINUTE

SECOND

FRAME

ZERO

ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE

ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND

ABS FRAME

CS8416

DS578PP2

8.15

OMCK/RMCK Ratio (18h)

This register allows the calculation of the incoming sample rate by the host microcontroller from the
equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256
Fso. ORR is represented as an unsigned 2-bit integer and a 6-bit fractional part. The value is mean-
ingful only after the PLL has reached lock. For example, if the OMCK is 12.288MHz, Fso would be
48KHz (48KHz = 12.288MHz/256). Then if the input sample rate is also 48KHz, you would get 1.0
from the ORR register.(The value from the ORR register is hexadecimal, so the actual value you will
get is 40h). If F

, ORR will saturate at the value FFh. Also, there is no hysteresis on

ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.

ORR[7:6] - Integer part of the ratio (Integer value=Integer(SRR[7:6]))

ORR[5:0] - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)

8.16

Channel Status Registers (19h - 22h)

8.17

IEC61937 PC/PD Burst preamble (23h - 26h)

8.18

CS8416 I.D. and Version Register (7Fh)

ID[3:0]= 0010

VER[3:0] = 0001 (revision A)

ORR7

ORR6

ORR5

ORR4

ORR3

ORR2

ORR1

ORR0

Channel A Status Byte 0

AC0[7]

AC0[6]

AC0[5]

AC0[4]

AC0[3]

AC0[2]

AC0[1]

AC0[0]

Channel A Status Byte 1

AC1[7]

AC1[6]

AC1[5]

AC1[4]

AC1[3]

AC1[2]

AC1[1]

AC1[0]

Channel A Status Byte 2

AC2[7]

AC2[6]

AC2[5]

AC2[4]

AC2[3]

AC2[2]

AC2[1]

AC2[0]

Channel A Status Byte 3

AC3[7]

AC3[6]

AC3[5]

AC3[4]

AC3[3]

AC3[2]

AC3[1]

AC3[0]

Channel A Status Byte 4

AC4[7]

AC4[6]

AC4[5]

AC4[4]

AC4[3]

AC4[2]

AC4[1]

AC4[0]

Channel B Status Byte 0

BC0[7]

BC0[6]

BC0[5]

BC0[4]

BC0[3]

BC0[2]

BC0[1]

BC0[0]

Channel B Status Byte 1

BC1[7]

BC1[6]

BC1[5]

BC1[4]

BC1[3]

BC1[2]

BC1[1]

BC1[0]

Channel B Status Byte 2

BC2[7]

BC2[6]

BC2[5]

BC2[4]

BC2[3]

BC2[2]

BC2[1]

BC2[0]

Channel B Status Byte 3

BC3[7]

BC3[6]

BC3[5]

BC3[4]

BC3[3]

BC3[2]

BC3[1]

BC3[0]

Channel B Status Byte 4

BC4[7]

BC4[6]

BC4[5]

BC4[4]

BC4[3]

BC4[2]

BC4[1]

BC4[0]

Burst Preamble PC Byte 0

PC0[7]

PC0[6]

PC0[5]

PC0[4]

PC0[3]

PC0[2]

PC0[1]

PC0[0]

Burst Preamble PC Byte 1

PC1[7]

PC1[6]

PC1[5]

PC0[4]

PC1[3]

PC1[2]

PC1[1]

PC1[0]

Burst Preamble PD Byte 0

PD0[7]

PD0[6]

PD0[5]

PC0[4]

PD0[3]

PD0[2]

PD0[1]

PD0[0]

Burst Preamble PD Byte 1

PD1[7]

PD1[6]

PD1[5]

PD1[4]

PD1[3]

PD1[2]

PD1[1]

PD1[0]

ID3

ID2

ID1

ID0

VER3

VER2

VER1

VER0

CS8416

DS578PP2

9. PIN DESCRIPTION - SOFTWARE MODE

RXP3

RXP2

RXP1

RXP0

RXN

VA+

AGND

FILT

RST

RXP4

RXP5

RXP6

RXP7

AD0/CS

OLRCK

OSCLK

SDOUT

OMCK

RMCK

VD+

DGND

VL+

GPO0

GPO1

AD2/GPO2

SDA/CDOUT

SCL/CCLK

AD1/CDIN

RXP[7:0]

RXN

13
12

1
2
3
4

Additional AES3/SPDIF Receiver Port

(Input) - Single-ended receiver inputs carrying AES3 or

S/PDIF digital data. These inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is
accessed using the Control 4 register. Please note that any unused inputs can be left floating or tied to
ground. See Appendix A for recommended input circuits.

AES/SPDIF input

- Used along with RXP[X] to form an AES3 differential input. In single-ended

operation this should be capacitively coupled to ground.

VA+

VD+

VL+

Positive Analog Power

- Positive supply for the analog section. Nominally +3.3 V. This supply should

be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered
clock

Positive Digital Power

Nominally 3.3 V

Positive Interface Power

3.3 V to 5.0 V: this supply sets the CS8416 I/O levels, including RXPx &

RXN

AGND

DGND

Analog Ground

- Ground for the analog circuitry in the chip. AGND and DGND should be con nected

to a common ground area under the chip.

Digital & I/O Ground

FILT

PLL Loop Filter

(Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND

CS8416

DS578PP2

RST

Reset

(Input) - When RST is low, the CS8416 enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase.

AD0/CS

Address Bit 0 (I

C) / Control Port Chip Select (SPI)

(Input) - A falling edge on this pin puts the

CS8416 into SPI control port mode. With no falling edge, the CS8416 defaults to I

C mode. In I

mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the
CS8416

AD1/CDIN

Address Bit 1 (I

C) / Serial Control Data in (SPI)

(Input) - In I

C mode, AD1 is a chip address pin. In

SPI mode, CDIN is the input data line for the control port interface

SCL/CCLK

Control Port Clock

(Input) - Serial control interface clock and is used to clock control data bits into and

out of the CS8416.

SDA/
CDOUT

Serial Control Data I/O (I

C) / Data Out (SPI)

(Input/Output) - In I

C mode, SDA is the control I/O data

line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the
output data from the control port interface on the CS8416

AD2/GPO2

General Purpose Output 2 (Output)

- If using the I

C control port, this pin must be pulled high or low

through a 47 k

resistor. See

"General Purpose Outputs" on page 22

for GPO functions.

GPO1

General Purpose Output 1 (Output)

See

"General Purpose Outputs" on page 22

for GPO functions.

GPO0

General Purpose Output 0 (Output)

See

"General Purpose Outputs" on page 22

for GPO functions.

SDOUT

Serial Audio Output Data

(Output) - Audio data serial output pin. This pin must be pulled high to VL+

through a 47 K

resistor to place the part in Software Mode.

OLRCK

Serial Audio Output Left/Right Clock

(Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

OSCLK

Serial Audio Output Bit Clock

(Input/Output) - Serial bit clock for audio data on the SDOUT pin

OMCK

System Clock

(Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the

Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as
reference signal for OMCK/RMCK ratio expressed in register 24

RMCK

Input Section Recovered Master Clock

(Output) - Input section recovered master clock output when

PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x. It may also be
tri-stated by the RXD bit in the Control 4 register (04h).

CS8416

DS578PP2

10 HARDWARE MODE

The CS8416 has a hardware mode which allows using the device without a microcontroller. Hardware
mode is selected by connecting the 47K pull-up/down resistor on the SDOUT pin to ground. Various pins
change function in hardware mode, described in the hardware mode pin definition section (Section 11).

Hardware mode data flow is shown in

Figure 13

. Audio data is input through the AES3/SPDIF receiver,

and routed to the serial audio output port. The decoded C and U bits are also output, clocked at both edges
of OLRCK (master mode only, see

Figure 9

An error in the incoming audio stream will be indicated on the NV/RERR. This pin can be configured in
one of two ways. If RERR is chosen by pulling NV/RERR to ground, the previous audio sample is held
and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or PLL
lock error occurs during the current sample. If NVERR is chosen by pulling NV/RERR to VL+, only par-
ity, bi-phase, confidence or PLL lock error cause the previous audio sample to be held.

10.1

Serial Audio Port Formats

In hardware mode, only a limited number of alternative serial audio port formats are available.

Table 4

de-

fines the equivalent software mode bit settings for each format.

The start-up options, shown in

Table 4

, allow choice of the serial audio output port as a master or slave,

and the serial audio port format.

NV/RERR

Power supply pins (VA+, VD+, VL+, AGND, DGND, the reset pin (RST) and the PLL filter pin (FILT)
are omitted from the diagram. Please refer to the Typical Connection Diagram for connection details.

RXP1

4:2

MUX

RXP2

RXP3

RXP0

96kHz

RMCK

RXSEL[1:0]

TXSEL[1:0]

AUDIO

RCBL

RXN

AES3 Rx

Decoder

OMCK

OLRCK
OSCLK
SDOUT

C
U

De-emphasis

Filter

Serial
Audio

Output

Figure 13. Hardware Mode Data Flow

CS8416

DS578PP2

11 PIN DESCRIPTION - HARDWARE MODE

RXP3

RXP2

RXP1

RXP0

RXN

VA+

AGND

FILT

RST

RXSEL1

RXSEL0

TXSEL1

TXSEL0

NV/RERR

OLRCK

OSCLK

SDOUT

OMCK

RMCK

VD+

DGND

VL+

RCBL

96 KHZ

AUDIO

RXP[3:0]

RXN

1
2
3
4

Additional AES3/SPDIF Receiver Port

(Input) - Single-ended receiver inputs carrying AES3 or

S/PDIF digital data. These inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is
the RXSEL[1:0] pins. Please note that any unused inputs can be left floating. See Appendix A for rec-
ommended input circuits.

AES/SPDIF Input -

Used along with RXP[X] to form an AES3 differential input. In single-ended

operation this should be capacitively coupled to ground.

VD+

VA+

VL+

Positive Digital Power

3.3 V

Positive Analog Power 

3.3 V

Positive Interface Power 

3.3 V 5.0 V

DGND

AGND

Digital/Interface Ground

Analog Ground

RX_SEL0
RX_SEL1

Receiver_MUX Selector (Input)

- used to select which pin, RXP[3:0], is used for the receiver

input.

TX_SEL0
TX_SEL1

12
13

TX Pin MUX SELECTION(Input)

- used to select which pin, RXP[3:0], is used for the TX pin

output.

FILT

PLL Filter Pin 

A RC network should be connected from this pin to AGND. For best PLL jitter

performance, this pin should be returned directly to the AGND pin

RST

RESET(Input)

active low input . Resets CS8416 to default state, configuration pins are read on the

rising edge of this pin

NV/RERR

Non-Validity Receiver Error/Receiver Error (output)

CS8416

DS578PP2

AUDIO

Audio Channel Status Bit(output)

When low, a valid linear PCM audio stream is indicated.

96KHZ

96 khz Sample Rate Detect(output)

if input sample rate is

48 KHz, ouputs a "0". Outputs a "1" if

the sample rate is

88.1 KHz. Otherwise output indeterminate.

RCBL

Receiver Channel Status Block

(

Output

) -

Indicates the beginning of a received channel status

block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames
and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK.

User Data

(Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling

edges of OLRCK.

Channel Status Data

(Output) - Outputs channel status data from the AES3 receiver, clocked by the

ris ing and falling edges of OLRCK.

S/PDIF MUX Pass through

(Output)

SDOUT

Serial Audio Output Data

(Output) - Audio data serial output pin. This pin must be pulled to low to

DGND through a 47 K

resistor.

OLRCK

Serial Audio Output Left/Right Clock

(Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs).

OSCLK

Serial Audio Output Bit Clock

(Input/Output) - Serial bit clock for audio data on the SDOUT pin.

OMCK

System Clock

(Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the

Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as
reference signal for OMCK/RMCK ratio expressed in register 24

RMCK

Recovered Master Clock

(Output) - Recovered master clock output when PLL is locked to the

incoming AES3 stream. Frequency is 128/256x the sample rate (Fs).

CS8416

DS578PP2

12 APPLICATIONS

12.1

Reset, Power Down and Start-up

When RST is low, the CS8416 enters a low power
mode and all internal states are reset, including the
control port and registers, and the outputs are mut-
ed. In Software Mode, when RST is high, the con-
trol port becomes operational and the desired
settings should be loaded into the control registers.
Writing a 1 to the RUN bit will then cause the part
to leave the low power state and begin operation.
After the PLL has settled, the serial audio outputs
will be enabled.

Some options within the CS8416 are controlled by
a start-up mechanism. During the reset state, some
of the pins are reconfigured internally to be inputs.
Immediately upon exiting the reset state, the level
of these pins is sensed. The pins are then switched
to be outputs. This mechanism allows output pins
to be used to set alternative modes in the CS8416
by connecting a 47K resistor to between the pin and
either VL+ (HI) or DGND (LO). For each mode,
every start-up option select pin MUST have an ex-
ternal pull-up or pull-down resistor. In software
mode, the only start-up option pins are GPO2,
which are used to set a chip address bit for the con-
trol port in I

C mode, and SDOUT, which selects

between Hardware and Software Modes. The hard-
ware mode uses many start-up options, which are
detailed in the hardware definition section at the
end of this data sheet.

12.2

ID Code and Revision Code

The CS8416 has a register that contains a 4-bit
code to indicate that the addressed device is a

CS8416. This is useful when other CS84XX
family members are resident in the same system,
allowing common software modules.

The CS8416 4-bit revision code is also available.
This allows the software driver for the CS8416 to
identify which revision of the device is in a
particular

system,

and

modify

its

behavior

accordingly. To allow for future revisions, it is
strongly recommend that the revision code is read
into a variable area within the microcontroller, and
used wherever appropriate as revision details
become known.

12.3

Power Supply, Grounding, and PCB
layout

For most applications, the CS8416 can be operated
from a single +3.3 V supply, following normal
supply decoupling practices. (See

Figure 5

and

Figure 6

). For applications where the recovered

input clock, output on the RMCK pin, is required
to be low jitter, then use a separate, quiet, analog
+3.3 V supply for VA+, decoupled to AGND. In
addition, a separate region of analog ground plane
around the FILT, AGND, VA+, RXP0-7 and RXN
pins is recommended. VL+ sets the level for the
digital

inputs and outputs, as well as the

AES/SPDIF inputs.

Extensive use of power and ground planes, ground
plane fill in unused areas and surface mount decou-
pling capacitors are recommended. Decoupling ca-
pacitors should be mounted on the same side of the
board as the CS8416 to minimize inductance ef-
fects, and all decoupling capacitors should be as
close to the CS8416 as possible. Refer to AN159
for examples of proper techniques.

CS8416

DS578PP2

14 APPENDIX A: EXTERNAL

AES3/SPDIF/IEC60958 RECEIVER
COMPONENTS

14.1

AES3 Receiver External Components

The CS8416 AES3 receiver is designed to accept
both the professional and consumer interfaces. The
digital audio specifications for professional use call
for a balanced receiver, using XLR connectors,
with 110

±20% impedance. The XLR connector

on the receiver should have female pins with a male
shell. Since the receiver has a very high input im-
pedance, a 110

resistor should be placed across

the receiver terminals to match the line impedance,
as shown in

Figure 14

and

Figure 15

. Although

transformers are not required by the AES, they are,
however, strongly recommended.

If some isolation is desired without the use of trans-
formers, a 0.01

µF capacitor should be placed in se-

ries with each input pin (RXP0 and RXN0) as
shown in Figure . However, if a transformer is not
used, high frequency energy could be coupled into
the receiver, causing degradation in analog perfor-
mance.

Figure 14

and

Figure 15

show an optional DC

blocking capacitor (0.1

µF to 0.47 µF) in series with

the cable input. This improves the robustness of the
receiver, preventing the saturation of the trans-
former, or any DC current flow, if a DC voltage is
present on the cable.

In the configuration of systems, it is important to
avoid ground loops and DC current flowing down
the shield of the cable that could result when boxes
with different ground potentials are connected.
Generally, it is good practice to ground the shield
to the chassis of the transmitting unit, and connect
the shield through a capacitor to chassis ground at
the receiver. However, in some cases it is advanta-
geous to have the ground of two boxes held to the
same potential, and the cable shield might be de-
pended upon to make that electrical connection.
Generally, it may be a good idea to provide the op-
tion of grounding or capacitively coupling the
shield to the chassis.

In the case of the consumer interface, the standards
call for an unbalanced circuit having a receiver im-
pedance of 75

±5%. The connector for the con-

sumer interface is an RCA phono socket. The
receiver circuit for the consumer interface is shown
in Figure .

Figure

shows an implementation of the

Input S/PDIF Multiplexer using the consumer in-
terface.

The circuit shown in

Figure

may be used when ex-

ternal RS422 receivers, optical receivers or other
TTL/CMOS logic outputs drive the CS8416 receiv-
er section.

14.2

Isolating Transformer Requirements

Please refer to the application note AN134: AES
and SPDIF Recommended Transformers for re-
sources on transformer selection.

CS8416

DS578PP2

15 APPENDIX B: CHANNEL STATUS

BUFFER MANAGEMENT

15.1

AES3 Channel Status (C) Bit
Management

The CS8416 contains sufficient RAM to store the
first 5 bytes of C data for both A and B channels
(5 x 2 x 8 = 80 bits). The user may read from this
buffer's RAM through the control port.

The buffering scheme involves 2 80-bit buffers,
named D and E, as shown in

Figure 19

. The MSB

of each byte represents the first bit in the serial C
data stream. For example, the MSB of byte 0
(which is at control port address 32) is the consum-
er/professional bit for channel status block A.

The first buffer (D) accepts incoming C data from
the AES receiver. The 2nd buffer (E) accepts entire
blocks of data from the D buffer. The E buffer is
also accessible from the control port, allowing
reading of the C data.

15.2

Accessing the E buffer

The user can monitor the incoming data by reading
the E buffer, which is mapped into the register
space of the CS8416, through the control port.

The user can configure the interrupt enable register
to cause interrupts to occur whenever D to E buffer

transfers occur. This allows determination of the al-
lowable time periods to interact with the E buffer.

Also provided is a D to E inhibit bit. This may be
used whenever "long" control port interactions are
occurring.

A flowchart for reading the E buffer is shown in

Figure 20

. Since a D to E interrupt just occurred af-

ter reading, there is a substantial time interval until
the next D to E transfer (approximately 192 frames
worth of time). This is usually plenty of time to ac-
cess the E data without having to inhibit the next
transfer.

15.2.1

Serial Copy Management System
(SCMS)

In software mode, the CS8416 allows read access
to all the channel status bits. For consumer mode
SCMS compliance, the host microcontroller needs
to read and interpret the Category Code, Copy bit
and L bit appropriately.

In hardware mode, the SCMS protocol can be fol-
lowed by either using the COPY and ORIG output
pins, or by using the C bit serial output pin. These
options are documented in the hardware mode sec-
tion of this data sheet.

Control Port

From
AES3
Receiver

words

8-bits

Received
Data
Buffer

Figure 19. Channel Status Data Buffer Structure

D to E interrupt occurs

Optionally set D to E inhibit

Read E data

If set, clear D to E inhibit

Return

Figure 20. Flowchart for Reading the E Buffer

Part Number CS8416

Document Outline