Copyright

Cirrus Logic, Inc. 2005

http://www.cirrus.com

Advanced Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

114 dB, 192 kHz, 8-Channel A/D Converter

Overall Features

Advanced Multi-bit Delta-Sigma Architecture

24-Bit Conversion

114 dB Dynamic Range

-105 dB THD+N

Supports Audio Sample Rates up to 216 kHz

Selectable Audio Interface Formats

Left-Justified, I²S, TDM
8-channel TDM Interface Formats

Low Latency Digital Filter

Less than 600 mW Power Consumption

On-Chip Oscillator Driver

Operation as System Clock Master or Slave

Differential Analog Architecture

Separate 1.8 V to 5 V Logic Supplie s for

Control and Serial Ports

High-Pass Filter for DC Offset Calibration

Overflow Detection

Pin-Compatible with the 4-Channel CS5364

and 6-Channel CS5366

Additional Control Port Features

Supports Standard I²C or SPI Control Interface

Individual Channel HPF Disable

Overflow Detection for Individual Channels

Mute Control for Individual Channels

Independent Power-Down Control per Channel

Pair

Digital
Audio

Internal

Oscillator

Lev

r
ans

l
a

t
o

Lev

r
ans

l
a

t
o

Voltage

Reference

3.3 - 5V

Control Interface

C, SPI

or Pins

Configuration

Registers

VLC

1.8 - 5V

VLS

1.8 - 5V

8 Differential

Analog Inputs

Device
Control

Decimation

Filter

High Pass

Filter

Serial

Audio Out

PCM or

TDM

V A

Multi-Bit

ADC

JULY '05

DS624A1

CS5368

DS624A1

CS5368

Description

The CS5368 is a complete 8-channel analog-to-digital converter for digital audio systems. It performs sampling, an-
alog-to-digital conversion and anti-alias filtering, generating 24-bit values for all 8-channel inputs in serial form at
sample rates up to 216 kHz per channel.

The CS5368 uses a 5th-order, multi-bit delta sigma modulator followed by low latency digital filtering and decima-
tion, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which
provides excellent noise rejection.

Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5368 and
other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking
flexibility and simplifies design.

The CS5368 is the industry's first audio A/D to support a high-speed TDM interface which provides a serial output
of 8 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout
complexity and relieves input/output constraints in digital signal processors.

The CS5368 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion,
wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel record-
ers, outboard converters, digital effect processors, and automotive audio systems.

ORDERING INFORMATION

Product

Description

Package Pb-Free

Grade

Temp Range Container

Order #

CS5368

114 dB, 192 kHz,

8-channel A/D Con-

verter

48-pin

LQFP

YES

Commercial -10°

+85°C

Tray

CS5368-CQZ

Tape & Reel

CS5368-CQZR

Automotive

-40° to +85°C

Tray

CS5368-DQZ

Tape & Reel

CS5368-DQZR

CDB5368

Evaluation Board for CS5368

CDB5368

DS624A1

CS5368

TABLE OF CONTENTS

1. PIN DESCRIPTION ...................................................................................................... 9

2. CHARACTERISTICS AND SPECIFICATIONS.......................................................... 13

Specified Operating Conditions .............................................................................................. 13
Absolute Ratings .................................................................................................................... 13
System Clocking ..................................................................................................................... 13
Thermal Characteristics.......................................................................................................... 13
DC Power CS5368 ................................................................................................................. 14
Logic Levels ........................................................................................................................... 14
PSRR, Vq and FILT+ Characteristics ..................................................................................... 14
Analog Performance (CS5368-CQZ)...................................................................................... 15
Analog Performance (CS5368-DQZ)...................................................................................... 16
Digital Filter Characteristics ................................................................................................... 17
Serial Audio Interface - I²S/LJ Timing ..................................................................................... 18
Serial Audio Interface - TDM Timing....................................................................................... 19
Overflow Timeout ................................................................................................................... 19
Switching Specifications - Control Port - I²C Timing ............................................................... 20
Switching Specifications - Control Port - SPI Timing .............................................................. 21

3. TYPICAL CONNECTION DIAGRAM ....................................................................... 23

3.1 Suggested Analog Input Buffer......................................................................................... 24

4. APPLICATIONS ......................................................................................................... 25

4.1 Power ............................................................................................................................... 25
4.2 Clocking............................................................................................................................ 25
4.3 Stand-Alone Operation ..................................................................................................... 26
4.4 Control-Port Operation ..................................................................................................... 26
4.5 DC Offset Control ............................................................................................................. 26
4.6 Serial Audio Interface (SAI) .............................................................................................. 26

4.6.1 General Description ............................................................................................. 26
4.6.2 Master and Slave Operation ................................................................................ 26
4.6.3 Synchronization of Multiple Devices .................................................................... 27
4.6.4 Sample Rate Ranges........................................................................................... 27
4.6.5 Using M1 and M0 to Set Sampling Parameters................................................... 27
4.6.6 Using DIF1 and DIF0 to Set Serial Audio Interface Format ................................. 28
4.6.7 Master Mode Audio Clocking ............................................................................... 28
4.6.8 Slave Mode Audio Clocking ................................................................................. 28
4.6.9 Master and Slave Clock Frequencies .................................................................. 29

4.7 Serial Audio Formats ........................................................................................................ 30

4.7.1 LJ and I²S FORMAT ............................................................................................ 31
4.7.2 TDM Format......................................................................................................... 31

4.8 Overflow Detection ........................................................................................................... 31

4.8.1 Stand-Alone Mode ............................................................................................... 31
4.8.2 Control-Port Mode................................................................................................ 31

4.9 Control Port Operation...................................................................................................... 31

4.9.1 SPI Mode ............................................................................................................. 31
4.9.2 I²C Mode .............................................................................................................. 32

5. REGISTER MAP......................................................................................................... 35

5.1 Register Quick Reference ............................................................................................... 35
5.2 00h (REVI) Chip ID Code & Revision Register................................................................. 35
5.3 01h (GCTL) Global Mode Control Register ..................................................................... 35

DS624A1

CS5368

5.4 02h (OVFL) Overflow Status Register ............................................................................. 36
5.5 03h (OVFM) Overflow Mask Register .............................................................................. 37
5.6 04h (HPF) High-Pass Filter Register ............................................................................... 37
5.7 05h Reserved .................................................................................................................. 37
5.8 06h (PDN) Power Down Register .................................................................................... 37
5.9 07h Reserved .................................................................................................................. 38
5.10 08h (MUTE) Mute Control Register ................................................................................ 38
5.11 09h Reserved ................................................................................................................ 38
5.12 0Ah (SDEN) SDOUT Enable Control Register .............................................................. 38

Appendix A Digital Filter Plots .................................................................................... 39

Appendix B Parameter Definitions.............................................................................. 43

Appendix C Package Dimensions .............................................................................. 45

DS624A1

CS5368

LIST OF FIGURES

Figure 1. CS5368 Pinout................................................................................................................. 9
Figure 2. I²S/LJ Timing.................................................................................................................. 18
Figure 3. TDM Timing ................................................................................................................... 19
Figure 4. I²C Timing ...................................................................................................................... 20
Figure 5. SPI Timing ..................................................................................................................... 21
Figure 6. Typical Connection Diagram.......................................................................................... 23
Figure 7. Recommended Analog Input Buffer............................................................................... 24
Figure 8. Crystal Oscillator Topology ............................................................................................ 25
Figure 9. Master Slave Clock Flow ............................................................................................... 27
Figure 10. Master and Slave Clocking for a 32-Channel Application............................................ 27
Figure 11. Master Mode Clock Dividers ........................................................................................ 28
Figure 12. LJ Format..................................................................................................................... 30
Figure 13. I²S Format .................................................................................................................... 30
Figure 14. TDM Format................................................................................................................. 30
Figure 15. SPI Format................................................................................................................... 32
Figure 16. I²C Write Format ......................................................................................................... 33
Figure 17. I²C Read Format .......................................................................................................... 33
Figure 18. SSM Passband ............................................................................................................ 39
Figure 19. DSM Passband ............................................................................................................ 39
Figure 20. QSM Passband............................................................................................................ 39
Figure 21. SSM Stopband............................................................................................................. 40
Figure 22. DSM Stopband............................................................................................................. 40
Figure 23. QSM Stopband ............................................................................................................ 40
Figure 24. SSM -1 dB Cutoff ......................................................................................................... 41
Figure 25. DSM -1 dB Cutoff......................................................................................................... 41
Figure 26. QSM -1 dB Cutoff......................................................................................................... 41

DS624A1

CS5368

LIST OF TABLES

Table 1. Overflow Timeout ............................................................................................................ 19
Table 2. M1 and M0 Settings ........................................................................................................ 27
Table 3. DIF1 and DIF0 Pin Settings ............................................................................................ 28
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S ......................................................... 29
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S ......................................................... 29
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S ....................................................... 29
Table 7. Frequencies for 48 kHz Sample Rate using TDM........................................................... 29
Table 8. Frequencies for 96 kHz Sample Rate using TDM........................................................... 30
Table 9. Frequencies for 192 kHz Sample Rate using TDM......................................................... 30
Table 10. Revision History ........................................................................................................... 47

DS624A1

CS5368

Pin Name

Pin #

Pin Description

AIN2+AIN2-
AIN4+AIN4-
AIN3+AIN3-
AIN7+AIN7-
AIN8+AIN8-
AIN6+AIN6-
AIN5+AIN5-
AIN1+AIN1-

1,2,

11,12

13,14
15,16
17,18
43,44
45,46
47,48

Differential Analog (Inputs) - Audio signals are presented differently to the delta
sigma modulators via the AIN+/- pins.

GND

3,8

10,19
29,32

Ground (Input) Ground reference. Must be connected to analog ground.

4,9

Analog Power (Input) - Positive power supply for the analog section

Quiescent Voltage (Output) - Filter connection for the internal quiescent reference
voltage.

XTAL Power

VLS

Serial Audio Interface Power - Positive power for the serial audio interface.

Digital Power (Input)- Positive power supply for the digital section/

VLC

Control Port Interface Power - Positive power for the control port interface.

REF_GND

Reference Ground (Input) - For the internal sampling circuits.

FILT+

Positive Voltage Reference (Output) - Reference voltage for internal sampling cir-
cuits.

XTIXTO

21
22

Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which
may be used to generate MCLK.

MCLK

System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buff-
ered MCLK Source (Output). When the oscillator function is not used, this pin acts as
an input for the system master clock. In this case, the XTI and XTO pins must be tied
low.

LRCK/FS

Serial Audio Channel Clock (Input/Output)
In I²S mode Serial Audio Channel Select. When high, the odd channels are selected.
In LJ mode Serial Audio Channel Select. When low, the odd channels are selected.
In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of
serial audio samples. In Slave Mode, this pin acts as an input pin.

SCLK

Main timing clock for the Serial Audio Interface(Input/Output). During Master Mode,
this pin acts as an output, and during Slave Mode it acts as an input pin.

SDOUT4/TDMC

Serial Audio Data (Output) Channels 7,8.

SDOUT2/TDMC

Serial Audio Data (Output) Channels 3,4.

SDOUT1/TDM

Serial Audio Data (Output) Channels 1,2.

SDOUT3/TDM

Serial Audio Data (Output) Channels 5,6.

OVFL

Overflow (Output, open drain) - Detects an overflow condition on both left and right
channels.

RST

Reset (Input) - The device enters a low power mode when low.

DS624A1

CS5368

Stand-Alone Mode

CLKMODE

CLKMODE (Input) Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK
path to the core device circuitry.

DIF1, DIF0

37, 38 DIF1, DIF0 (Input) - Inputs of the audio interface format.

M1, M0

39,40 Mode Selection (Input) - Determines the operational mode of the device.

MDIV

MCLK Divider (Input) Setting this pin HIGH places a divide-by-2 circuit in the MCLK
path to the core device circuitry.

Control Port Mode

CLKMODE

CLKMODE (Input) This pin is ignored in Control Port Mode and the same functionality
is obtained from the corresponding bit in the Global Control Register. Note: Should be
connected to GND.

AD1/CDIN

I²C Format, AD1 (Input) - Forms the device address input AD[1].
SPI Format, CDIN (Input) - Becomes the input data pin.

AD0/CS

I²C Format, ADO (Input) - Forms the device address input AD[0].
SPI Format, CS (Input) - Acts as the active low chip select input.

SCL/CCLK

I²C Format, SCL (Output) - Acts as the serial clock output from the CS5368.
SPI Format, CCLK (Output) - Acts as the serial clock output from the CS5368.

SDA/CDOUT

I²C Format SDA (Input/Output) - Acts as an input/output data pin.
SPI Format CDOUT (Output) - Acts as an output only data pin

MDIV

MCLK Divider (Input) This pin is ignored in Control Port Mode and the same function-
ality is obtained from the corresponding bit in the Global Control Register.
Note: Should be connected to GND.

DS624A1

CS5368

2. CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the specified operating conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at typical supply voltages and
T

= 25

SPECIFIED OPERATING CONDITIONS

GND = 0 V, all voltages with respect to 0 V.

1. TDM Quad-Speed Mode specified to operate correctly at VLS

3.14 V.

ABSOLUTE RATINGS

Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed
at these extremes. Transient currents up to ±100 mA on the analog input pins will not cause SCR latch-up.

SYSTEM CLOCKING

THERMAL CHARACTERISTICS

Parameter

Symbol Min

Typ

Max

Unit

DC Power Supplies:

Positive Analog
Positive Crystal

Positive Digital

Positive Serial Logic

Positive Control Logic

VLS

VLC

4.75
4.75
3.14

1.71

5.0
5.0
3.3
3.3
3.3

5.25
5.25
5.25
5.25
5.25

V
V
V
V
V

Ambient Operating Temperature

(-CQZ)
(-DQZ)

-10
-40

-
-

85
85

°C
°C

Parameter

Symbol

Min

Typ

Max

Units

DC Power Supplies:

Positive Analog
Positive Crystal

Positive Digital

Positive Serial Logic

Positive Control Logic

VA
VX

VLS

VLC

-0.3
-0.3
-0.3
-0.3
-0.3

+6.0
+6.0
+6.0
+6.0
+6.0

V
V
V
V
V

Input Current

Analog Input Voltage

-0.3

VA+0.3

V
V

Digital Input Voltage

IND

-0.3

VL+0.3

Ambient Operating Temperature (Power Applied)

-50

+95

Storage Temperature

stg

-65

+150

Parameter

Symbol

Min

Typ

Max

Unit

Input Master Clock Frequency

MCLK

0.512

55.05

MHz

Input Master Clock Duty Cycle

clkhl

Parameter

Symbol

Min

Typ

Max

Unit

Allowable Junction Temperature

135

Package Thermal Resistance

C/W

DS624A1

CS5368

DC POWER CS5368

MCLK = 12.288 MHz; Master Mode. Power Down is defined as RST = LOW with all clocks and data lines held
static. GND = 0 V.

LOGIC LEVELS

PSRR, VQ AND FILT+ CHARACTERISTICS

MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in
the "Typical Connection Diagram".

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply Current

VA = 5 V

(Normal Operation)

VX = 5 V

VD = 5 V

VD = 3.3 V

VLS, VLC = 5 V

VLS, VLC = 3.3 V

-
-
-
-
-
-

88
58

8
5

97
64

9
6

mA
mA
mA
mA
mA
mA

Power Supply Current

VA = 5 V

(Power-Down)

VLS, VLC,VD = 5 V

-
-

2
2

-
-

mA
mA

Power Consumption
(Normal Operation)

All Supplies = 5 V

VA = 5 V, VD = VLS = VLC = 3.3 V

(Power-Down)

-
-
-

830
558

915
616

mW
mW
mW
mW

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

%VLS/VLC

%
%

Low-Level Input Voltage

%VLS/VLC

High-Level Output Voltage at 100

A load %VLS/VLC

%
%

Low-Level Output Voltage at -100

A load %VLS/VLC

OVFL

Current Sink

-4

Input Leakage Current

logic pins only

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply Rejection Ratio at 1 kHz)

PSRR

Nominal Voltage

Output Impedance
Maximum allowable DC current source/sink

-
-
-

VA/2

25
10

-
-
-

Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink

-
-
-

4.4

-
-
-

DS624A1

CS5368

ANALOG PERFORMANCE (CS5368-CQZ)

Unless otherwise specified, input test signal is a 1 kHz sine wave. Measurement bandwidth is 10 Hz to 20 kHz.

Parameter

Symbol

Min

Typ Max

Unit

Single-Speed Mode (Fs = 48 kHz)
Dynamic Range

A-weighted

unweighted

108
105

114

111

-
-

dB
dB

Total Harmonic Distortion + Noise

-1 dB

referred to typical full scale

-20 dB
-60 dB

THD+N

-
-
-

-105

-91
-51

-99

-
-

dB
dB
dB

Double-Speed Mode (Fs = 96 kHz)
Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

108
105

114

111

108

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise

-1 dB

referred to typical full scale

-20 dB
-60 dB

40 kHz bandwidth -1dB

THD+N

-
-
-
-

-105

-91
-51

-102

-99

-
-
-

dB
dB
dB
dB

Quad-Speed Mode (Fs = 192 kHz)
Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

108
105

114

111

108

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise

-1 dB

referred to typical full scale

-20 dB
-60 dB

40 kHz bandwidth -1dB

THD+N

-
-
-
-

-105

-91
-51

-102

-99

-
-
-

dB
dB
dB
dB

Dynamic Performance for All Modes
Interchannel Isolation

110

DC Accuracy
Interchannel Gain Mismatch

0.1

Gain Error

Gain Drift

100

ppm/°C

Offset Error

HPF enabled

HPF disabled

-
-

100

LSB
LSB

Analog Input Characteristics
Full-scale Differential Input Voltage

(at VA = 5V)

1.07*VA

1.13*VA

1.19*VA

Vpp

Input Impedance (Differential)

7.5

Common Mode Rejection Ratio

CMRR

DS624A1

CS5368

ANALOG PERFORMANCE (CS5368-DQZ)

Unless otherwise specified, input test signal is a 1 kHz sine wave. Measurement bandwidth is 10 Hz to 20 kHz.

Parameter

Symbol

Min

Typ

Max

Unit

Single-Speed Mode Fs = 48 kHz
Dynamic Range

A-weighted

unweighted

106
103

114

111

-
-

dB
dB

Total Harmonic Distortion + Noise

-1 dB

referred to typical full scale

-20 dB
-60 dB

THD+N

-
-
-

-105

-91
-51

-97

-
-

dB
dB
dB

Double-Speed Mode Fs = 96 kHz
Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

106
103

114

111

108

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise

-1 dB

referred to typical full scale

-20 dB
-60 dB

40 kHz bandwidth -1 dB

THD+N

-
-
-
-

-105

-91
-51

-102

-97

-
-
-

dB
dB
dB
dB

Quad-Speed Mode Fs = 192 kHz
Dynamic Range

A-weighted

unweighted

40 kHz bandwidth unweighted

106
103

114

111

108

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise

-1 dB

referred to typical full scale

-20 dB
-60 dB

40 kHz bandwidth -1 dB

THD+N

-
-
-
-

-105

-91
-51

-102

-97

-
-
-

dB
dB
dB
dB

Dynamic Performance for All Modes
Interchannel Isolation

110

DC Accuracy
Interchannel Gain Mismatch

0.1

Gain Error

Gain Drift

100

ppm/°C

Offset Error

HPF enabled

HPF disabled

-
-

100

LSB
LSB

Analog Input Characteristics
Full-scale Input Voltage

(at VA = 5.0 V)

1.02*VA

1.13*VA

1.24*VA

Vpp

Input Impedance (Differential)

7.5

Common Mode Rejection Ratio

CMRR

DS624A1

CS5368

SERIAL AUDIO INTERFACE - TDM TIMING

The serial audio port is a 3 pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; C

= 20 pF, timing threshold is 50% of VLS.

Notes:

1. TDM Quad-Speed Mode only specified to operate correctly at VLS

3.14 V.

2. In Master mode, the SCLK/LRCK ratio is fixed at 256. In Slave Mode, the SCLK/RCLK ratio can be set

according to preference. However, chip performance is guaranteed only when using the ratios in

Section

4.6.9 Master and Slave Clock Frequencies on page 29

Figure 3. TDM Timing

OVERFLOW TIMEOUT

Logic "0" = GND = 0 V; Logic "1" = VLS; C

= 15 pF, timing threshold is 50% of VLS.

Table 1. Overflow Timeout

Parameter

Symbol

Min

Typ

Max

Unit

Sample Rates

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

-
-
-

108

-
-
-

108
216

kHz
kHz
kHz

SCLK Frequency

SCLK Period

1/(256*54 kHz)

SCLK Duty Cycle

PERIOD

HIGH1

72.3

256*Fs

-
-

FS setup

before SCLK rising

FS hold

after SCLK rising

FS width

in SCLK cycles

SETUP1

HOLD1

HIGH2

20
20

-
-
-

-
-

250

ns
ns

SDOUT setup

before SCLK rising

SDOUT hold

after SCLK rising

SETUP2

HOLD2

10
10

-
-

ns
ns

Parameter

Symbol

Min

Typ

Max

Unit

OVFL time-out on overrange condition

Fs = 44.1 kHz

Fs = 192 kHz

-
-
-

-1)/Fs

2972

683

-
-
-

ms
ms
ms

SDOUT

SCLK

data

HOLD2

SETUP2

HOLD1

SETUP1

new frame

data

PERIOD

HIGH1

HIGH2

DS624A1

CS5368

3. TYPICAL CONNECTION DIAGRAM

Figure 6. Typical Connection Diagram

For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low cost single
ended to differential solution is provided on the Customer Evaluation Board.

FILT+

+5V

5.1

SDOUT2/ TDMC

DIF0/AD0/CS

Power Down

and Mode

Settings

0.01

MODE0/SDA/CDOUT

MODE1/SCL/CCLK

REF_GND

VLC

AIN +

AIN -

Channel 1 Analog

Input Buffer

AIN +

AIN -

Channel 2 Analog

Input Buffer

AIN +

AIN -

Channel 3 Analog

Input Buffer

AIN +

AIN -

Channel 4 Analog

Input Buffer

AIN +

AIN -

Channel 5 Analog

Input Buffer

AIN +

AIN -

Channel 6 Analog

Input Buffer

AIN +

AIN -

Channel 7 Analog

Input Buffer

AIN +

AIN -

Channel 8 Analog

Input Buffer

0.1

GND

220

0.1

GND

DIF1/AD1/CDIN

RST

OVFL

0.01

+5V to 3.3V

A/D CONVERTER

CS5368

SDOUT1/ TDM

SDOUT3/ TDM

SDOUT4/ TDMC

SCLK

MCLK

Timing Logic

and Clock

Audio Data

Processor

MDIV

CLKMODE

LRCK/FS

+5V to 1.8V

3, 8, 10,

19, 29, 32

4, 9, 20

VLS

0.01

XTI

XTO

* Resistor may only

be used if VD is

derived from VA. If

used, do not drive any

other logic from VD.

+5V to 1.8V

+5V

DS624A1

CS5368

4. APPLICATIONS

4.1

Power

For convenient interfacing to external devices, there are five independent power pins for the CS5368. VD
powers the digital core. VA powers the analog core. VLS powers the Serial Audio Interface. VLC powers
the control logic. VX powers the crystal oscillator. The power pins may have any supported voltage range
of the specified voltages supplied simultaneously.

To meet full performance specifications, the CS5368 requires normal low noise board layout. The

"Typical

Connection Diagram" on page 23

shows the recommended power arrangements, with VA connected to a

clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be pow-
ered from the analog supply via a single-pole decoupling filter.

Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high frequency
capacitors being placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ
pins in order to avoid unwanted coupling into the device. The FILT+ and VQ decoupling capacitors must be
positioned to minimize the electrical path to ground.

The CDB5368 evaluation board demonstrates an optimum layout for the device.

4.2

Clocking

The device supports clocking through the use of either an on-board crystal oscillator driver or an externally
supplied clock. When using the on-board crystal driver, the topology shown in

Figure 8. "Crystal Oscillator

Topology"

must be used. The crystal oscillator manufacturer supplies recommended capacitor values.

Figure 8. Crystal Oscillator Topology

When using the on-board crystal oscillator driver, the XTI pin is the input for the Master clock (MCLK) to the
device. The XTO pin must not be used to drive anything other than the oscillator tank circuitry. Instead, a
buffered copy of XTI is available on the MCLK pin, which is level controlled by VLS and may be used to
synchronize other parts to the device.

If an external clock is used, the XTI and XTO pins must be grounded, and the MCLK pin becomes an input
for the system Master clock.

The CS5368 provides on board master clock dividers that precede all other internal clocking. The available
dividers are divide by 1, 1.5, 2, 3, 4.

XTI

XTO

DS624A1

CS5368

4.3

Stand-Alone Operation

In Stand-Alone Mode, the CS5368 is programmed exclusively with multi-use configuration pins. This mode
provides a set of commonly used features. To utilize the complete set of device features, Control-Port Mode
needs to be used.

To use the CS5368 in Stand-Alone Mode, the configuration pins must be held in a stable state and RST
must be asserted until the power supplies and clocks are stable. Upon de-assertion of RST the state of the
configuration pins are latched, Vq stabilizes and the device starts sending audio output data.

4.4

Control-Port Operation

In Control-Port Mode, all features of the CS5368 are available. Four multi-use configuration pins become
software pins that support the I²C or SPI bus protocol. To initiate Control-Port Mode, a controller that sup-
ports I²C or SPI must be used to enable the internal register functionality. This is done by setting the
CP-EN bit (bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part.

4.5

DC Offset Control

The CS5368 includes a dedicated high-pass filter for each channel to remove input DC offset at the system
level. If a DC level is present, clicks might be heard when switching between devices in a multichannel sys-
tem.

In Standalone Mode, all of the high pass filters remain enabled. In Control-Port Mode, the high pass filters
default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the re-
spective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output
of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset reg-
ister is frozen, and this DC offset will continue to be subtracted from the conversion result.

4.6

Serial Audio Interface (SAI)

4.6.1 General Description

The SAI port consists of two timing pins, SCLK, LRCK/FS, and four audio data output pins,
SDOUT1/TDM, SDOUT2/TDM, SDOUT3/TDMC and SDOUT4/TDMC. The SAI port may be operated as
a timing master or a timing slave. The port supplies digital audio data in three standard formats, LJ, I²S
and TDM. Three sampling ranges are used to provide analog to digital audio conversion from 2 kHz to
216 kHz sampling rates.

The main TDM output port resides on the SDOUT1 pin. The remaining three TDM outputs are used to
balance device substrate noise. It is recommended that all four of these nets be routed and loaded iden-
tically for best device noise performance.

4.6.2 Master and Slave Operation

In Master mode, the CS5368 outputs SCLK and LRCK/FS which are synchronously derived from MCLK.
SCLK is the audio clock which shifts out the individual bits of each sample. In LJ and I²S format, LRCK/FS
signifies which channel of data is being shifted out. In TDM Mode, LRCK/FS acts as a frame synchroni-
zation signal. A high transition indicates the beginning of a new frame of 8 channels of serial data.

In Slave Mode, SCLK and LRCK/FS become inputs, and the signals must be supplied by another device.
The device may be another CS5368 or a microcontroller. Serial data is shifted out by the CS5368 in both
cases.

DS624A1

CS5368

Figure 9. Master Slave Clock Flow

4.6.3 Synchronization of Multiple Devices

To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK
must be the same for all of the CS5368s in the system. If only one Master clock source is needed, one
solution is to place one CS5368 in Master mode, and slave all of the other devices to the one master. If
multiple Master clock sources are needed, a possible solution would be to supply all clocks from the same
external source and time the CS5368 reset de-assertion with the falling edge of MCLK. This will ensure
that all converters begin sampling on the same clock edge.

Figure 10. Master and Slave Clocking for a 32-Channel Application

4.6.4 Sample Rate Ranges

Supported sampling rates are 2 kHz-216 kHz divided into three ranges: 2 kHz-54 kHz, 54 kHz-108 kHz,
and 108 kHz-216 kHz. These sampling speed modes are called Single-Speed Mode, Double-Speed
Mode and Quad-Speed Mode (SSM, DSM, QSM), respectively.

4.6.5 Using M1 and M0 to Set Sampling Parameters

The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and
M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control-
Port Mode.

Table 2. M1 and M0 Settings

Mode

Frequency Range

Single-Speed Master Mode

2 kHz - 54 kHz

Double-Speed Master Mode

54 kHz - 108 kHz

Quadruple-Speed Master Mode

108 kHz - 216 kHz

Auto-Detected Speed Slave Mode

2 kHz - 216 kHz

ADC as

timing

master

Controller

LRCK

SCLK

ADC as

timing

slave

Controller

LRCK

SCLK

Master

CS5368

Slave1

CS5368

Slave2

CS5368

Slave3

CS5368

SCLK & LRCK/FS

DS624A1

CS5368

4.6.6 Using DIF1 and DIF0 to Set Serial Audio Interface Format

The format of the data at the Serial Audio Interface ports is controlled by the settings of the DIF1 and DIF0
pins in standalone mode, or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control-
Port Mode.

Table 3. DIF1 and DIF0 Pin Settings

4.6.7 Master Mode Audio Clocking

Figure 11. "Master Mode Clock Dividers"

shows the configuration of the MCLK dividers and the sample

rate dividers while in Master Mode.

Figure 11. Master Mode Clock Dividers

4.6.8 Slave Mode Audio Clocking

In Slave Mode, the sampling rate is auto-set by examining the incoming MCLK and LRCK/FS signals.
LRCK/FS and SCLK operate as inputs in Slave Mode. It is recommended that the LRCK/FS be synchro-
nously derived from the Master clock, and it must be equal to the desired sampling rate, Fs.

DIF1

DIF0

Mode

Left Justified

I²S

TDM (2 wire)

TDM (4 wire)

÷ 1 2 8

÷ 6 4

M 0

M 1

L R C K / F S

S in g le
S p e e d

Q u a d

S p e e d

D o u b le

S p e e d

0 0

0 1

1 0

÷ 2

÷ 4

÷ 1

S C L K

S in g le
S p e e d

Q u a d

S p e e d

D o u b le

S p e e d

0 0

0 1

1 0

÷ 2 5 6

p in

C M O D E

M D I V

n /a

M C L K

÷ 1

÷ 1 .5

÷ 2

÷ 1

÷ 2

÷ 1

b it

C M O D E

M D IV 1

M D IV 0

0 /1

0 / 1

M C L K D IV ID E R S

S A M P L E R A T E D IV ID E R S

DS624A1

CS5368

4.6.9 Master and Slave Clock Frequencies

Tables 4 through

show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. In Master

Mode, the device outputs the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set ac-
cording to design preference. However, device performance is guaranteed only when using the ratios
shown in the tables

Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S

Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S

Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S

Table 7. Frequencies for 48 kHz Sample Rate using TDM

Control Port Mode only

LJ/I²S MASTER OR SLAVE

SSM

MCLK Divider

1.5

MCLK (MHz)

49.152

36.864

24.576

18.384

12.288

SCLK(MHz)

3.072

3.072

MCLK/LRCK Ratio

1024

768

512

384

256

SCLK/LRCK Ratio

LJ/I²S MASTER OR SLAVE

DSM

MCLK Divider

1.5

MCLK (MHz)

49.152

36.864

24.567

18.384

12.288

SCLK(MHz)

6.144

6.144

MCLK/LRCK Ratio

512

384

256

192

128

SCLK/LRCK Ratio

LJ/I²S MASTER OR SLAVE

QSM

MCLK Divider

1.5

MCLK (MHz)

49.152

36.864

18.384

12.288

SCLK (MHz)

12.288

12.288

MCLK/LRCK Ratio

256

192

128

SCLK/LRCK Ratio

TDM MASTER OR SLAVE

SSM

MCLK Divider

1.5

MCLK (MHz)

49.152

36.864

24.567

18.384

12.288

SCLK (MHz)

12.288

12.288

MCLK/FS Ratio

1024

768

512

384

256

SCLK/FS Ratio

256

256

DS624A1

CS5368

Table 8. Frequencies for 96 kHz Sample Rate using TDM

Table 9. Frequencies for 192 kHz Sample Rate using TDM

4.7

Serial Audio Formats

The ADC supports I²S, Left-Justified and TDM digital interface formats. Audio data should be latched by the
receiver on the rising edge of SCLK within the specified setup and hold times.

Figure 12. LJ Format

Figure 13. I²S Format

Figure 14. TDM Format

TDM MASTER OR SLAVE

DSM

MCLK Divider

1.5

MCLK (MHz)

49.152

36.864

24.567

18.384

12.288

SCLK (MHz)

24.576

24.576

MCLK/FS Ratio

512

384

256

192

128

SCLK/FS Ratio

256

256

TDM MASTER OR SLAVE

QSM

MCLK Divider

1.5

MCLK (MHz)

49.152

36.864

24.567

18.384

12.288

SCLK (MHz)

49.152

49.152

MCLK/FS Ratio

256

192

128

SCLK/FS Ratio

256

256

Odd Channels 1,3, ...

Even Channels 2,4, ...

LRCK

receiver latches data on rising edges of SCLK

MSB

...

LSB

MSB

...

LSB

SDOUT

SCLK

Odd Channels 1,3, ...

Even Channels 2,4, ...

LRCK

receiver latches data on rising edges of SCLK

SDOUT

SCLK

MSB

...

LSB

MSB

...

LSB

MSB

Channel 6

SCLK

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

TDM OUT

Channel 1

Channel 4

Channel 2

Channel 5

Channel 3

32 clks

Channel 8

LSB

MSB

LSB

MSB

Channel 7

32 clks

256 sclks

MSB

Bit or Word Wide

LSB

DS624A1

CS5368

4.7.1 LJ and I

S FORMAT

The left-justified and I

S formats are both two-channel protocols. During one LRCK period, two channels

of data are transmitted, odd channels first, then even. The MSB is always clocked out first.

In Slave Mode, if more than 32 SCLKs per channel are received from a Master controller, the CS5368 will
fill the longer frame with trailing zeroes. If fewer than 24 SCLKs per channel are received from a Master,
the CS5368 will truncate the serial data output to the number of SCLKs received.

4.7.2 TDM Format

In TDM Mode, all eight channels of audio data are serially clocked out during a single Frame Sync (FS)
cycle. The rising edge of FS signifies the start of a new TDM frame cycle. Each channel slot occupies 32
SCLKs, with the data left justified and with MSB first. TDM output data should both be latched on the rising
edge of SCLK within the specified setup and hold times.

To achieve maximum noise performance, SDOUT2/TDM should be loaded in the same manner as
SDOUT1/TDM. For the same reason, it is also recommended that the serial clock be synchronously de-
rived from the Master clock and be equal to 256xFS.

4.8

Overflow Detection

4.8.1 Stand-Alone Mode

The CS5368 includes overflow detection on all input channels. In Stand-Alone Mode, this information is
presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an over-
range condition in any channel is detected. The data will remain low, then timeout as specified in

"Over-

flow Timeout" on page 19

. After the timeout, the OVFL pin will return to a logical high if there has not been

any other overrange condition detected. Note that an overrange condition on any channel will restart the
timeout period.

4.8.2 Control-Port Mode

In Control-Port mode, the Overflow Status Register interacts with the Overflow Mask Register to provide
interrupt capability for each individual channel. See

page 36

for details on these two registers.

4.9

Control Port Operation

The Control Port is used to read and write the internal device registers. It supports two industry standard
formats, I²C and SPI. The part is in I²C format by default. SPI mode is selected if there is ever a high-to-low
transition on the AD0/CS pin after the RST pin has been brought high.

4.9.1 SPI Mode

In SPI mode, CS is the CS5368 chip select signal; CCLK is the control port bit clock (input into the CS5368
from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a con-
troller. Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.

To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be
1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits
form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated.
The next eight bits are the data which will be placed into the register designated by the MAP. During
writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k

re-

sistor, if desired.

DS624A1

CS5368

There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR
is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto
increment after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle that
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not,
as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear
consecutively

Figure 15. SPI Format

4.9.2 I²C Mode

In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is latched when the
CS5368 is being released from RST.

A Start condition is defined as a falling transition of SDA while SCL is high. A Stop condition is a rising
transition of SDA while SCL is high. All other transitions of SDA occur while SCL is low. The first byte sent
to the CS5368 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read,
low for a write). The upper five bits of the 7-bit address field are fixed at 10011. To communicate with a

CS5368

, the chip address field, which is the first byte sent to the CS5368, should match 10011 and be

followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation
is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or
written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting
the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is
separated by an acknowledge bit. The ACK bit is output from the CS5368 after each input byte is read
and is input to the CS5368 from the microcontroller after each transmitted byte.

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. The write
operation is aborted after the acknowledge for the MAP byte by sending a Stop condition. The following
pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.

M A P

MSB

LSB

DATA

b y te 1

b y te n

R/W

A D D R E S S

C H IP

ADDRESS

C H IP

C D IN

C C L K

C D O U T

MSB

LSB MSB

LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

DS624A1

CS5368

5. REGISTER MAP

In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC.

5.1

Register Quick Reference

5.2

00h (REVI) Chip ID Code & Revision Register

Default: See description

The Chip ID Code & Revision Register is used to store the ID and revision of the chip.

Bits[7:4] contain the chip ID, where the CS5368 is represented with a value of 0x8.

Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is
represented as 0x1, etc.

5.3

01h (GCTL) Global Mode Control Register

Default:

0x00

The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial
audio data format and the Master clock dividers for all channels. It also contains a control port
enable bit.

Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in
Stand-Alone Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and
the corresponding register values become functional.

Adr

Name

REVI CHIP-ID[3:0]

REVISION[3:0]

GCTL

CP-EN

CLKMODE

MDIV[1:0]

DIF[1:0]

MODE[1:0]

OVFL

OVFL8

OVFL7

OVFL6

OVFL5

OVFL4

OVFL3

OVFL2

OVFL1

OVFM

OVFM8

OVFM7

OVFM6

OVFM5

OVFM4

OVFM3

OVFM2

OVFM1

HPF

HPF8

HPF7

HPF6

HPF5

HPF4

HPF3

HPF2

HPF1

RESERVED

PDNE

not used

PDN-BG PDN-OSC

PDN87

PDN65

PDN43

PDN21

RESERVED

MUTE

MUTE8

MUTE7

MUTE6

MUTE5

MUTE4

MUTE3

MUTE2

MUTE1

RESERVED

SDEN

not used

SDEN4

SDEN3

SDEN2

SDEN1

R/W

CHIP-ID[3:0]

REVISION[3:0]

R/W

R/W

CP-EN

CLKMODE

MDIV[1:0]

DIF[1:0]

MODE[1:0]

DS624A1

CS5368

Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing
the bit invokes 256X mode (divide XTI by 1.0 - pass through).

Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide by 1
function is selected. When either bit is HIGH, an XTI divide by 2 function is selected. With both
bits HIGH, XTI is divided by 4.

The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].

Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock out da-
ta.

DIF[1:0]
0x00 Left Justified format
0x01 I²S format
0x02 TDM format
0x03 TDM format

Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is op-
erating as an audio clocking Master or Slave.

MODE[1:0]
0x00 Single-Speed Mode Master
0x01 Double-Speed Mode Master
0x02 Quad-Speed Mode Master
0x03 Slave Mode all speeds

5.4

02h (OVFL) Overflow Status Register

Default:

0xFF, no overflows have occurred.

Note:

This register interacts with Register 03h, the Overflow Mask Register.

The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow
condition on any channel is detected, the corresponding bit in this register is asserted (low) in ad-
dition to the open drain active low OVFL pin going low. Each overflow status bit is sticky and is
cleared only when read, providing full interrupt capability.

CLKMODE,MDIV[1],MDIV[0]

DESCRIPTION

000

Divide-by-1

100

Divide-by-1.5

001 or 010

Divide-by-2

101 or 110

Divide-by-3

011

Divide-by-4

111

Unused

R/W

OVFL8

OVFL7

OVFL6

OVFL5

OVFL4

OVFL3

OVFL2

OVFL1

DS624A1

CS5368

5.5

03h (OVFM) Overflow Mask Register

Default:

0xFF, all overflow interrupts enabled.

The Overflow Mask Register is used to allow or prevent individual channel overflow events from
creating activity on the OVFL pin. When a particular bit is set low in the Mask register, the
corresponding overflow bit in the Overflow Status register is prevented from causing any activity
on the OVFL pin.

5.6

04h (HPF) High-Pass Filter Register

Default:

0x00, all high-pass filters enabled.

The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each
channel. These filters are used to perform DC offset calibration, a procedure that is detailed in

"DC Offset Control" on page 26

5.7

05h Reserved

5.8

06h (PDN) Power Down Register

Default:

0x00 - everything powered up

The Power Down Register is used as needed to reduce the chip's power consumption.

Bit[7] RESERVED

Bit[6] RESERVED

Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.

Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscil-
lator core is shut down, and no clock is supplied to the chip. If the chip is running off an externally
supplied clock at the MCLK pin, it is also prevented from clocking the device internally.

Bit[3:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial
data outputs are forced to all zeroes.

R/W

R/W

OVFM8

OVFM7

OVFM6

OVFM5

OVFM4

OVFM3

OVFM2

OVFM1

R/W

R/W

HPF8

HPF7

HPF6

HPF5

HPF4

HPF3

HPF2

HPF1

R/W

Reserved

R/W

R/W

RESERVED

PDN-BG

PDN-OSC

PDN87

PDN65

PDN43

PDN21

DS624A1

CS5368

Appendix B Parameter Definitions

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal.
60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the
distortion components are below the noise level and do not affect the measurement. This measurement technique
has been accepted by the Audio Engineering Society, AES17-199, and the Electronic Industries Association of Ja-
pan, EIAJ CP-307. Expressed in decibels. The dynamic range is specified with and without an A-weighting filter.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth
(typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS
as suggested in AES17-1991 Annex A. Specified using an A-weighting filter.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz.
Units in decibels.

Interchannel Isolation

A measure of crosstalk between one channel and all remaining channels, measured for each channel at the con-
verter's output with no signal to the input under test and a full-scale signal applied to all other channels. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

Intrachannel Phase Deviation

The deviation from linear phase within a given channel.

Interchannel Phase Deviation

The difference in phase response between channels.
.

DS624A1

CS5368

Table 10. Revision History

Revision

Date

Changes

July 2005

Initial Release

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to

http://www.cirrus.com/

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VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-

STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,

INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT

THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL

APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND

OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION

WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.

Part Number CS5368

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