CHRONTEL
CHRONTEL
CHRONTEL
CHRONTEL
Chrontel
201-0000-038 Rev 3.0, 9/8/2002
1
CH7010B
Chrontel CH7010 DVI / TV Output Device
1. F
EATURES
· DVI Transmitter up to 165M pixels/second
· DVI low jitter PLL
· DVI hot plug detection
· TV output supporting graphics resolutions up to
1024 x768 pixels
· Programmable digital interface supports RGB and
YCrCb
· True scale rendering engine supports underscan in all TV
output resolutions
· Enhanced text sharpness and adaptive flicker removal
with up to 7 lines of filtering
· Support for all NTSC and PAL formats
· Provides CVBS, S-Video and SCART (RGB) outputs
· TV connection detection
· Programmable power management
· 10-bit video DAC outputs
· Fully programmable through serial port
· Complete Windows and DOS driver support
· Low voltage interface support to graphics device
· Offered in a 64-pin LQFP package
2. G
ENERAL
D
ESCRIPTION
The CH7010 is a display controller device which accepts a
digital graphics input signal, and encodes and transmits data
through a DVI (DFP can also be supported) or TV output
(analog composite, s-video or RGB). The device accepts data
over one 12-bit wide variable voltage data port which supports
five different data formats including RGB and YCrCb.
The DVI processor includes a low jitter PLL for generation of
the high frequency serialized clock, and all circuitry required
to encode, serialize and transmit data. The CH7010 comes in
versions able to drive a DVI display at a pixel rate of up to
165MHz, supporting UXGA resolution displays. No scaling
of input data is performed on the data output to the DVI
device.
The TV-Out processor performs non-interlace to interlace
conversion with scaling and flicker filters, and encode the data
into any of the NTSC or PAL video standards. The scaling and
flicker filter is adaptive and programmable to enable superior
text display. Eight graphics resolutions are supported up to
1024 by 768 with full vertical and horizontal underscan
capability in all modes. A high accuracy low jitter phase
locked loop is integrated to create outstanding video quality.
Support is provided for RGB bypass
mode which enables
driving a VGA CRT with the input data.
Figure 1. Functional Block Diagram
Clock
Driver
Data
Latch,
Demux
H, V, DE
Latch
Serial
port
Control
Scaling
Scan
Conv
Flicker Filt
DVI PLL
XCLK, XCLK*
DVI
Encode
DVI
Serialize
DVI
Driver
TV
Encode
Four
10-bit
DAC's
PLL3
Timing
D[11:0]
2
12
H,V,DE
VREF
XI/FIN,XO
P-OUT/TLDET*
BCO
TLC,TLC*
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
HPDET
GPIO[1:0]
AS
SPC
SPD
RESET*
C/H SYNC
ISET
CVBS
(DAC3)
Y/G
(DAC1)
C/R
(DAC2)
CVBS/B
(DAC0)
2
2
2
2
2
2
24
24
24
24
3
3
3
3
CHRONTEL
CH7010B
2
201-0000-038 Rev 3.0, 9/8/2002
3. P
IN
D
ESCRIPTIONS
3.1 Package Diagram
Figure 2. 64-Pin LQFP
DVDDV
C / H SYNC
Y / G
C / R
CVBS
ISET
VDD
GND
GND
AGND
XI / FIN
XO
AVDD
GPIO[1] / TLDET*
GPIO[0]
AS
DGND
A
GN
D
A
VD
D
VS
WI
N
G
TL
C
TL
C*
TD
C0
TD
C0
*
TD
C1
TD
C1
*
TD
C2
TD
C2
*
TVDD
TVDD
TG
ND
TG
ND
TG
ND
DGND
SPD
SPC
RESET*
HPDET
DVDD
VREF
DVDD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CVBS / B
Chrontel
XC
LK
XC
LK
*
D
[
11]
D
[
10]
D[
9
]
D[
8
]
D[
7
]
D[
6
]
D[
5
]
D[
4
]
D[
2
]
D[
1
]
D[
0
]
DG
ND
DV
D
D
H
V
DE
BCO / V SYNC
P-OUT/TLDET*
CH70
10
D[
3]
201-0000-038 Rev 3.0, 9/8/2002
3
CHRONTEL
CH7010B
3.2 Pin Description
Table 1. Pin Description
64-Pin
LQFP
# Pins Type
Symbol
Description
2
1
In
DE
Data Enable
This pin accepts a data enable signal which is high when active
video data is input to the device, and low all other times. The levels
are 0 to DVDDV, and the VREF signal is used as the threshold level.
This input is used by the DVI. The TV-Out function uses H and V
sync signals as reference to active video.
3
1
In
VREF
Reference Voltage Input
The VREF pin inputs a reference voltage of DVDDV / 2. The signal
is derived externally through a resistor divider and decoupling
capacitor, and will be used as a reference level for data, sync, data
enable and clock inputs.
4
1
In/Out
H
Horizontal Sync Input / Output
When the SYO bit is low, this pin accepts a horizontal sync input for
use with the input data. The amplitude will be 0 to DVDDV, and the
VREF signal is used as the threshold level.
When the SYO bit is high, the device will output a horizontal sync
pulse, 64 pixels wide. The output is driven from the DVDD. This
output is only for use with the TV-Out function.
5
1
In/Out
V
Vertical Sync Input / Output
When the SYO bit is low, this pin accepts a vertical sync input for
use with the input data. The amplitude will be 0 to DVDDV, and the
VREF signal is used as the threshold level.
When the SYO bit is high, the device will output a vertical sync
pulse one line wide. The output is driven from the DVDD supply.
This output is only for use with the TV-Out function.
7
2
In/Out
GPIO[1]
/
TLDET*
General Purpose Input - Output[1] /
DVI Detect Output
(Open drain or internal weak pull-up)
This pin provides a general purpose I/O controlled via the serial port.
When the GPIO[1] pin is configured as an output, this pin can be
used to output the DVI detect signal (pulls low when a termination
change has been detected on the HPDET input). This is an open
drain output. The output is released through serial port control.
8
2
In/Out
GPIO[0]
General Purpose Input - Output[0]
(Open drain or internal weak pull-up)
This pin provides a general purpose I/O controlled via the serial port.
This allows an external switch to be used to select NTSC or PAL at
power-up.
9
1
In
HPDET
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI is connected to a DVI
monitor. When terminated, the monitor is required to apply a
voltage greater than 2.4 volts. Changes on the status of this pin will
be relayed to the graphics controller via the P-OUT/TLDET* or
GPIO[1]/TLDET* pin pulling low.
10
1
In
AS
Address Select (Internal pull-up)
This pin determines the serial port address of the device
(1,1,1,0,1,AS*,AS).
CHRONTEL
CH7010B
4
201-0000-038 Rev 3.0, 9/8/2002
64-Pin
LQFP
# Pins Type
Symbol
Description
13
1
In
RESET*
Reset * Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the
serial port register.
14
1
In/Out
SPD
Serial Port Data Input / Output
This pin functions as the serial port data pin of the serial port
interface, and uses the DVDD supply.
15
1
In
SPC
Serial Port Clock Input
This pin functions as the clock pin of the
serial port
interface, and
uses the DVDD supply.
19
1
In
VSWING
DVI Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm
resistor should be connected between this pin and TGND using short
and wide traces.
22, 21
2
Out
TDC0,
TDC0*
DVI Data Channel 0 Outputs
These pins provide the DVI differential outputs for data channel 0
(blue).
25, 24
2
Out
TDC1,
TDC1*
DVI Data Channel 1 Outputs
These pins provide the DVI differential outputs for data channel 1
(green).
28, 27
2
Out
TDC2,
TDC2*
DVI Data Channel 2 Outputs
These pins provide the DVI differential outputs for data channel 2
(red).
30, 31
2
Out
TLC,
TLC*
DVI Clock Outputs
These pins provide the differential clock output for the DVI interface
corresponding to data on the TDC[0:2] outputs.
35
1
In
ISET
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be
connected between this pin and GND (DAC ground) using short and
wide traces.
36
1
Out
CVBS
Composite Video
This pin outputs a composite video signal capable of driving a 75
ohm doubly terminated load.
37
1
Out
Y/G
Luma / Green Output
This pin outputs a selectable video signal. The output is designed to
drive a 75 ohm doubly terminated load. The output can be selected
to be s-video luminance or green
.
38
1
Out
C/R
Chroma / Red Output
This pin outputs a selectable video signal. The output is designed to
drive a 75 ohm doubly terminated load. The output can be selected
to be s-video chrominance or red.
39
1
Out
CVBS/B
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is designed to
drive a 75 ohm doubly terminated load. The output can be selected
to be composite video or blue.
42
1
In
XI / FIN
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be
attached between this pin and XO. However, an external clock can
drive the XI/FIN input.
Table 1. Pin Description (continued)
201-0000-038 Rev 3.0, 9/8/2002
5
CHRONTEL
CH7010B
64-Pin
LQFP
# Pins Type
Symbol
Description
43
1
In
XO
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be
attached between this pin and XI / FIN. However, if an external
CMOS clock is attached to XI/FIN, XO should be left open.
46
1
Out
P-OUT /
TLDET*
Pixel Clock Output / DVI Detect Output
When the CH7010 is operating as a VGA to TV encoder in master
clock mode, this pin provides a pixel clock signal to the VGA
controller which is used as a reference frequency. The output is
selectable between 1X or 2X of the pixel clock frequency. The
output driver is driven from the DVDDV supply. This output has a
programmable tri-state. The capacitive loading on this pin should be
kept to a minimum.
When the CH7010 is operating as a DVI transmitter, this pin
provides an open drain output which pulls low when a termination
change has been detected on the HPDET input. The output is
released through serial port control.
47
1
Out
BCO/
V SYNC
Buffered Clock Output / Vertical Sync Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO reg-
ister.
This pin can also be used as VSYNC output.
48
1
Out
C/H SYNC
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal sync.
The output is driven from the DVDD supply.
50 55,
58 63
12
In / Out
D[11] - D[0]
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port of a
graphics controller. The levels are 0 to DVDDV, and the VREF
signal is used as the threshold level.
57, 56
2
In
XCLK,
XCLK*
External Clock Inputs
These inputs form a differential clock signal input to the CH7010
for use with the H, V, DE and D[11:0] data. If differential clocks
are not available, the XCLK* input should be connected to
VREF.
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit (in register
1Ch).
1, 12, 49
3
Power
DVDD
Digital Supply Voltage (3.3V-3.6V)
6, 11, 64
3
Power
DGND
Digital Ground
45
1
Power
DVDDV
I/O Supply Voltage (3.3V to 1.1V)
23, 29
2
Power
TVDD
DVI Transmitter Supply Voltage (3.3V-3.6V)
20, 26, 32 3
Power
TGND
DVI Transmitter Ground
18, 44
2
Power
AVDD
PLL Supply Voltage (3.3V-3.6V)
16, 17, 41 3
Power
AGND
PLL Ground
33
1
Power
VDD
DAC Supply Voltage (3.3V-3.6V)
34, 40
2
Power
GND
DAC Ground
Table 1. Pin Description (continued)
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