1
Features
F/F Enable
INHIBIT A
INV
V
IN
STOP -
INHIBIT REF
V
OUTB
Gnd
V
OUTA
V
CC
INHIBIT B
NONINV
STOP +
A
O u t p u t
L o g i c
B
O u t p u t
L o g i c
-
+
+
-
A
I n h
A m p
B
I n h
A m p
S t o p
A m p
D i g i t a l
I n p u t
L o g i c
Logic
Voltage
Regulator
Thermal
Shutdown
Analog
Stop
Latch
Toggle
Flip
Flop
+5V
Q
T
Q
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
R
S
+V
IN
130mV
s
Dual 1.5A Totem Pole
Outputs
s
40nsec Rise and Fall into
1000pF
s
Parallel or Push-Pull
Operation
s
Single-Ended to Push-Pull
Conversion
s
High-Speed Power
MOSFET Compatible
s
Low Cross-Conduction
Current Spike
s
Analog Latched
Shutdown
s
Internal Deadband Inhibit
Circuit
s
Low Quiescent Current
s
5V to 40V Operation
s
Thermal Shutdown
Protection
CS3706
Dual Output Driver
CS3706
Description
Block Diagram
The CS3706 integrated circuit pro-
vides an interface between low-
level TTL inputs and high-power
switching devices such as power
MOSFETs. A typical application is
single-ended PWM control to push-
pull power control conversion.
The primary function of this device
is to convert a bipolar single-ended
low current digital input to a pair of
totem pole outputs which can
source or sink up to 1.5A. An inter-
nal flip-flop, driven by double-
pulse suppression logic, can be
enabled to provide single-ended to
push-pull conversion. With the flip-
flop disabled, the outputs work in
parallel for 3.0A capability.
Protection functions are also includ-
ed for pulse-by-pulse current limit-
ing, automatic deadband control
and thermal shutdown.
Package Options
16 Lead PDIP
(Internally Fused Leads)
1
INHIBIT B
2
3
4
5
6
7
8
INV
NONINV
Gnd
Gnd
V
OUTA
F/F ENABLE
V
CC
16
15
14
13
12
11
10
9
INHIBIT A
INHIBIT REF
V
IN
Gnd
Gnd
V
OUTB
STOP +
STOP -
Note: All Four Ground
Pins must be Connected
to Common Ground.
A Company
¨
Rev. 4/29/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
2
Electrical Characteristics:
These specifications apply over the operating temperature range of the IC.
(V
IN
= V
CC
= 20V, Pins 4, 5, 12 &13 = 0V; unless otherwise stated.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Absolute Maximum Ratings
CS3706
Logic Supply Voltage (V
IN
) ...................................................................................................................................................40.0V
Output Supply Voltage (V
CC
) ...............................................................................................................................................40.0V
Output Current (each output, source, or sink)
Steady State ...............................................................................................................................................................±500mA
Peak Transient for Less Than 100µs ...........................................................................................................................±1.5A
Capacitive Discharge Energy ......................................................................................................................................20.0µJ
Digital Inputs (INV, NONINV) ..............................................................................................................................................5.5V
Analog Inputs (STOP +, STOP -) ............................................................................................................................................VIN
Inhibit Inputs (INHIBIT A, INHIBIT B, INHIBIT REF)......................................................................................................5.5V
Operating Temperature Range .......................................................................................................................................0 to 70ûC
Storage Temperature Range.......................................................................................................................................-65 to 150ûC
Lead Temperature Soldering
Wave Solder (through hole styles only).....................................................................................10 sec. max, 260¡C peak
Notes: All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, neg-
ative out of the specified terminal.
V
IN
Supply Current
V
IN
= 40V, V
CC
= 20V, INV = 0V,
Unused pins = open.
8
12
mA
V
CC
Supply Current
V
IN
= 20V, V
CC
= 40V, Outputs low
3
5
mA
V
CC
Leakage Current
V
IN
= 0V, V
CC
= 40V
0.05
0.10
mA
Digital Input Low Level
0.8
V
Digital Input High Level
2.2
V
Digital Input Current
V
I
= 0V
-0.6
-1.0
mA
Digital Input Leakage
V
I
= 5V
0.05
0.10
mA
Output High Sat., V
C
-V
OUT
I
OUT
= -50mA
2.0
V
Output High Sat., V
C
-V
OUT
I
OUT
= -500mA
2.5
V
Output Low Sat., V
OUT
I
OUT
= 50mA
0.4
V
Output Low Sat., V
OUT
I
OUT
= 500mA
2.5
V
Inhibit Threshold
V
REF
= 0.5V
0.4
0.6
V
Inhibit Threshold
V
REF
= 3.5V
3.3
3.7
V
Inhibit Input Current
V
REF
= 0V
-10
-20
µA
Analog Threshold
V
CM
= 0V to 15 V
100
130
150
mV
Analog Input Bias Current
V
I
= 0V, V
CM
= 15V
-10
-20
µA
Thermal Shutdown
Turn on
155
ûC
Thermal Shutdown
Turn off
125
ûC
3
CS3706
Typical Switching Characteristics: (V
IN
= V
CC
= 20V, T
A
= 25ûC. Delays measured 50% in to 50% out.)
PARAMETER
TEST CONDITIONS
OUTPUT C
L
=
UNIT
From Inv. Input to Output:
open
1.0
2.2
nF
Rise Time Delay
110
130
140
ns
10% to 90% Rise
20
40
60
ns
Fall Time Delay
80
90
110
ns
90% to 10% Fall
25
30
50
ns
From N.I. Input to Output:
Rise Time Delay
120
130
140
ns
10% to 90% Rise
20
40
60
ns
Fall Time Delay
100
120
130
ns
90% to 10% Fall
25
30
50
ns
V
C
Cross-Conduction
Output Rise
25
ns
Current Spike Duration
Output Fall
0
ns
Inhibit Delay
Inhibit Ref. = 1V
Inhibit = 0.5 to 1.5V
250
ns
Analog Shutdown Delay
Stop (+) Ref. = 0
Stop (-) Input = 0 to 0.5V
180
ns
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
16L PDIP
(Internally Fused Leads)
1
INHIBIT B
Control pin for deadband control on Channel B.
2
INV
Inverting input for output drivers.
3
NONINV
Noninverting input for output drivers.
4
Gnd
Ground.
5
Gnd
Ground.
6
V
OUT(A)
Channel A output.
7
F/F ENABLE
Controls the phase of the two outputs.
F/F ENABLE = Gnd
Out of phase.
F/F ENABLE = floating In phase.
8
V
CC
Supply voltage (5V to 40V) for output drivers.
9
STOP -
Inverting input for stop latch comparator.
10
STOP +
Noninverting input for stop latch comparator.
11
V
OUT(B)
Channel B output.
12
Gnd
Ground.
13
Gnd
Ground.
14
V
IN
Supply voltage (5V to 40V) for IC (except output driver).
15
INHIBIT REF
Reference input for deadband control.
16
INHIBIT A
Control pin for deadband control on channel A.
4
Outputs
The totem-pole outputs have been designed to minimize
cross-conduction current spikes while maximizing fast,
high-current rise and fall times. Current limiting can be
done externally either at the outputs or at the common
V
CC
pin. The output diodes included have slow recovery
and should be shunted with high-speed external diodes
when driving high-frequency inductive loads.
Flip/Flop
Grounding F/F Enable activates the internal flip-flop to
alternate the two outputs. With pin open, the two outputs
operate simultaneously and can be paralleled for higher
current operation. Since the flip-flop is triggered by the
digital input, an off-time of at least 200nsec. must be pro-
vided to allow the flip/flop to change states. Note that the
circuit logic is configured such that the ÒOFFÓ state is
defined as the outputs low.
Digital Inputs
With both an inverting and non-inverting input available,
either active-high or active-low signals may be accepted.
These are true TTL compatible inputsÐthe threshold is
approximately 1.2V with no hysteresis; and external pull-
up resistors are not required.
Inhibit Circuit
Although it may have other uses, this circuit is included to
eliminate the need for deadband control when driving rel-
atively slow bipolar power transistors. A diode from each
inhibit input to the opposite power switch collector will
keep one output from turning on until the other has
turned-off. The threshold is determined by the voltage on
INHIBIT REF which can be set from 0.5 to 3.5 V. When this
circuit is not used, ground INHIBIT REF and leave INHIB-
IT A&B open.
Analog Shutdown
This circuit is included to get a latched shutdown as close
to the outputs as possible, from a time standpoint. With an
internal 130mV threshold, this comparator has a common-
mode range from ground to (V
IN
- 3V). When not used,
both inputs should be grounded. The time required for
this circuit to latch is inversely proportional to the amount
of overdrive but reaches a minimum of 180nsec. As with
the flip-flop, an input off-time of at least 200nsec is
required to reset the latch between pulses.
Supply Voltage
With an internal 5V regulator, this circuit is optimized for
use with a 7 to 40V supply, however, with some slight
response time degradation, it can also be driven from 5V.
When V
IN
is low, the entire circuit is disabled and no cur-
rent is drawn from V
CC
. When combined with a CS384X
PWM, the Driver Bias switch can be used to supply V
IN
to
the CS3706. V
IN
switching should be fast as undefined
operation of the outputs may occur with V
IN
less than 5V.
Thermal Considerations
Should the chip temperature reach approximately 155ûC, a
parallel, non-inverting input is activated driving both out-
puts to the low state.
Circuit Description
INV.
N.I.
OUT
H
H
L
L
H
H
H
L
L
L
L
L
Truth Table
OUT = INV and N.I.
OUT = INV or N.I.
CS3706
5
CS3706
Application Diagram
5V
3k
2k
Input
Gnd
F/F ENABLE
INHIBIT A
V
OUTB
V
OUTA
INHIBIT B
V
IN
V
CC
CS3706
REF
NONINV
INV
14V
10
W
R
L
100
mF
100
W
.047
mF
.047
mF
100
W
10k
10k
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