CAT24C01B

1K-Bit Serial EEPROM

PIN CONFIGURATION

BLOCK DIAGRAM

PIN FUNCTIONS

Pin Name

Function

No Connect

SDA

Serial Data/Address

SCL

Serial Clock

+1.8V to +6.0V Power Supply

Ground

TEST

Test Input (GND, V

Floating)

DIP Package (P)

SOIC Package (J)

5020 FHD F01

FEATURES

2-Wire Serial Interface

1.8 to 6.0Volt Operation

Low Power CMOS Technology

4-Byte Page Write Buffer

Self-Timed Write Cycle with Auto-Clear

1,000,000 Program/Erase Cycles

100 Year Data Retention

8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP

Commercial, Industrial and Automotive
Temperature Ranges

DESCRIPTION

The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst's
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT24C01B features a

4-byte page write buffer. The device operates via a 2-
wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.

TSSOP Package (U)

Doc. No. 25085-00 7/99 S-1

DOUT

ACK

SENSE AMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

STATE COUNTERS

PROM

VCC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGH VOLTAGE/

TIMING CONTROL

VSS

SCL

SDA

VSS

VCC
TEST

SCL

SDA

VCC

SCL

SDA

VSS

TEST

VCC

SCL

SDA

VSS

TEST

MSOP Package (R)

VCC
TEST

SCL

SDA

VSS

EEPROM

CAT24C01B

Doc. No. 25085-00 7/99 S-1

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. 55

C to +125

Storage Temperature ....................... 65

C to +150

Voltage on Any Pin with

Respect to Ground

(1)

........... 2.0V to +V

+ 2.0V

with Respect to Ground ............... 2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25

C) .................................. 1.0W

Lead Soldering Temperature (10 secs) ............ 300

Output Short Circuit Current

(2)

........................ 100mA

*COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min.

Max.

Units

Reference Test Method

END

(3)

Endurance

1,000,000

Cycles/Byte

MIL-STD-883, Test Method 1033

(3)

Data Retention

100

Years

MIL-STD-883, Test Method 1008

ZAP

(3)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

LTH

(3)(4)

Latch-up

100

JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

Power Supply Current

SCL

= 100 KHz

(5)

Standby Current (V

= 5.0V)

= GND or V

Input Leakage Current

= GND to V

Output Leakage Current

OUT

= GND to V

Input Low Voltage

x 0.3

Input High Voltage

x 0.7

+ 0.5

OL1

Output Low Voltage (V

= 3.0V)

0.4

= 3 mA

OL2

Output Low Voltage (V

= 1.8V)

0.5

= 1.5 mA

Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V

+0.5V, which may overshoot to V

+ 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V

+1V.

(5) Standby Current (I

) = 0

A (<900nA).

CAPACITANCE T

= 25

C, f = 1.0 MHz, V

= 5V

Symbol

Test

Max.

Units

Conditions

I/O

(3)

Input/Output Capacitance (SDA)

I/O

= 0V

(3)

Input Capacitance (A0, A1, A2, SCL, WP)

= 0V

CAT24C01B

Doc. No. 25085-00 7/99 S-1

A.C. CHARACTERISTICS

= +1.8V to +6.0V, C

=1TTL Gate and 100pF (unless otherwise specified).

Read & Write Cycle Limits

Symbol

Parameter

1.8V, 2.5V

4.5V-5.5V

Min.

Max.

Min.

Max.

Units

SCL

Clock Frequency

100

400

kHz

(1)

Noise Suppression Time

100

Constant at SCL, SDA Inputs

SCL Low to SDA Data Out

3.5

and ACK Out

BUF

(1)

Time the Bus Must be Free Before

4.7

1.2

a New Transmission Can Start

HD:STA

Start Condition Hold Time

0.6

LOW

Clock Low Period

4.7

1.2

HIGH

Clock High Period

0.6

SU:STA

Start Condition Setup Time

4.7

0.6

(for a Repeated Start Condition)

HD:DAT

Data In Hold Time

SU:DAT

Data In Setup Time

250

100

(1)

SDA and SCL Rise Time

0.3

(1)

SDA and SCL Fall Time

300

SU:STO

Stop Condition Setup Time

4.7

0.6

Data Out Hold Time

100

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated.

The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its input.

Write Cycle Limits

Symbol

Parameter

Min.

Typ.

Max

Units

Write Cycle Time

Power-Up Timing

(1)(2)

Symbol

Parameter

Max.

Units

PUR

Power-up to Read Operation

PUW

Power-up to Write Operation

CAT24C01B

Doc. No. 25085-00 7/99 S-1

FUNCTIONAL DESCRIPTION

The CAT24C01B uses a 2-wire data transmission pro-
tocol. The protocol defines any device that sends data to
the bus to be a transmitter and any device receiving data
to be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.

PIN DESCRIPTIONS

SCL: Serial Clock
The CAT24C01B serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.

SDA: Serial Data/Address
The CAT24C01B bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.

2-WIRE BUS PROTOCOL

The following defines the features of the 2-wire bus
protocol:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.

Figure 2. Write Cycle Timing

Figure 1. Bus Timing

Figure 3. Start/Stop Timing

5020 FHD F05

5020 FHD F04

5020 FHD F03

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH

tWR

STOP
CONDITION

START
CONDITION

ADDRESS

ACK

8TH BIT

BYTE n

SCL

SDA

START BIT

SDA

STOP BIT

SCL

CAT24C01B

Doc. No. 25085-00 7/99 S-1

START Condition

The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C01B monitors the
SDA and SCL lines and will not respond until this
condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.

Acknowledge

After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.

The CAT24C01B responds with an acknowledge after
receiving a START condition and its word address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.

When the CAT24C01B is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowl-
edge, the CAT24C01B will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the
START condition and the word address information

(with the R/

bit set to zero) to the Slave device. After the

Slave generates an acknowledge, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24C01B acknowledge once
more and the Master generates the STOP condition, at
which time the device begins its internal programming
cycle to nonvolatile memory. While this internal cycle is
in progress, the device will not respond to any request
from the Master device.

Page Write

The CAT24C01B writes up to 4 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 3 additional bytes. After each byte has been
transmitted the CAT24C01B will respond with an ac-
knowledge, and internally increment the low order ad-
dress bits by one. The high order bits remain un-
changed.

If the Master transmits more than 4 bytes prior to sending
the STOP condition, the address counter `wraps around,'
and previously transmitted data will be overwritten.

Once all 4 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C01B in a single write cycle.

Acknowledge Polling

The disabling of the inputs can be used to take advan-

Figure 4. Acknowledge Timing

5020 FHD F06

ACKNOWLEDGE

START

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Part Number CAT24C01B