© 2000 California Micro Devices Corp. All rights reserved.
3/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CALIFORNIA MICRO DEVICES
PRN299
1
POSITIVE / PSEUDO ECL (PECL) CLOCK TERMINATION NETWORK
Features
Stable resistor network
Reduces power dissipation on the clock lines
Ideal for high-speed clock termination
Reduces board space by 70% vs. 1206 discretes
and component count by more than 50%
PAC VGA200 is a trademark of California Micro Devices Corp.
Application Note
High speed microprocessors line Intels Pentium/P6®, Apple PowerPC®, SPARC® and other CISC and RISC based systems need
well-controlled and precise clock signals to maintain a synchronous systems. The fast edge rated clock signals will exhibit
transmission line effects on the clock lines resulting in undershoots and overshoots. The integrated PECL termination is
designed to suppress the undershoots and overshoots on the clock lines. The PECL RC terminator dissipates very low power
compared to the resistor termination network.
Why thin.film R networks? The PECL termination is an integrated R network fabricated on a silicon substrate using
advanced thin film technology. This will have a fixed time constant and will not create additional skew on the clock lines. It
has a low parasitic inductance compared to discrete and conventional thick film R terminators and provide effective termination
at high frequencies.
Applications
PECL clock termination
When placing an order please specify desired shipping: Tubes or Tape & Reel.
T
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CALIFORNIA MICRO DEVICES
©2000 California Micro Devices Corp. All rights reserved.
3/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
PRN299
2
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Note 1: These parameter applies only to the HSYNC and VSYNC channels.
Note 2: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
CC1
, V
CC3
and V
CC4
must be bypassed
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins
are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD
protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
Note 3: This parameter is guaranteed by design and characterization.
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k
© 2000 California Micro Devices Corp. All rights reserved.
3/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CALIFORNIA MICRO DEVICES
PRN299
3
Typical Connection Diagram
A resistor may be necessary between the V
CC3
pin and ground if protection against a stream of ESD pulses is required while the
PAC VGA200 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into
the V
CC3
bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD
repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PAC VGA200 is in the power-up
state, an internal discharge resistor is connected to ground via an FET switch for this purpose.
For the same reason, V
CC1
and V
CC4
may also require bypass capacitor discharging resistors to ground if there are no other
components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75R resistors is not connected internally to GNDD and should ideally be connected to the
ground of the video DAC IC.
T
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V
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A
P
When placing an order please specify desired shipping: Tubes or Tape & Reel.
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