© 2000 California Micro Devices Corp. All rights reserved.
8/25/2000
1
PACS1284-06
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
P/AcitveTM IEEE 1284 ECP/EPP Termination Network
Features
· Single chip IEEE 1284 parallel port termination
· 28 pin QSOP package, smallest physical solution
· 17 terminating lines in a single package
· In system ESD protection to 8KV, HBM
· In system ESD protection to 4KV per IEC1000-4-2
· Protects downstream devices to 30V
Product Description
California Micro Devices' PACS1284-06 Parallel Port
Termination Network provides a complete integrated
solution for the entire IEEE 1284 interface in a single
QSOP package.
Advanced, enhanced high-speed parallel ports, con-
forming to the IEEE 1284 standard, are used to provide
communications with external devices such as tape
back-up drives, ZIP drives, printers, parallel port SCSI
adapters, external LAN adapters, scanners, video
capture, and other PC peripherals. These advanced
ports support bi-directional transfers to 2MB/sec. To
effectively support these higher transfer data rates, the
IEEE 1284 standard recommends a combined termina-
tion, pull-up filter network between the driver/receiver
and the cable at both ends of the parallel port interface.
In addition, government EMC compatibility requirements
impose strict filtering on the parallel port. California
Micro Devices' PACS1284-06
Parallel Port Termination
Network addresses all of these requirements by provid-
Applications
· ECP/EPP Parallel Port termination
· PC Peripherals
· Notebook and Desktop computers
· Engineering Workstations and Servers
C1380800
ing a seventeen line, IEEE 1284 compliant network in a
thin film integrated circuit. The device provides a
complete parallel port termination solution for space
critical applications by integrating a total of 43 discrete
components. In addition, all I/O pins are ESD
protected for contact discharges up to 4KV per the
Human Body Model. However, the output pins of the
device which have the highest probability of exposure
to ESD pulses are protected to 8KV, HBM, thereby
providing the necessary robustness for the port's
application environment.
California Micro Devices' P/Active technology provides
high reliability and low cost through manufacturing
efficiency. The resistors and capacitors are fabricated
using proprietary state-of-the-art thin film technology.
California Micro Devices' solution is silicon-based and
has the same reliability characteristics as today's
integrated circuits.
SCHEMATIC CONFIGURATION
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©2000 California Micro Devices Corp. All rights reserved.
8/25/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
PACS1284-06
CALIFORNIA MICRO DEVICES
* Guaranteed by design
Note 1: Human Body Model per MIL-STD-883, Method 3015
C
Discharge
= 100pF, R
Discharge
= 1.5 K
, pin 20 @ 5V and pin 22 @ ground.
Note 2: Pin 22 grounded, pin 20 to V
CC
, all other pins are open. ESD contact discharge between ground and
pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23 through 28, one at a time.
Note 3: Standard IEC 1000-4-2 with C
Discharge
= 150pF, R
Discharge
= 330
, pin 20 @ 5V and pin 22 @ ground.
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1
© 2000 California Micro Devices Corp. All rights reserved.
8/25/2000
3
PACS1284-06
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Application Information
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and
Status lines (8 in total) only require a pull-up resistor and a filter capacitor. The Data lines and Strobe also require a
series termination resistor in addition to the pull resistors and filter capacitors. See Table 1 and Schematic Diagram.
IEEE 1284 defines three interface connectors:
- 1284 A is a 25-pin DB series connector which is the defacto PC standard for the host connection.
- 1284 B is a 36-pin, 0.085 inch centerline connector used on the peripheral device.
- 1284 C is a new 36-pin, 0.050 inch centerline connector which can be used for both host and peripheral.
Figure 1 shows a possible hook-up between the 1284-A connector on a PC motherboard and the PACS1284-06,
illustrating how the pin configuration of the PACS1284-06 allows for easy interconnects between the two. The dotted I/
O signals of the PACS1284-06 will typically be connected to a Super I/O chip on the motherboard.
Figure 2 shows a possible hook-up between the 1284-B connector on a peripheral and the PACS1284-06.
Figure 3 shows a possible hook-up between the 1284-C connector and the PACS1284-06.
Sample Hook-ups of IEEE 1284 Connectors and PACS1284-06.
(connector and PACS1284-06 not drawn to scale)
Figure 1
Figure 2
Figure 3
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19
1
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20
= FLOW
THROUGH
SIGNALS
= GND
= V
CC
SUPER 1284
SUPER 1284
SUPER 1284
1284-A Connector
Host
1284-B Connector
Peripheral
1284-C Connector
Host/Peripheral
25
13
36
18
36
18
19
©2000 California Micro Devices Corp. All rights reserved.
8/25/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
4
PACS1284-06
CALIFORNIA MICRO DEVICES
Table 2 defines the signals for the three connectors.
Table 2. IEEE 1284 Connector Pinouts.
When connecting a 1284-A host to a 1284-B peripheral the "Peripheral Logic High" signal is not used. Similarly, when
a 1284-A host is connected to a 1284-C peripheral the "Peripheral Logic High" and "Host Logic High" are not used.
These two signals are optionally used to detect a "Power Off" or "Cable Disconnect" state for host and peripheral
respectively.
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© 2000 California Micro Devices Corp. All rights reserved.
8/25/2000
5
PACS1284-06
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Figure 4 shows typical Insertion Loss graphs for the PACS1284-06 for Data and Strobe signals. The curves are
dependent on the physical location of the filter elements with respect to the ground and V
CC
terminals of the device.
These graphs are measured in a 50 Ohm environment. The signal is introduced at the series resistor input and the
output is measured at the corresponding filter capacitor. The graphs labeled A,B, and C are measured between 14
(input) and 16 (output), pin 3 (input) and 26 (output), and pin 6 (input) and 23 (output), respectively. The A graph
depicts "worst case" filter performance, while C represents a "best case" situation. Graphs of all other filter elements
will fall in between these two.
Figure 4. Typical Filter Insertion Loss for PACS1284-06 (S
12
in dB, T
A
= 25
O
C)
Filter insertion loss is measured using Hewlett Packard HP 8753C Analyzer
0
-10
-20
-30
-40
-50
S
in dB
A
B
C
12
300
450
(FREQUENCY, MHz)
600
750
900
1050
1200
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