ChipFind - Datasheet

Part Number PACRAMBUS-1

Download:  PDF   ZIP
OBJECTIVE
© 2000 California Micro Devices Corp. All rights reserved.
4/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
1
CALIFORNIA MICRO DEVICES
PACRAMBUS-1
HIGH PERFORMANCE RAMBUS TERMINATION NETWORK
FOR RIMM CONNECTOR
Features
2 chip solution for all Rambus load
terminations, in 20-pin QSOP narrow package
14 Terminations in a single package
1% absolute tolerance 28 ohms
terminations across temperature range
Center ground pin placement reduces
ground bounce and eases board layout
Very low cross-talk
Saves board space and reduces assembly cost
Product Description
The Direct Rambus memory interface transfers data at both edges of a 400MHz clock resulting in an 800MHz transfer rate.
The Rambus channel uses a memory controller on one end of the bus, terminations at the other end, and the RIMM
modules in between. The Rambus channel contains control signals and data bus lines that must be terminated in order to
prevent any reflections. California Micro Devices PAC RAMBUS-1 integrates fourteen 28-ohm resistors specified at 1%
absolute tolerance across the commercial temperature range.
This termination network provides high performance, high reliability, and low cost through manufacturing efficiency. The
termination resistor elements are fabricated using state-of-the-art thin film manufacturing. This integrated solution is silicon-
based and has the same reliability characteristics as any of todays microprocessor products. The thin film resistors have very
high stability over temperature, over applied voltage, and over life. In addition, the QSOP industry standard packaging is easy
to handle in manufacturing and yields a high reliability similar to other semiconductor components.
Applications
Rambus Memory System
C0470199
SCHEMATIC
(
R
)
e
d
o
C
8
2
0
8
2
S
N
O
I
T
A
C
I
F
I
C
E
P
S
D
R
A
D
N
A
T
S
)
R
(
r
o
t
si
s
e
R
s
m
h
O
8
2
)
C
°
0
7
o
t
°
0
(
)
R
(
e
c
n
a
r
e
l
o
T
e
t
u
l
o
s
b
A
%
1
±
R
C
T
m
p
p
0
5
1
±
e
g
n
a
R
e
r
u
t
a
r
e
p
m
e
T
g
n
it
a
r
e
p
O
C
°
0
7
o
t
C
°
0
r
o
t
si
s
e
R
/
g
n
it
a
R
r
e
w
o
P
W
m
0
4
)
C
°
0
7
(
g
n
it
a
R
r
e
w
o
P
e
g
a
k
c
a
P
x
a
M
W
0
0
.
1
k
l
a
T
s
s
o
r
C
D
B
T
OBJECTIVE
©2000 California Micro Devices Corp. All rights reserved.
4/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
CALIFORNIA MICRO DEVICES
PACRAMBUS-1
The following lines must be terminated:
DQA[8:0]:
Data bus A,
DQB[8:0]:
Data bus B,
CFM, CFMN: Clock From Master (positive and negative polarity),
ROW[2:0]:
Row bus,
COL[4:0]:
Column bus.
RECOMMENDED LAYOUT (PAC RAM-280) FOR RAMBUS RIMM CONNECTOR
N
O
I
T
A
M
R
O
F
N
I
G
N
I
R
E
D
R
O
T
R
A
P
D
R
A
D
N
A
T
S
e
g
a
k
c
a
P
r
e
b
m
u
N
t
r
a
P
g
n
i
r
e
d
r
O
s
n
i
P
e
l
y
t
S
s
e
b
u
T
l
e
e
R
&
e
p
a
T
g
n
i
k
r
a
M
t
r
a
P
0
2
w
o
r
r
a
N
P
O
S
Q
T
/
1
-
S
U
B
M
A
R
C
A
P
R
/
1
-
S
U
B
M
A
R
C
A
P
1
-
S
U
B
M
A
R
C
A
P
OBJECTIVE
© 2000 California Micro Devices Corp. All rights reserved.
4/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
3
CALIFORNIA MICRO DEVICES
PACRAMBUS-1
E
D
C
B
e
L
H
H
1
A
A
1
CAMD
QSOP - TOP VIEW
S
N
O
I
T
A
C
I
F
I
C
E
P
S
L
A
C
I
N
A
H
C
E
M
g
n
it
a
l
P
d
a
e
L
d
a
e
L
-
n
i
T
l
a
ir
e
t
a
M
d
a
e
L
y
o
ll
A
r
e
p
p
o
C
y
ti
r
a
n
a
l
p
o
C
d
a
e
L
)
m
m
2
0
1
.
0
(
"
4
0
0
.
0
l
a
ir
e
t
a
M
e
t
a
rt
s
b
u
S
n
o
c
il
i
S
l
a
ir
e
t
a
M
y
d
o
B
y
x
o
p
E
d
e
d
l
o
M
y
ti
li
b
a
m
m
a
l
F
0
-
V
4
9
L
U
N
O
I
T
A
M
R
O
F
N
i
&
N
O
I
T
A
P
I
S
S
I
D
R
E
W
O
P
,
S
N
O
I
S
N
E
M
I
D
E
G
A
K
C
A
P
e
g
a
k
c
a
P
P
O
S
Q
#
s
n
i
P
0
2
m
m
s
e
h
c
n
i
n
i
m
x
a
m
n
i
m
x
a
m
A
5
3
.
1
5
7
.
1
3
5
0
.
0
9
6
0
.
0
A
1
0
1
.
0
5
2
.
0
4
0
0
.
0
0
1
0
.
0
B
0
2
.
0
0
3
.
0
8
0
0
.
0
2
1
0
.
0
C
8
1
.
0
5
2
.
0
7
0
0
.
0
0
1
0
.
0
D
6
5
.
8
3
7
.
8
7
3
3
.
0
4
4
3
.
0
E
1
8
.
3
8
9
.
3
0
5
1
.
0
7
5
1
.
0
e
C
S
B
4
6
.
0
C
S
B
5
2
0
.
0
H
9
7
.
5
9
1
.
6
8
2
2
.
0
4
4
2
.
0
L
0
4
.
0
7
2
.
1
6
1
0
.
0
0
5
0
.
0
P
D
C
°
0
7
@
W
0
0
.
1
e
b
u
t
/
#
s
c
p
6
5
l
e
e
r
&
e
p
a
t
/
#
s
c
p
0
0
5
,
2
POWER DERATING CURVE