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Part Number PLL1708

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PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
3.3 V DUAL PLL MULTICLOCK GENERATOR
FEATURES
D
27-MHz Master Clock Input
D
Generated Audio System Clock (PLL1707):
­ SCKO0: 768 f
S
(f
S
= 44.1 kHz)
­ SCKO1: 768 f
S
, 512 f
S
(f
S
= 48 kHz)
­ SCKO2: 256 f
S
(f
S
= 32, 44.1, 48, 64, 88.2,
96 kHz)
­ SCKO3: 384 f
S
(f
S
= 32, 44.1, 48, 64, 88.2,
96 kHz)
D
Generated Audio System Clock (PLL1708):
­ SCKO0: 768 f
S
(f
S
= 44.1 kHz)
­ SCKO1: 768 f
S
, 512 f
S
, 384 f
S
, 256 f
S
(f
S
= 48 kHz)
­ SCKO2: 256 f
S
(f
S
= 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
­ SCKO3: 384 f
S
(f
S
= 16, 22.05, 24, 32, 44.1,
48, 64, 88.2, 96 kHz)
D
Zero PPM Error Output Clocks
D
Low Clock Jitter: 50 ps (Typical)
D
Multiple Sampling Frequencies (PLL1707):
­ f
S
= 32, 44.1, 48, 64, 88.2, 96 kHz
D
Multiple Sampling Frequencies (PLL1708):
­ f
S
= 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,
96 kHz
D
3.3-V Single Power Supply
D
PLL1707: Parallel Control
PLL1708: Serial Control
D
Package: 20-Pin SSOP (150 mil), Lead-Free
Product
APPLICATIONS
D
HDD + DVD Recorders
D
DVD Recorders
D
HDD Recorders
D
DVD Players
D
DVD Add-On Cards for Multimedia PCs
D
Digital HDTV Systems
D
Set-Top Boxes
DESCRIPTION
The PLL1707
and PLL1708
are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1707 and
PLL1708 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1707 can be controlled by sampling frequency-control
pins and those of the PLL1708 can be controlled through
serial-mode control pins. The device gives customers both
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1707 and PLL1708 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD recorders, HDD recorders, DVD
add-on cards for multimedia PCs, digital HDTV systems,
and set-top boxes.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
2
FUNCTIONAL BLOCK DIAGRAM
Mode Control Interface
( ): PLL1708
XT1
(MS)
SR
(MC)
FS2
(MD)
FS1
CSEL
PLL2
PLL1
OSC
XT2
MCKO1
MCKO2
SCKO0
Divider
Divider
Divider
SCKO1
SCKO2
SCKO3
Reset
Power Supply
VCC AGND VDD1­3 DGND1­3
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PLL1707DBQ
SSOP 20
20DBQ
25
°
C to 85
°
C
PLL1707
PLL1707DBQ
Tube
PLL1707DBQ
SSOP 20
20DBQ
­25
°
C to 85
°
C
PLL1707
PLL1707DBQR
Tape and reel
PLL1708DBQ
SSOP 20
20DBQ
25
°
C to 85
°
C
PLL1708
PLL1708DBQ
Tube
PLL1708DBQ
SSOP 20
20DBQ
­25
°
C to 85
°
C
PLL1708
PLL1708DBQR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PLL1705 AND PLL1706
Supply voltage: VCC, VDD1­VDD3
4 V
Supply voltage differences: VCC, VDD1­VDD3
±
0.1 V
Ground voltage differences: AGND, DGND1­DGND3
±
0.1 V
Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL
­
0.3 V to (VDD + 0.3) V
Analog input voltage, XT1, XT2
­
0.3 V to (VCC + 0.3) V
Input current (any pins except supplies)
±
10 mA
Ambient temperature under bias
­
40
°
C to 125
°
C
Storage temperature
­55
°
C to 150
°
C
Junction temperature
150
°
C
Lead temperature (soldering)
260
°
C, 5 s
Package temperature (IR reflow, peak)
260
°
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
3
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25
°
C, VDD1
­
VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic input
CMOS compatible
VIH (1)
Input logic level
0.7VDD
3.6
Vdc
VIL (1)
Input logic level
0.3 VDD
Vdc
IIH (1)
Input logic current
VIN = VDD
65
100
µ
A
IIL (1)
Input logic current
VIN = 0 V
±
10
µ
A
Logic output
CMOS
VOH (2)
Output logic level
IOH = ­4 mA
VDD ­ 0.4 V
Vdc
VOL (2)
Output logic level
IOL = 4 mA
0.4
Vdc
PLL1707
Standard fS
32
44.1
48
PLL1707
Double fS
64
88.2
96
Sampling frequency
Half fS
16
22.05
24
kHz
Sam ling frequency
PLL1708
Standard fS
32
44.1
48
kHz
PLL1708
Double fS
64
88.2
96
MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin)
Master clock frequency
26.73
27
27.27
MHz
VIH
Input level(3)
0.7 VCC
V
VIL
Input level(3)
0.3 VCC
V
IIH
Input current(3)
VIN = VCC
±
10
µ
A
IIL
Input current(3)
VIN = 0 V
±
10
µ
A
Output voltage (4)
3.5
Vp-p
Output rise time
20% to 80% of VDD
2.0
ns
Output fall time
80% to 20% of VDD
2.0
ns
Duty cycle
For crystal oscillation
45%
51%
55%
Duty cycle
For external clock
50%
Clock jitter (5)
50
ps
Power-up time (6)
0.5
1.5
ms
PLL AC CHARACTERISTICS (SCKO0­SCKO3) (fM = 27 MHz, CL = 20 pF on measurement pin)
SCKO0
Fixed
33.8688
SCKO1
PLL1707
Selectable for 48 kHz
24.576
36.864
SCKO2
PLL1707
256 fS
8.192
12.288
24.576
SCKO3
Output system clock
384 fS
12.288
18.432
36.864
MHz
SCKO0
Out ut system clock
frequency
Fixed
33.8688
MHz
SCKO1
q
y
PLL1708
Selectable for 48 kHz
12.288
24.576
36.864
SCKO2
PLL1708
256 fS
4.096
12.288
24.576
SCKO3
384 fS
6.144
18.432
36.864
Output rise time
20% to 80% of VDD
2.0
ns
Output fall time
80% to 20% of VDD
2.0
ns
Output duty cycle
45
50
55
%
(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
(2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
(3) Pin 10: XT1
(4) Pin 11: XT2
(5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6) The delay time from power on to oscillation
(7) The settling time when the sampling frequency is changed
(8) The delay time from power on to lockup
(9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25
°
C, VDD1
­
VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETER
UNIT
MAX
TYP
MIN
TEST CONDITIONS
Output clock jitter (5)
SCKO0, SCKO1
58
100
ps
Output clock jitter (5)
SCKO2, SCKO3
50
100
ps
Frequency Settling Time(7)
PLL1707, to stated output frequency
50
150
ns
Frequency Settling Time(7)
PLL1708, to stated output frequency
80
300
ns
Power-up time (8)
To stated output frequency
3
6
ms
POWER SUPPLY REQUIREMENTS
VCC, VDD
Supply voltage range
2.7
3.3
3.6
Vdc
IDD + ICC
Supply current (9)
VDD = VCC = 3.3 V, fS = 48 kHz
19
25
mA
IDD + ICC
Supply current (9)
Power down(10)
350
550
µ
A
Power dissipation
VDD = VCC = 3.3 V, fS = 48 kHz
63
90
mW
TEMPERATURE RANGE
Operating temperature
­25
85
°
C
JA
Thermal resistance
PLL1707/8DBQ: 20-pin SSOP (150 mil)
150
°
C/W
(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
(2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
(3) Pin 10: XT1
(4) Pin 11: XT2
(5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6) The delay time from power on to oscillation
(7) The settling time when the sampling frequency is changed
(8) The delay time from power on to lockup
(9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
V
CC
AGND
XT1
V
DD
3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
V
DD
2
CSEL
XT2
PLL1707
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
1
SCKO2
SCKO3
DGND1
MD
MC
MS
V
CC
AGND
XT1
V
DD
3
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
V
DD
2
CSEL
XT2
PLL1708
(TOP VIEW)
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
5
PLL1707 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
9
­
Analog ground
CSEL
12
I
SCKO1 frequency selection control(1)
DGND1
4
­
Digital ground 1
DGND2
16
­
Digital ground 2
DGND3
17
­
Digital ground 3
FS1
5
I
Sampling frequency group control 1(1)
FS2
6
I
Sampling frequency group control 2(1)
MCKO1
14
O
27-MHz master clock output 1
MCKO2
15
O
27-MHz master clock output 2
SCKO0
18
O
System clock output 0 (33.8688 MHz fixed)
SCKO1
19
O
System clock output 1 (selectable for 48 kHz)
SCKO2
2
O
System clock output 2 (256 fS selectable)
SCKO3
3
O
System clock output 3 (384 fS selectable)
SR
7
I
Sampling rate control(1)
VCC
8
­
Analog power supply, 3.3 V
VDD1
1
­
Digital power supply 1, 3.3 V
VDD2
13
­
Digital power supply 2, 3.3 V
VDD3
20
­
Digital power supply 3, 3.3 V
XT1
10
I
27-MHz crystal oscillator, or external clock input
XT2
11
O
27-MHz crystal oscillator, must be OPEN for external clock input mode
(1) Schmitt-trigger input with internal pulldown.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
6
PLL1708 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
9
­
Analog ground
CSEL
12
I
SCKO1 frequency selection control(1)
DGND1
4
­
Digital ground 1
DGND2
16
­
Digital ground 2
DGND3
17
­
Digital ground 3
MC
6
I
Bit clock input for serial control(1)
MCKO1
14
O
27-MHz master clock output 1
MCKO2
15
O
27-MHz master clock output 2
MD
5
I
Data input for serial control(1)
MS
7
I
Chip select input for serial control(1)
SCKO0
18
O
System clock output 0 (33.8688 MHz fixed)
SCKO1
19
O
System clock output 1 (selectable for 48 kHz)
SCKO2
2
O
System clock output 2 (256 fS selectable)
SCKO3
3
O
System clock output 3 (384 fS selectable)
VCC
8
­
Analog power supply, 3.3 V
VDD1
1
­
Digital power supply 1, 3.3 V
VDD2
13
­
Digital power supply 2, 3.3 V
VDD3
20
­
Digital power supply 3, 3.3 V
XT1
10
I
27-MHz crystal oscillator, or external clock input
XT2
11
O
27-MHz crystal oscillator, must be OPEN for external clock input mode
(1) Schmitt-trigger input with internal pulldown.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
7
TYPICAL PERFORMANCE CURVES
fS ­ Sampling Frequency ­ kHz
40
45
50
55
60
65
70
30
40
50
60
70
80
90
100
Jitter
­
psrms
JITTER
vs
SAMPLING FREQUENCY
Figure 1
MCKO1
MCKO2
SCKO0
SCKO1
SCKO3
SCKO2
CL ­ Load Capacitance ­ pF
40
45
50
55
60
65
70
0
5
10
15
20
Jitter
­
psrms
JITTER
vs
LOAD CAPACITANCE
SCKO0
MCKO1
SCKO2
MCKO2
Figure 2
SCKO1
SCKO3
40
45
50
55
60
65
70
2.7
3.0
3.3
3.6
VCC ­ Supply Voltage ­ V
Jitter
­
psrms
JITTER
vs
SUPPLY VOLTAGE
SCKO0
SCKO3
MCKO1
MCKO2
SCKO1
Figure 3
SCKO2
Figure 4
40
45
50
55
60
65
70
­50
­25
0
25
50
75
100
TA ­ Free-Air Temperature ­
°
C
Jitter
­
psrms
JITTER
vs
FREE-AIR TEMPERATURE
SCKO0
SCKO1
SCKO3
MCKO1
MCKO2
SCKO2
NOTE: All specifications at TA = 25
°
C, VDD1
­
3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency
(33.8688 MHz for SCKO0, 36.864 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin,
unless otherwise noted.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
8
Figure 5
VCC ­ Supply Voltage ­ V
Duty Cycle
­
%
DUTY CYCLE
vs
SUPPLY VOLTAGE
45
46
47
48
49
50
51
52
53
54
55
2.7
3.0
3.3
3.6
MCKO1
SCKO1
SCKO2
SCKO3
SCKO0
MCKO2
Figure 6
TA ­ Free-Air Temperature ­
°
C
Duty Cycle
­
%
DUTY CYCLE
vs
FREE-AIR TEMPERATURE
45
46
47
48
49
50
51
52
53
54
55
­50
­25
0
25
50
75
100
SCKO3
MCKO1
MCKO2
SCKO1
SCKO2
SCKO0
NOTE: All specifications at TA = 25
°
C, VDD1
­
3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency
(33.8688 MHz for SCKO0, 36.864 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin,
unless otherwise noted.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
9
THEORY OF OPERATION
MASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1707/8 consists of a dual PLL clock and master clock generator which generates four system clocks and two
buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707/8. The PLL is
designed to accept a 27-MHz master clock.
PLL2
Counter N
Phase Detector
and
Loop Filter
OSC
Divider
SCKO3
384 fS
SCKO0­3
Frequency
Control
Counter M
VCO
Divider
PLL1
Counter M
Phase Detector
and
Loop Filter
Counter N
VCO
SCKO2
256 fS
Divider
SCKO1
36.864/24.576 MHz
(36.864/24.576 MHz)
(18.432/12.288 MHz)
SCKO0
33.8688 MHz
MCKO2
27 MHz
MCKO1
27 MHz
XT1 XT2
( ): PLL1708
Figure 7. Block Diagram
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
10
The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to
XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,
and Figure 9 illustrates the 27-MHz master clock timing requirement.
Crystal
PLL1707/PLL1708
Crystal
OSC
Circuit
27-MHz
Internal
Master
Clock
XT1
XT2
C2
C1
MCKO1
MCKO2
C1, C2 = 10 pF to 33 pF
Crystal Resonator Connection
PLL1707/PLL1708
XT1
XT2
MCKO1
MCKO2
External Clock Input Connection
External
Clock
Crystal
OSC
Circuit
27-MHz
Internal
Master
Clock
Figure 8. Master Clock Generator Connection Diagram
t(XT1H)
XT1
t(XT1L)
0.7 VCC
0.3 VCC
DESCRIPTION
SYMBOL
MIN
MAX
UNIT
Master clock pulse duration HIGH
t(
XT1H)
10
ns
Master clock pulse duration LOW
t(
XT1L)
10
ns
Figure 9. External Master Clock Timing Requirement
The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs
256 f
S,
384 f
S
512 f
S,
or 768 f
S
(f
S
= 48 kHz) which is selected by hardware or software control. The output frequency of
the remaining clocks is determined by the sampling frequency (f
S
) under hardware or software control. SCKO2 and SCKO3
output 256-f
S
and 384-f
S
system clocks, respectively. Table 2 shows each sampling frequency which can be programmed.
The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling
frequencies on SCKO2 and SCKO3 and 256 f
S
and 384 f
S
on SCKO1 are supported only on the PLL1708.
Table 1. Generated System Clock SCKO1 Frequency
fS
SCKO1 FREQUENCY
256 fS
12.288 MHz
384 fS
18.432 MHz
512 fS
24.576 MHz
768 fS
36.864 MHz
PLL1708 only
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
11
Table 2. Sampling Frequencies
SAMPLING RATE
SAMPLING FREQUENCY (kHz)
Half sampling frequencies
16
22.05
24
Standard sampling frequencies
32
44.1
48
Double sampling frequencies
64
88.2
96
PLL1708 only
Table 3. Sampling Frequencies and System Clock Output Frequencies
SAMPLING FREQUENCY (kHz)
SAMPLING RATE
256 fS
SCKO2 (MHZ)
384 fS
SCKO3 (MHZ)
16
Half
4.096
6.144
22.05
Half
5.6448
8.4672
24
Half
6.144
9.216
32
Standard
8.192
12.288
44.1
Standard
11.2896
16.9344
48
Standard
12.288
18.432
64
Double
16.384
24.576
88.2
Double
22.5792
33.8688
96
Double
24.576
36.864
PLL1708 only
Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from
sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the
PLL1708.
SCKO0
SCKO1
300 ns
SCKO2
SCKO3
MS
Stable
Clock Transition Region
Stable
33.8688 , 36.864, or 24.576 MHz
1­2 Clocks of MCKO1, 2
Figure 10. System Clock Transient Timing
The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient
timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on
all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
12
SCKO0
150 ns
SCKO1
SCKO2
SCKO3
FS2, 1
Stable
Clock Transition Region
Stable
33.8688 MHz
SR
CSEL
50 ns
Figure 11. SCKO Transient Timing
POWER-ON RESET
The PLL1707/8 has an internal power-on reset circuit. The mode register of the PLL1708 is initialized with default settings
by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time.
Initialization by internal power-on reset is done automatically during 1024 master clocks at V
DD
> 2.0 V (TYP). Power-on
reset timing is shown in Figure 12.
Reset
Reset Removal
1024 Master Clocks
VDD
2.4 V
2.0 V
1.6 V
Internal Reset
Master Clock
Figure 12. Power-On Reset Timing
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
13
FUNCTION CONTROL
The built-in functions of the PLL1707 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1
(pin 5) and FS2 (pin 6). The PLL1708 can be controlled in the serial mode (software mode), which has a three-wire interface
using MS (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.
Table 4. Selectable Functions
SELECTABLE FUNCTION
PARALLEL MODE
SERIAL MODE
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Yes
Yes
Sampling rate select (standard/double)
Yes
Yes
Sampling rate select (half)
No
Yes
Each clock output enable/disable
No
Yes
Power down
No
Yes
SCKO1 configuration
No
Yes
PLL1707 (Parallel Mode)
In the parallel mode, the following functions can be selected:
Sampling Frequency Group Select
The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).
FS2 (PIN 6)
FS1 (PIN 5)
SAMPLING FREQUENCY
LOW
LOW
48 kHz
LOW
HIGH
44.1 kHz
HIGH
LOW
32 kHz
HIGH
HIGH
Reserved
Sampling Rate Select
The sampling rate can be selected by SR (pin 7)
SR (PIN 7)
SAMPLING RATE
LOW
Standard
HIGH
Double
System Clock SCKO1 Frequency Select
System clock SCKO1 frequency can be selected by CSEL (pin 12).
CSEL (PIN 12)
SCKO1 FREQUENCY
LOW
36.864 MHz
HIGH
24.576 MHz
PLL1708 (Serial Mode)
The built-in functions of the PLL1708 are shown in Table 5. These functions are controlled using the MS, MC, and MD serial
control signals.
Table 5. Selectable Functions
SELECTABLE FUNCTION
DEFAULT
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
48-kHz group
Sampling rate select (half, standard, double)
Standard
Each clock output enable/disable
Enabled
Power down
Disabled
SCKO1 configuration
36.864 MHz, 24.576 MHz
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
14
Program-Register Bit Mapping
The built-in functions of the PLL1708 are controlled through a 16-bit program register. This register is loaded using MD,
MC and MS. After the 16 data bits are clocked in using the rising edge of MC, MS is used to latch the data into the register.
Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in
Figure 13 and Figure 14, respectively.
MS
MC
MD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 13. Serial Mode Control Format
t(MSL)
VDD/2
MC
MD
MSB
MS
t(MHH)
VDD/2
VDD/2
t(MSS)
t(MSH)
t(MCL)
t(MCH)
LSB
t(MDH)
t(MCY)
t(MDS)
t(MSS)
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNIT
MC pulse cycle time
t(MCY)
100
ns
MC pulse duration LOW
t(MCL)
40
ns
MC pulse duration HIGH
t(MCH)
40
ns
MD hold time
t(MDH)
40
ns
MD setup time
t(MDS)
40
ns
MS low-level time
t(MSL)
16
MC clocks(1)
MS high-level time
t(MHH)
200
ns
MS hold time(2)
t(MSH)
40
ns
MS setup time(3)
t(MSS)
40
ns
(1) MC clocks: MC clock period
(2) MC rising edge for LSB to MS rising edge
(3) MS rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any MS rise time is accepted.
Figure 14. Control Data Input Timing
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
15
Mode Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
CE6
CE5
CE4
CE3
CE2
CE1
SR2
SR1
FS2
FS1
Table 6. Mode Register Mapping
REGISTER
BIT NAME
DESCRIPTION
CE6
MCKO2 output enable/disable
CE5
MCKO1 output enable/disable
CE4
SCKO1 output enable/disable
Mode control
CE3
SCKO3 output enable/disable
Mode control
CE2
SCKO2 output enable/disable
CE1
SCKO0 output enable/disable
SR[2:1]
Sampling rate select
FS[2:1]
Sampling frequency select
FS[2:1]: Sampling Frequency Group Select
FS2
FS1
SAMPLING FREQUENCY
0
0
48 kHz (default)
0
1
44.1 kHz
1
0
32 kHz
1
1
Reserved
SR[2:1]: Sampling Rate Select
SR2
SR1
SAMPLING RATE
0
0
Standard (default)
0
1
Double
1
0
Half
1
1
Reserved
CE [6:1]: Clock Output Control
CE1­CE6
CLOCK OUTPUT CONTROL
0
Clock output disable
1
Clock output enable (default)
While all the bits of CE [6:1] are 0, the PLL1708 goes into the power-down mode, all dynamic operation including PLLs
and the oscillator halts, but serial mode control is enabled for resumption.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
16
Configuration Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
1
RSV
RSV
RSV
RSV
RSV
CFG1
RSV
RSV
RSV
RSV
Table 7. Configuration Register Mapping
REGISTER
BIT NAME
DESCRIPTION
Configuration
RSV
Reserved, must be 0
Configuration
CFG1
SCKO1 configuration
CFG1: SCKO1 Configuration Control
CFG1
CONFIGURATION 1
0
36.864 MHz, 24.576 MHz for SCKO1 (default)
1
18.432 MHz, 12.288 MHz for SCKO1
The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register).
CFG1
(REGISTER)
CSEL
(PIN 12)
SCKO1
0
LOW
36.864 MHz
0
HIGH
24.576 MHz
1
LOW
18.432 MHz
1
HIGH
12.288 MHz
CONNECTION DIAGRAM
Figure 15 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog power
supplies. However, the use of one common ground connection is recommended to avoid latch-up or other
power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.
MPEG-2 APPLICATIONS
Typical applications for the PLL1707/8 are MPEG-2 based systems such as DVD recorders, HDD recorders, DVD players,
DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1707/8 provides audio system
clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
17
SR(MS)
FS1 (MD)
16
15
14
13
12
11
5
6
7
8
9
10
PLL1707/8
FS2 (MC)
VCC
AGND
XT1
DGND2
MCKO2
MCKO1
VDD2
CSEL
XT2
VDD1
1
2
3
4
SCKO2
SCKO3
DGND1
20
19
18
17
VDD3
SCKO1
SCKO0
DGND3
3.3 V
(1)
(1)
(2)
(4)
(3)
(3)
(1)
(2)
Clock Outputs (5)
(1)
(1) 0.1-
µ
F ceramic capacitor typical, depending on quality of power supply and pattern layout
(2) 10-
µ
F aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout
(3) 27-MHz quartz crystal and 10­33 pF
×
2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2
(4) This connection is for PLL1707 (parallel mode); when PLL1708 (serial mode) is to be used, control pins must be connected to serial interfaced
controller.
(5) For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock outputs through buffers,
especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual interference by separating them or inserting a guard pattern
between them.
Figure 15. Typical Connection Diagram
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
18
BLOCK DIAGRAM OF DVD PLAYER APPLICATION
SCKO3
SCKO2
SCKO0
MCKO1/2
PLL1707/8
384 fS
256 fS
27 MHz
27 MHz
Crystal
PCM/DSD1608
Down Mix
CD-DA/
DVD DSP
MPEG/AC-3
Audio Decoder
Front
Center, Subwoofer
Surround
BLOCK DIAGRAM OF HDD+DVD RECORDER APPLICATION
SCKO1
XTI
SCKO2, 3
MCKO1/2
PLL1707/8
PCM1802
PCM1742
27-MHz Master Clock
MPEG
Encoder
MPEG
Decoder
PLL1707
PLL1708
SLES065 ­ DECEMBER 2002
www.ti.com
19
MECHANICAL DATA
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4073301/F 02/02
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.035 (0,89)
0.244 (6,20)
0.228 (5,80)
1
12
24
13
0.150 (3,81)
0.157 (3,99)
0.008 (0,20) NOM
0
°
­8
°
Gauge Plane
0.012 (0,30)
0.008 (0,20)
0.197
(5,00)
(4,80)
0.189
A MAX
A MIN
PINS **
DIM
16
0.337
(8,56)
(8,74)
0.344
20
24
A
(8,74)
0.344
(8,56)
0.337
28
0.394
(10,01)
0.386
(9,80)
M0­137
VARIATION
AB
AD
AE
AF
0.025 (0,64)
0.005 (0,13)
0.004 (0,10)
D
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO­137.
MECHANICAL DATA
MSOI004E JANUARY 1995 ­ REVISED MAY 2002
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
DBQ (R­PDSO­G**) PLASTIC SMALL­OUTLINE PACKAGE
4073301/F 02/02
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.035 (0,89)
0.244 (6,20)
0.228 (5,80)
1
12
24
13
0.150 (3,81)
0.157 (3,99)
0.008 (0,20) NOM
0
°
­8
°
Gauge Plane
0.012 (0,30)
0.008 (0,20)
0.197
(5,00)
(4,80)
0.189
A MAX
A MIN
PINS **
DIM
16
0.337
(8,56)
(8,74)
0.344
20
24
A
(8,74)
0.344
(8,56)
0.337
28
0.394
(10,01)
0.386
(9,80)
M0­137
VARIATION
AB
AD
AE
AF
D
0.025 (0,64)
0.005 (0,13)
0.004 (0,10)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO­137.
MECHANICAL DATA
MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
°
­ 8
°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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