Burr Brown Products
from Texas Instruments
FEATURES
DESCRIPTION
APPLICATIONS
DAC A
DAC B
DAC C
DAC D
V
REF
L AB
V
REF
H AB
V
REF
V
REF
V
OUT
D
V
OUT
C
V
OUT
B
V
OUT
A
V
OUT
B
Sense
V
REF
L CD V
REF
H CD
SDI
SDO
Control
Logic
CS
CLOCK
RST
RESTSEL
LDAC
LOAD
AGND
DGND
V
OUT
C
Sense
V
OUT
D
Sense
V
OUT
A
Sense
V
CC
V
SS
V
DD
DAC7634
V
REF
V
REF
Shift
Register
Input
Register A
Input
Register B
Input
Register C
Input
Register D
DAC
Register A
DAC
Register B
DAC
Register C
DAC
Register D
AB Sense
L
H
AB Sense
CD Sense
CD Sense
L
H
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
16-BIT, QUAD VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
·
Low Power: 10 mW
The DAC7634 is a 16-bit, quad voltage output, digital-
to-analog converter with specified 15-bit monotonic
·
Unipolar or Bipolar Operation
performance over the specified temperature range. It
·
Settling Time: 10 µs to 0.003%
accepts 24-bit serial input data, has double-buffered
·
15-Bit Linearity and Monotonicity:
DAC input logic (allowing simultaneous update of all
40
°
C to 85
°
C
DACs), and provides
a
serial
data
output
for
daisy-chaining multiple DACs. Programmable asyn-
·
Programmable Reset to Mid-Scale
chronous reset clears all registers to a mid-scale
or Zero-Scale
code of 8000
H
or to a zero-scale of 0000
H
. The
·
Double-Buffered Data Inputs
DAC7634 can operate from a single 5-V supply or
from 5-V and 5 V supplies.
Low power and small size per DAC make the
·
Process Control
DAC7634
ideal
for
automatic
test
equipment,
·
Closed-Loop Servo-Control
DAC-per-pin programmers, data acquisition systems,
·
Motor Control
and closed-loop servo-control. The DAC7634 is avail-
·
Data Acquisition Systems
able in a 48-lead SSOP package and offers specifi-
cations over the 40
°
C to 85
°
C temperature range.
·
DAC-Per-Pin Programmers
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
SPECIFICATIONS
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
LINEARITY
DIFFERENTIAL
PACKAGE
SPECIFICATION
ORDERING
TRANSPORT
PRODUCT
ERROR
NONLINEARITY
PACKAGE
DRAWING
TEMPERATURE
NUMBER
(1)
MEDIA
(LSB)
(LSB)
NUMBER
RANGE
DAC7634E
Rails
DAC7634E
±
4
±
3
48-Lead SSOP
333
40
°
C to 85
°
C
DAC7634E/1K
Tape and Reel
DAC7634EB
Rails
DAC7634EB
±
3
±
2
48-Lead SSOP
333
40
°
C to 85
°
C
DAC7634E/1K
Tape and Reel
(1)
Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel).
Ordering 1000 pieces of DAC7634E/1K will get a single 1000-piece Tape and Reel.
UNIT
V
CC
and V
DD
to V
SS
0.3 V to 11 V
V
CC
and V
DD
to GND
0.3 V to 5.5 V
V
REF
L to V
SS
0.3 V to (V
CC
- V
SS
)
V
CC
to V
REF
H
0.3 V to (V
CC
- V
SS
)
V
REF
H to V
REF
L
0.3 V to (V
CC
- V
SS
)
Digital input voltage to GND
0.3 V to V
DD
+ 0.3 V
Digital output voltage to GND
0.3 V to V
DD
+ 0.3 V
T
J
Maximum junction temperature
150
°
C
T
A
Operating temperature range
40
°
C to 85
°
C
T
stg
Storage temperature range
65
°
C to 125
°
C
Lead temperature (solder, 10s)
300
°
C
(1)
Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= 5 V, V
SS
= 5 V, V
REF
H = 2.5 V, and V
REF
L = 2.5 V, unless otherwise noted
DAC7634E
DAC7634EB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ACCURACY
Linearity error
±
3
±
4
±
2
±
3
LSB
Linearity match
±
4
±
2
LSB
Differential linearity error
±
2
±
3
±
1
±
2
LSB
Monotonicity, T
MIN
to T
MAX
14
15
Bits
Bipolar zero error
±
1
±
2
±
1
±
2
mV
Bipolar zero error drift
5
10
5
10
ppm/
°
C
Full-scale error
±
1
±
2
±
1
±
2
mV
Full-scale error drift
5
10
5
10
ppm/
°
C
Channel-to-channel
Bipolar zero matching
±
1
±
2
±
1
±
2
mV
matching
Channel-to-channel
Full-scale matching
±
1
±
2
±
1
±
2
mV
matching
Power supply rejection ratio (PSRR)
At full scale
10
100
10
100
ppm/V
2
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DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
SPECIFICATIONS (continued)
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= 5 V, V
SS
= 5 V, V
REF
H = 2.5 V, and V
REF
L = 2.5 V, unless otherwise noted
DAC7634E
DAC7634EB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ANALOG INPUT
Voltage output
V
REF
L
V
REF
H
V
REF
L
V
REF
H
V
V
REF
= 2.5 V, R
L
= 10 k
,
V
SS
= 5 V
Output current
1.25
1.25
1.25
1.25
mA
Maximum load capacitance
No oscillation
500
500
pF
Short-circuit current
10, 30
10, +30
mA
Short-circuit duration
GND or V
CC
or V
SS
Indefinite
Indefinite
REFERENCE INPUT
V
REF
L
V
REF
L
Ref high input voltage range
2.5
2.5
V
+1.25
+1.25
V
REF
H
V
REF
H
Ref low input voltage range
2.5
2.5
V
1.25
1.25
Ref high input current
500
500
µA
Ref low input current
500
500
µA
DYNAMIC PERFORMANCE
Settling time
To
±
0.003%, 5-V output step
8
10
8
10
µs
Channel-to-channel crosstalk
See Figure 5
0.5
0.5
LSB
Digital feedthrough
2
2
nV-s
Output noise voltage
f = 10 kHz
60
60
nV/
Hz
7FFF
H
to 8000
H
or
DAC glitch
40
40
nV-s
8000
H
to 7FFF
H
DIGITAL INPUT
V
IH
0.7
×
V
DD
0.7
×
V
DD
V
V
IL
0.3
×
V
DD
0.3
×
V
DD
V
I
IH
±
10
±
10
µA
I
IL
±
10
±
10
µA
DIGITAL OUTPUT
V
OH
I
OH
= 0.8 mA
3.6
4.5
3.6
4.5
V
V
OL
I
OL
= 1.6 mA
0.3
0.4
0.3
0.4
V
POWER SUPPLY
V
DD
4.75
5.0
5.25
4.75
5.0
5.25
V
V
CC
4.75
5.0
5.25
4.75
5.0
5.25
V
V
SS
5.25
5.0
4.75
5.25
5.0
4.75
V
I
CC
1.5
2
1.5
2
mA
I
DD
50
50
µA
I
SS
2.3
1.5
2.3
1.5
mA
Power
15
20
15
20
mW
3
www.ti.com
SPECIFICATIONS
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= 5 V, V
SS
= 0 V, V
REF
H = 2.5 V, and V
REF
L = 0 V, unless otherwise noted
DAC7634E
DAC7634EB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ACCURACY
Linearity error
(1)
±
3
±
4
±
2
±
3
LSB
Linearity match
±
4
±
2
LSB
Differential linearity error
±
2
±
3
±
1
±
2
LSB
Monotonicity, T
MIN
to T
MAX
14
15
Bits
Zero-scale error
±
1
±
2
±
1
±
2
mV
Zero-scale error drift
5
10
5
10
ppm/
°
C
Full-scale error
±
1
±
2
±
1
±
2
mV
Full-scale error drift
5
10
5
10
ppm/
°
C
Zero-scale matching
Channel-to-channel matching
±
1
±
2
±
1
±
2
mV
Full-scale matching
Channel-to-channel matching
±
1
±
2
±
1
±
2
mV
Power supply rejection ratio (PSRR)
At full scale
10
100
10
100
ppm/V
ANALOG INPUT
Voltage output
0
V
REF
H
0
V
REF
H
V
V
REF
L = 0 V, V
SS
= 0 V,
R
L
= 10 k
Output current
1.25
1.25
1.25
1.25
mA
Maximum load capacitance
No oscillation
500
500
pF
Short-circuit current
±
30
±
30
mA
Short-circuit duration
GND or V
CC
Indefinite
Indefinite
REFERENCE INPUT
V
REF
L
V
REF
L
Ref high input voltage range
2.5
2.5
V
+1.25
+1.25
V
REF
H
V
REF
H
Ref low input voltage range
0
0
V
1.25
1.25
Ref high input current
250
250
µA
Ref low input current
250
250
µA
DYNAMIC PERFORMANCE
Settling time
To
±
0.003%, 2.5-V output step
8
10
8
10
µs
Channel-to-channel crosstalk
See Figure 6
0.5
0.5
LSB
Digital feedthrough
2
2
nV-s
Output noise voltage
f = 10 kHz
60
60
nV/
Hz
7FFF
H
to 8000
H
or
DAC glitch
40
40
nV-s
8000
H
to 7FFF
H
DIGITAL INPUT
V
IH
0.7
×
V
DD
0.7
×
V
DD
V
V
IL
0.3
×
V
DD
0.3
×
V
DD
V
I
IH
±
10
±
10
µA
I
IL
±
10
±
10
µA
DIGITAL OUTPUT
V
OH
I
OH
= 0.8 mA
3.6
4.5
3.6
4.5
V
V
OL
I
OL
= 1.6 mA
0.3
0.4
0.3
0.4
V
POWER SUPPLY
V
DD
4.75
5.0
5.25
4.75
5.0
5.25
V
V
CC
4.75
5.0
5.25
4.75
5.0
5.25
V
V
SS
0
0
0
0
0
0
V
I
CC
1.5
2
1.5
2
mA
I
DD
50
50
µA
Power
7.5
10
7.5
10
mW
(1)
If V
SS
= 0 V specification applies at Code 0040
H
and above due to possible negative zero-scale error.
4
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DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
NC
No connection
25
V
CC
Analog +5-V power supply
2
NC
No connection
26
V
CC
Analog +5-V power supply
3
SDI
Serial data input
27
AGND
Analog ground
4
DGND
Digital ground
28
AGND
Analog ground
5
CLK
Data clock input
29
V
SS
Analog +5-V power supply or 0-V single supply
6
DGND
Digital ground
30
V
SS
Analog +5-V power supply or 0-V single supply
7
LDAC
DAC register load control, rising edge triggered
31
V
OUT
D
DAC D output voltage
DAC D's output amplifier inverting input. Used to close
8
DGND
Digital ground
32
V
OUT
D Sense
feedback loop at load.
9
LOAD
DAC input register load control, active low
33
V
REF
L CD Sense
DAC C and D reference low sense input
10
DGND
Digital ground
34
V
REF
L CD
DAC C and D reference low input
11
CS
Chip select, active low
35
V
REF
H CD
DAC C and D reference high input
12
DGND
Digital ground
36
V
REF
H CD Sense
DAC C and D reference high sense input
13
SDO
Serial data output
37
V
OUT
C
DAC C output voltage
DAC C's output amplifier inverting input. Used to close
14
DGND
Digital ground
38
V
OUT
C Sense
the feedback loop at the load.
Reset Select. Determines the action of RST. If
HIGH, a RST common sets the DAC registers to
15
RSTSEL
39
V
OUT
B
DAC B output voltage
mid-scale (8000
H
). If LOW, a RST command sets
the DAC registers to zero (0000
H
).
DAC B's output amplifier inverting input. Used to close
16
DGND
Digital ground
40
V
OUT
B Sense
the feedback loop at the load.
Reset, rising edge triggered. Depending on the
17
RST
state of RSTSEL, the DAC registers are set to
41
V
REF
H AB Sense
DAC A and B reference high sense input
either mid-scale or zero.
18
DGND
Digital ground
42
V
REF
H AB
DAC A and B reference high input
19
NC
No connection
43
V
REF
L AB
DAC A and B reference low input
20
NC
No connection
44
V
REF
L AB Sense
DAC A and B reference low sense input
21
DGND
Digital ground
45
V
SS
Analog 5-V power supply or 0-V single supply
22
DGND
Digital ground
46
AGND
Analog ground
23
V
DD
Digital 5-V power supply
47
V
OUT
A
DAC A output voltage
DAC A's output amplifier inverting input. Used to close
24
V
DD
Digital 5-V power supply
48
V
OUT
A Sense
the feedback loop at the load.
5
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PIN CONFIGURATION
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
V
DD
V
DD
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
V
SS
AGND
AGND
V
CC
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DAC7634
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
6
www.ti.com
TYPICAL PERFORMANCE CURVES: V
SS
= 0 V
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25
°
C)
(DAC B, 25
°
C)
Figure 1.
Figure 2.
LINEARY ERROR AND
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25
°
C)
(DAC D, 25
°
C)
Figure 3.
Figure 4.
7
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LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 0 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
LINEARY ERROR AND
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 85
°
C)
(DAC B, 85
°
C)
Figure 5.
Figure 6.
LINEARY ERROR AND
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 85
°
C)
(DAC D, 85
°
C)
Figure 7.
Figure 8.
8
www.ti.com
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
Digital Input Code
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2
1.5
1
0.5
0
0.5
1
1.5
2
Zero-Scale Error (mV)
40 30
10
0
20
10
20
40
50
30
70
80
90
60
Code (0040
H
)
DAC C
DAC B
DAC D
DAC A
Temperature - (
°
C)
2
1.5
1
0.5
0
0.5
1
1.5
2
Positive Full-Scale Error (mV)
Code (FFFF
H
)
40 30
10
0
20
10
20
40
50
30
70
80
90
60
DAC C
DAC A
DAC B
DAC D
Temperature - (
°
C)
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 0 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
LINEARY ERROR AND
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 40
°
C)
(DAC B, 40
°
C)
Figure 9.
Figure 10.
LINEARY ERROR AND
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 40
°
C)
(DAC D, 40
°
C)
Figure 11.
Figure 12.
ZERO-SCALE ERROR vs TEMPERATURE
FULL-SCALE ERROR vs TEMPERATURE
Figure 13.
Figure 14.
9
www.ti.com
0.00
0.05
0.10
0.15
0.20
0.25
0.30
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0.30
0.25
0.20
0.15
0.10
0.05
0.00
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2
1.5
1
0.5
0
I
CC
(mA)
Temperature
°
C)
40 30
10
0
20
10
20
40
50
30
70
80
90
60
Data = FFFF
H
No Load
(all DACs)
2
1.5
1
0.5
0
Digital Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000H FFFF
H
I
CC
(mA)
No Load
All DACs
One DAC
+5V
LDAC
0
Output V
oltage
Large-Signal Settling Time: 0.5V/div
Small-Signal Settling Time: 4LSB/div
Time (2
µ
s/div)
Output V
oltage
+5V
LDAC
0
Large-Signal Settling Time: 0.5V/div
Small-Signal Settling Time: 4LSB/div
Time (2
µ
s/div)
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 0 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
V
REFH
CURRENT vs CODE
V
REFL
CURRENT vs CODE
(ALL DACs SENT TO INDICATED CODE)
(ALL DACs SENT TO INDICATED CODE)
Figure 15.
Figure 16.
POWER SUPPLY CURRENT
POSITIVE SUPPLY CURRENT
vs TEMPERATURE
vs DIGITAL INPUT CODE
Figure 17.
Figure 18.
OUTPUT VOLTAGE vs SETTLING TIME
OUTPUT VOLTAGE vs SETTLING TIME
(0 V TO 2.5 V)
(2.5 V TO 2 mV)
Figure 19.
Figure 20.
10
www.ti.com
Output V
oltage (50mV/div)
+5V
LDAC
0
8000
H
to 7FFF
H
Time (1
µ
s/div)
Output V
oltage (50mV/div)
+5V
LDAC
0
7FFF
H
to 8000
H
Time (1
µ
s/div)
Time (10
µ
s/div)
Noise V
oltage (50
µ
V/div)
H
1000
100
10
Frequency (Hz)
10
100
1000
10000
100000
1000000
Noise (nV/
Hz)
5
4
3
2
1
0
R
LOAD
(k
)
0.001
0.01
0.1
1
10
100
1000
V
OUT
(V)
Source
Sink
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 0 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
vs MIDSCALE GLITCH PERFORMANCE
Figure 21.
Figure 22.
BROADBAND NOISE
OUTPUT NOISE VOLTAGE vs FREQUENCY
Figure 23.
Figure 24.
V
OUT
vs
R
LOAD
Figure 25.
11
www.ti.com
TYPICAL PERFORMANCE CURVES: V
SS
= 5 V
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25
°
C)
(DAC B, 25
°
C)
Figure 26.
Figure 27.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25
°
C)
(DAC D, 25
°
C)
Figure 28.
Figure 29.
12
www.ti.com
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 5 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 85
°
C)
(DAC B, 85
°
C)
Figure 30.
Figure 31.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 85
°
C)
(DAC D, 85
°
C)
Figure 32.
Figure 33.
13
www.ti.com
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 5 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 40
°
C)
(DAC B, 40
°
C)
Figure 34.
Figure 35.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 40
°
C)
(DAC D, 40
°
C)
Figure 36.
Figure 37.
14
www.ti.com
+0.6
+0.5
+0.4
+0.3
+0.2
+0.1
0.0
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0.0
0.1
0.2
0.3
0.4
0.5
0.6
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2
1.5
1
0.5
0
0.5
1
1.5
2
Zero-Scale Error (mV)
40 30
10
0
20
10
20
40
50
30
70
80
90
60
DAC A
DAC B
DAC D
DAC C
Temperature - (
°
C)
2
1.5
1
0.5
0
0.5
1
1.5
2
Positive Full-Scale Error (mV)
40 30
10
0
20
10
20
40
50
30
70
80
90
60
DAC B
DAC A
DAC D
DAC C
Temperature - (
°
C)
3
2
1
0
1
2
3
I
Q
(mA)
I
CC
I
SS
40 30
10
0
20
10
20
40
50
30
70
80
90
60
Data = FFFF
H
(all DACs)
No Load
Temperature - (
°
C)
2
1.5
1
0.5
0
0.5
1
1.5
2
Negative Full-Scale Error (mV)
40 30
10
0
20
10
20
40
50
30
70
80
90
60
DAC D
DAC A
DAC B
DAC C
Temperature - (
°
C)
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 5 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
V
REFH
CURRENT vs CODE
V
REFl
CURRENT vs CODE
(ALL DACs SENT TO INDICATED CODE)
(ALL DACs SENT TO INDICATED CODE)
Figure 38.
Figure 39.
ZERO-SCALE ERROR vs TEMPERATURE
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 8000
H
)
(Code FFFF
H
)
Figure 40.
Figure 41.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
POWER SUPPLY CURRENT
(Code 0000
H
)
vs TEMPERATURE
Figure 42.
Figure 43.
15
www.ti.com
2
3
4
5
R
LOAD
(k
)
0.001
0.01
1
0.1
100
10
1000
V
OUT
(V)
Source
Sink
2
1.5
1
0.5
0
I
CC
(mA)
Digital Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
No Load
All DACs
One DAC
Output V
oltage
Large-Signal Settling Time: 1V/div
Small-Signal Settling Time:
2LSB/div
+5V
LDAC
0
Time (2
µ
s/div)
Output V
oltage
+5V
LDAC
0
Large-Signal Settling Time: 1V/div
Small-Signal Settling Time: 2LSB/div
Time (2
µ
s/div)
THEORY OF OPERATION
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES: V
SS
= 5 V (continued)
At T
A
= 25
°
C, V
DD
= V
CC
= 5 V, V
REFH
= 2.5 V, V
REFL
= 0 V, representative unit, unless otherwise specified.
POSITIVE SUPPLY CURRENT
V
OUT
vs R
LOAD
vs DIGITAL INPUT CODE
Figure 44.
Figure 45.
OUTPUT VOLTAGE vs SETTLING TIME
OUTPUT VOLTAGE vs SETTLING TIME
(2.5 V TO 2.5 V)
(2.5 V TO 2.5 V)
Figure 46.
Figure 47.
The DAC7634 is a quad voltage output, 16-bit digi-
The digital input is a 24-bit serial word that contains a
tal-to-analog converter (DAC). The architecture is an
2-bit address code for selecting one of four DACs, a
R-2R ladder configuration with the three MSBs seg-
quick load bit, five unused bits, and the 16-bit DAC
mented, followed by an operational amplifier that
code (MSB first). The converters can be powered
serves as a buffer. Each DAC has its own R-2R
from either a single 5-V supply or a dual
±
5-V supply.
ladder network, segmented MSBs, and output oper-
The device offers a reset function which immediately
ational amplifier, as shown in Figure 48. The mini-
sets all DAC output voltages and DAC registers to
mum voltage output (zero-scale) and maximum volt-
mid-scale code 8000
H
or to zero-scale, code 0000
H
.
age output (full-scale) are set by the external voltage
See Figure 49 and Figure 50 for the basic operation
references (V
REF
L and V
REF
H, respectively).
of the DAC7634.
16
www.ti.com
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
V
DD
V
DD
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
V
SS
AGND
AGND
V
CC
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7634
Reset DAC Registers
Chips Select
Serial Data Out
Serial Data In
Clock
Load DAC Registers
Load
NC = No Connection
0V to +2.5V
0V to +2.5V
0V to +2.5V
0V to +2.5V
+2.5000V
+2.5000V
+5V
0.1
F
1
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Figure 48. DAC7634 Architecture
Figure 49. Basic Single-Supply Operation of the DAC7634
17
www.ti.com
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
V
DD
V
DD
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
V
SS
AGND
AGND
V
CC
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7634
Reset DAC Registers
Chips Select
Serial Data Out
Serial Data In
Clock
Load DAC Registers
Load
NC = No Connection
2.5V to +2.5V
2.5V to +2.5V
2.5V to +2.5V
2.5V to +2.5V
+2.5V
+2.5V
2.5V
2.5V
+5V
+5V
5V
5V
+5V
+
+
1
µ
F
1
µ
F
0.1
µ
F
0.1
µ
F
0.1
µ
F
1
µ
F
ANALOG OUTPUTS
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Figure 50. Basic Dual-Supply Operation of the DAC7634
Due to the high accuracy of these D/A converters,
system design problems such as grounding and
contact resistance become important. A 16-bit con-
When V
SS
= 5V (dual supply operation), the output
verter with a 2.5 V full-scale range has a 1-LSB value
amplifier can swing to within 2.25 V of the supply
of 38 µV. With a load current of 1 mA, series wiring
rails, specified over the 40
°
C to 85
°
C temperature
and connector resistance of only 40 m
(R
W2
)
range. When V
SS
= 0 V (single-supply operation), and
causes a voltage drop of 40 µV, as shown in
with R
LOAD
also connected to ground, the output can
Figure 51. To understand what this means in terms of
swing to ground. Care must also be taken when
a system layout, the resistivity of a typical 1-ounce
measuring the zero-scale error when V
SS
= 0 V.
copper-clad printed-circuit board is 1.2 m
per
Because the output voltage cannot swing below
square. For a 1-mA load, a 10-mil wide printed-circuit
ground, the output voltage may not change for the
conductor 600 mil long results in a voltage drop of 30
first few digital input codes (0000
H
, 0001
H
, 0002
H
,
µV.
etc.) if the output amplifier has a negative offset. At
the negative limit of 2 mV, the first specified output
The DAC7634 offers a force and sense output
starts at code 0040
H
.
configuration for the high open-loop gain output
amplifier. This feature allows the loop around the
output amplifier to be closed at the load (as shown in
Figure 51), thus ensuring an accurate output voltage.
18
www.ti.com
REFERENCE INPUTS
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
R
W1
R
W2
+2.5V
+V
V
OUT
R
W1
R
W2
V
OUT
+2.5V
+V
2.5V
V
V
OUT
5V
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
1000pF
1000pF
2200pF
+V
OPA2234
V
100
100
2200pF
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
The reference inputs, V
REF
L and V
REF
H, can be any
voltage between VSS + 2.5 V and VCC 2.5 V,
provided that V
REF
H is at least 1.25 V greater than
V
REF
L. The minimum output of each DAC is equal to
V
REF
L plus a small offset voltage (essentially, the
offset of the output operational amp). The maximum
output is equal to V
REF
H plus a similar offset voltage.
Note that V
SS
(the negative power supply) must either
be connected to ground or must be in the range of
4.75 V to 5.25 V. The voltage on V
SS
sets several
bias points within the converter. If V
SS
is not in one of
these two configurations, the bias values may be in
error and proper operation of the device is not
specified.
The current into the V
REF
H input and out of V
REF
L
Figure 51. Analog Output Closed-Loop
depends on the DAC output voltages, and can vary
Configuration(1/2 DAC7634)
from a few microamps to approximately 0.5 mA. The
(R
W
Represents Wiring Resistances)
reference input appears as a varying load to the
reference. If the reference can sink or source the
required current, a reference buffer is not required.
The DAC7634 features a reference drive and sense
connection such that the internal errors caused by the
changing
reference
current
and
the
circuit
impedances can be minimized. Figure 52 through
Figure 60 show different reference configurations,
and the effect on the linearity and differential linearity.
Figure 52. Dual Supply Configuration-Buffered References, Used for Dual Supply Performance
19
www.ti.com
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
+2.5V
+V
OPA2350
98k
+0.050V
2k
V
OUT
1000pF
1000pF
2200pF
+V
100
2200pF
100
L has been chosen to be 50 mV to allow for current sinking voltage
drops across the 100-
resistor and the output stage of the buffer operational amplifier.
NOTE: V
REF
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
+2.5V
+V
+1.25V
+V
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
OPA2350
V
OUT
1000pF
1000pF
2200pF
+V
100
100
2200pF
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Figure 53. Single-Supply Buffered Reference With a Reference Low of 50 mV (1/2 DAC7634)
Figure 54. Integral Linearity and Differential Linearity
Figure 55. Integral Linearity and Differential Linearity
Error Curves for Figure 53
Error Curves for Figure 56
Figure 56. Single-Supply Buffered Reference With V
REF
L = 1.25 V and V
REF
H = 2.5 V (1/2 DAC7634)
20
www.ti.com
+V
1000pF
2200pF
100
+2.5V
OPA2350
+V
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
V
OUT
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
+2.5V
+V
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
V
OUT
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Figure 57. Single-Supply Buffered V
REF
H (1/2 DAC7634)
Figure 58. Linearity and Differential Linearity
Figure 59. Linearity and Differential Linearity
Error Curves for Figure 57
Error Curves for Figure 60
Figure 60. Low Cost Single-Supply Configuration
21
www.ti.com
DIGITAL INTERFACE
SERIAL DATA INPUT
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
The DAC code, quick load control, and address are
provided via a 24-bit serial interface (see Figure 15).
Table 1 shows the basic control logic for the
The first two bits select the input register that is
DAC7634. The interface consists of a signal data
updated when LOAD goes LOW. The third bit is a
clock (CLK) input, serial data (SDI), DAC input
Quick Load bit such that if HIGH, the code in the shift
register load control signal (LOAD), and DAC register
register is loaded into ALL DAC's input register when
load control signal (LDAC). In addition, a chip select
LOAD signal goes LOW. If the Quick Load bit is
(CS) input is available to enable serial communication
LOW, the content of shift register is loaded only to
when there are multiple serial devices. An asynchro-
the DAC input register that is addressed. The Quick
nous reset (RST) input, by the rising edge, is pro-
Load bit is followed by five unused bits. The last
vided to simplify start-up conditions, periodic resets,
sixteen bits (MSB first) are the DAC code.
or emergency resets to a known state, depending on
the status of the reset select (RSTSEL) signal.
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
QUICK
A1
A0
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOAD
Table 1. DAC7634 Logic Truth Table
(1)
INPUT
DAC
A1
A0
CS
RST
RSTSEL
LDAC
LOAD
MODE
DAC
REGISTER
REGISTER
L
L
L
H
X
X
L
Write
Hold
Write Input
A
L
H
L
H
X
X
L
Write
Hold
Write Input
B
H
L
L
H
X
X
L
Write
Hold
Write Input
C
H
H
L
H
X
X
L
Write
Hold
Write Input
D
X
X
H
H
X
H
Hold
Write
Update
All
X
X
H
H
X
H
H
Hold
Hold
Hold
All
X
X
X
L
X
X
Reset to Zero
Reset to Zero
Reset to Zero
All
X
X
X
H
X
X
Reset to Midscale
Reset to Midscale
Reset to Midscale
All
(1)
If the DAC7634 is the only device on the serial bus, the CS pin can be connected to DGND permanently, which enables the shift register
all the time. In this case, only the CLK operates the serial shift register and all other functions listed in Table 1 should be followed as
shown. The DAC updates on the rising edge of LDAC.
The internal DAC register is edge-triggered and not
Note that CS and CLK are combined with an OR
level-triggered. When the LDAC signal is transitioned
gate, which controls the serial-to-parallel shift regis-
from LOW to HIGH, the digital word currently in the
ter. These two inputs are completely interchangeable.
DAC input register is latched. The first set of registers
In addition, care must be taken with the state of CLK
(the DAC input registers) are level-triggered via the
when CS rises at the end of a serial transfer. If CLK
LOAD signal. This double-buffered architecture has
is LOW when CS rises, the OR gate provides a rising
been designed so that new data can be entered for
edge to the shift register, shifting the internal data
each DAC without disturbing the analog outputs.
one additional bit. The result will be incorrect data
When the new data has been entered into the device,
and possible selection of the wrong input register(s).
all of the DAC outputs can be updated simultaneously
If both CS and CLK are used, CS should rise only
by the rising edge of LDAC. Additionally, it allows the
when CLK is HIGH. If not, then either CS or CLK can
DAC input registers to be written to at any point, then
be used to operate the shift register. See Table 2 for
the DAC output voltages can be synchronously
more information.
changed via a trigger signal (LDAC).
22
www.ti.com
SERIAL-DATA OUTPUT
V
OUT
+
V
REF
L
)
V
REF
H
*
V
REF
L
N
65, 536
(1)
DIGITALLY-PROGRAMMABLE CURRENT
DIGITAL TIMING
DIGITAL INPUT CODING
I
OUT
+
V
REF
H
*
V
REF
L
R
SENSE
N
65, 536
)
V
REF
L R
SENSE
(2)
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Table 2. Serial Shift Register Truth Table
CS
(1)
CLK
(1)
LOAD
RST
SERIAL SHIFT REGISTER
H
(2)
X
(3)
H
H
No Change
L
(4)
L
H
H
No Change
L
(5)
H
H
Advanced One Bit
L
H
H
Advanced One Bit
H
(6)
X
L
(7)
H
No Change
H
(6)
X
H
(8)
No Change
(1)
CS and CLK are interchangeable.
(2)
H = Logic HIGH
(3)
X = Don't Care
(4)
L = Logic LOW
(5)
Positive logic transition
(6)
A HIGH value is suggested in order to avoid a false clock from advancing the shift register and
changing the shift register.
(7)
If data is clocked into the serial register while LOAD is LOW, the selected DAC register changes as
the shift register bits flow through A1 and A0. This corrupts the data in each DAC register that has
been erroneously selected.
(8)
Rising edge of RST causes no change in the contents of the serial shift register.
The Serial-Data Output (SDO) is the internal shift
register's output. For DAC7634, the SDO is a driven
output and does not require an external pull-up. Any
number of DAC7634s can be daisy-chained by con-
necting the SDO pin of one device to the SDI pin of
the following device in the chain, as shown in
SOURCE
Figure 61.
The DAC7634 offers a unique set of features that
allows a wide range of flexibility in designing appli-
cations
circuits
such
as
programmable
current
sources. The DAC7634 offers both a differential
Figure 62 and Table 3 provide detailed timing for the
reference input, as well as an open-loop configuration
digital interface of the DAC7634.
around the output amplifier. The open-loop configur-
ation around the output amplifier allows a transistor to
be placed within the loop to implement a digitally-
The DAC7634 input data is in straight binary format.
programmable, unidirectional current source. The
The output voltage is given by Equation 1.
availability
of
a
differential
reference
allows
programmability for both the full-scale and zero-scale
Where N is the digital input code. This equation does
currents. The output current is calculated as:
not include the effects of offset (zero-scale) or gain
(full-scale) errors.
23
www.ti.com
DAC7634
CLK
SDI
CS
SCK
DIN
CS
SDO
DAC7634
CLK
SDI
CS
SDO
DAC7634
CLK
SDI
CS
SDO
To
Other
Serial
Devices
A1
(LSB)
SDI
CLK
CS
LOAD
A0
D15
D1
D0
tcss
t
LD1
t
LD2
t
LDRW
t
CSH
X
X
XX
X
QUICK
LOAD
(MSB)
t
LDDD
LDAC
SDI
CLK
t
CL
t
CH
t
DS
t
DH
LDAC
RESET
V
OUT
t
S
t
RSTH
t
RSTL
t
RSSS
t
RSSH
t
S
±
1 LSB
ERROR BAND
±
1 LSB
ERROR BAND
RESETSEL
t
LDDH
t
LDDL
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Figure 61. Daisy-Chaining DAC7634
Figure 62. Serial Interface Timing
Figure 63. Data and Clock Timing
Figure 64. Reset and Output Timing
24
www.ti.com
I
OUT
+
2.5 V
*
0.5 V
125
W
N
65, 536
)
0.5 V
125
W
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Table 3. Timing Specifications (T
A
= 40
°
C to 85
°
C)
SYMBOL
DESCRIPTION
MIN
UNITS
t
DS
Data Valid to CLK Rising
10
ns
t
DH
Data Held Valid after CLK Rises
20
ns
t
CH
CLK HIGH
25
ns
t
CL
CLK LOW
25
ns
t
CSS
CS LOW to CLK Rising
15
ns
t
CSH
CLK HIGH to CS Rising
0
ns
t
LD1
LOAD HIGH to CLK Rising
10
ns
t
LD2
CLK Rising to LOAD LOW
30
ns
t
LDRW
LOAD LOW Time
30
ns
t
LDDL
LDAC LOW Time
100
ns
t
LDDH
LDAC HIGH Time
150
ns
t
RSSS
RESETSEL Valid to RESET HIGH
0
ns
t
RSSH
RESET HIGH to RESETSEL Not Valid
100
ns
t
RSTL
RESET LOW Time
10
ns
t
RSTH
RESET HIGH Time
10
ns
t
S
Settling Time
10
µs
Figure 65 shows a DAC7634 in a 4-mA to 20-mA
current output configuration. The output current can
be determined by Equation 3:
(3)
At full-scale, the output current is 16 mA, plus the 4
mA, for the zero current. At zero scale, the output
current is the offset current of 4 mA (0.5 V/125
).
25
www.ti.com
I
OUT
V
PROGRAMMED
125
I
OUT
V
PROGRAMMED
125
GND
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7634
+2.5V
OPA2350
80k
20k
1000pF
1000pF
2200pF
+V
+V
100
100
2200pF
DAC7634
SBAS134A JULY 2004 REVISED AUGUST 2004
Figure 65. 4 mA to 20 mA Digitally Controlled Current Source (1/2 DAC7634)
26
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