KSI-W002-000

1. Description

SD6830 is a remote control transmitter, consists of the optimized 4-bit CPU with ROM and
RAM. It contains power-on reset, watchdog timer and carrier frequency generator. The
SD6830 provide a various carrier frequency for encoding output of key matrix and has
built-in transistor to drive infrared LED. The SD6830 is supported with a software
development tool, which allows code development in a PC environment. It allows the user
to simulate the SD6830 on an instruction level.

2. Features

Number of basic instructions ------------------------------------- 45

Instruction cycle time (one word instruction)

At Fsys=480KHz ---------------------------------------- 16.67uS
At Fsys=455kHz ---------------------------------------- 17.58uS

Memory size

ROM --------------------------------------------------- 1024 x 8 Bits
RAM ------------------------------------------------------ 32 x 4 Bits

Input ports (D0 ~ D3, E0 ~ E3 : with pull-up resistor)

Output ports (C, G, K, F0 ~ F7)

Carrier frequency generator

Fsys/12 (1/2 duty), Fsys/12 (1/3 duty), Fsys/12 (1/4 duty),
Fsys/8 (1/2 duty), Fsys/8 (1/4 duty), Fsys/11 (4/11 duty), No carrier

Watchdog Timer

Built-in power on reset

Single power supply ------------------------------------------------ 1.8V ~ 3.6V

Power dissipation (stop mode , VDD = 3V) ----------------------- Less than 3uW

Package ------------------------------------------------------------- 20/24 DIP, 20/24 SOP

Low-power system applications such as an infrared remote controller

MASK OPTION

1. Divide ratio of the oscillator frequency

2. Whether connected infrared LED driver or not

* Descriptions of this spec sheet assume that the SD6830 include driver for infrared LED.

3. Ordering

Information

Type NO.

Marking

Package Code

SD6830P-option

DIP20

SD6830-option

SOP20

SD6830P-option

DIP24

SD6830-option

SOP24

SD6830

4BIT MICROCONTROLLER

KSI-W002-000

4. Block Diagram

Figure 4-1 Block Diagram of the SD6830

OSCOUT

Watchdog

Timer

Reset

Control

RAM

Key Input

Detector

ROM

Carrier

Frequency

Generator

Instruction

Decoder

Port

OSC

Start/Stop

Control

Test

Control

Port

OSC

Port

ALU

4
4

VSS

OSCIN

TEST

C/REM

VDD

Port

STACK

SD6830

KSI-W002-000

5. PIN Assignment and Description

5.1 PIN Assignment for 24PINS( DIP24, SOP24)

Figure 5-1. Pin Assignment of 24 Pins

5.2 PIN Description for 24 PINS

Symbol

Pin No.

I /O

Functions

I/O Type

VDD

Power Supply

VSS

Ground

TEST

INPUT

Input for test ( Normally connected to VSS )

OSCin

INPUT

Input for oscillating

OSCout

OUTPUT

Output for oscillating

C/REM

OUTPUT

1-Bit output for remote transmission

D0 - D3

5 ~ 8

INPUT

4-Bit input for key sense ( with pull-up resistor )

E0 - E3

9 ~ 12

INPUT

4-Bit input for key sense ( with pull-up resistor )

F0 - F7

20 ~ 13

OUTPUT

1-Bit individual output for key scan

OUTPUT

1-Bit output

OUTPUT

1-Bit output

SD6830

TEST

OSCIN

VSS

OSCOUT

VDD

C/REM

OUTLINE 24 PIN

DMC6830

SD 6830

SD6830

KSI-W002-000

5.3 PIN Assignment for 20PINS( DIP20, SOP20)

Figure 5-3. Pin Assignment of 20Pin

5.4 PIN Description for 20 PINS

Symbol

Pin No.

I /O

Functions

I/O Type

VDD

Power Supply

VSS

Ground

TEST

INPUT

Input for test ( Normally connected to VSS )

OSCin

INPUT

Input for oscillating

OSCout

OUTPUT

Output for oscillating

C/REM

OUTPUT

1-Bit output for remote transmission

D0 - D3

4 ~ 7

INPUT

4-Bit input for key scan ( with pull-up resistor )

E0 E1

8 ~ 9

INPUT

2-Bit input for key scan ( with pull-up resistor )

F0 F6

16 ~ 10

OUTPUT

1-Bit individual output for key scan

OUTPUT

1-Bit output

SD6830

TEST

OSCIN

VSS

OSCOUT

VDD

C/REM

OUTLINE 20 PIN

DMC6830

SD 6830

SD6830

KSI-W002-000

5.5 I/O CIRCUIT SCHEMATICS

Figure 5-5. I/O Circuit Schematics

SD6830

NOTE : If STOP mode is specified, the TYPE C output becomes "L" state and the TYPE B output becomes floating
state, the TYPE D output maintains previous state.

VDD

VSS

DATA

30 150

T Y P E A

VDD

VSS

DATA

T Y P E B

CARRIER

CLOCK

T Y P E D

VDD

VSS

DATA

T Y P E C

VDD

VSS

DATA

STOP

Note : If STOP mode is specified, the TYPE C output becomes "L" state and the TYPE B output becomes floating

state, the TYPE D output maintains previous state

KSI-W002-000

6. Basic Function Block

6.1 Program Counter (PC)

Program counter is used to indicate the address of the next instruction to be executed.
The 10-bit program counter consists of two registers, PC

(4-bit) and PC

(6-bit).

This is a polynomial counter.

6.2 Program Memory (ROM)

Program memory is used to store user-specified program. This consists of a 1024 x 8-bit.
It is organized in 16 pages and each page is 64 bytes long. For page-in addressing, all
instructions excluding JMPL and CALL can be executed by page. In order to execute jump
or call in page, JMP or CAL is suitable. For page-to-page addressing, JMPL or CALL must be
used.

Figure 6-1. Program Memory Map

SD6830

PAGE 15

PAGE 0

RESET

ADDRESS

000h

PROGRAM COUNTER

PCH (4-BIT)

PCL (6-BIT)

PROGRAM MEMORY

KSI-W002-000

6.3 Data Memory (RAM)

Data memory is used to store various type of processing data. This consists of a 32-nibble,
which is organized into two files of 16 nibbles each. RAM addressing is indirectly
implemented by a two registers; H, L. It's upper 1-bit register (H) selects one of two files
and its lower 4-bit register (L) selects one of 16 nibbles in the selected file.

Figure 6-2. Data Memory Map

6.4 Stack Register (SK)

Stack register is used to store return address and provide a particularly mechanism for
transferring control between programs. Two level hardware push/pop stacks are
manipulated by CAL, CALL, and RET instructions. CAL/CALL instructions push the current
program counter value, incremented by "1", into stack level 1. Stack level 1 is
automatically pushed to level 2.
If more than two subsequent CAL/CALL are executed, only the most recent two return
addresses are stored. RET instruction load the contents of stack level 1 into the program
counter while stack level 2 gets copied into level 1. If more than two subsequent RET are
executed, the stack will be filled with the address previously stored in level 2.

SD6830

REG H (1-bit)

REG L ( 4-bit )

PORT

FILE 1

Lower

3-bit

DATA MEMORY

FILE 0

KSI-W002-000

6.5 Arithmetic and Logic Unit (ALU)

This unit is used to perform arithmetic and logical operations such as addition,
comparison, and bit manipulation.

6.6 Carry Flag (CY)

The carry flag contains the carry generated by the arithmetic and logical unit immediately
after an operation. The set carry (SETB CY) and clear carry (CLRB CY) instructions allow
direct access for setting and clearing this flag.

6.7 Skip Flag (SF)

The skip flag is a 1-bit register, which enables programs to conditionally skip an instruction.
All instructions are executed when this flag is

, the program executes

NOP instruction and resets SF to "0". Then program execution proceeds.
The following instructions affect the skip flag

Instructions

Set conditions of SF

Arithmetic

ADD n
INC L

If carry occurs
(L) = 0

Compare

IF0 @HL.b
IF0 CY
IFEQU @HL
IFEQU n

M[HL].b = 0
(CY) = 0
(A) = M[HL].b
(A) = n

Data Transfer

STA @HL+
XCH @HL+

(L) = 0
(L) = 0

The instructions, which doesn t affect the skip flag but have a skip condition, are as follows.

Instructions

Skip conditions

Data
Transfer

LDA n
LDL n

If it is continuous, skip next same
instruction.
If it is continuous, skip next same
instruction.

Bit
Manipulate

SETB H
CLRB H

If SETB H or CLRB H are continuous,
skip next
SETB H or CLRB H instruction.

SD6830

KSI-W002-000

6.8 Registers

Register A
Register A, called the accumulator, plays a central role, is used to store an input or

output operand (result) in the execution of most instructions. It consists of 4-bit.

Register B
Register B is used to store a temporary data in CPU. It consists of 4-bit.

Register H
Register H is used to indicate an address of the data memory in conjunction with register L.
It consists of 1-bit, which is related with the bit 0 of accumulator

Register L
Register L is used to indicate an address of the data memory in conjunction with register H,
Also lower 3-bit can be used to indicate the bit position of the port F. It consists of 4-bit

Register Z
Register Z is used to select a carrier frequency. The carrier frequency must be selected
before Port C data write operation. It consists of 3-bit.

Register Z

Bit 2

Bit 1

Bit 0

Carrier frequency

SYS

/12, 1/2 duty

SYS

/12, 1/3 duty

SYS

/12, 1/4 duty

SYS

/8, 1/2 duty

SYS

/8, 1/4 duty

SYS

/11, 4/11 duty

No carrier

SD6830

KSI-W002-000

6.9 I /O Ports

Port C/REM
Port C/REM is a 1-bit output port, which is related with the bit 3 of accumulator, with CMOS
N-channel open drain, which have large current sink capability, for I.R.LED drive.
This output can be configured as carrier frequency by programming the register Z and port
C data. This pin is put into the high-impedance state in stop mode.

Port D
Port D is a 4-bit input port with pull-up resistor. Forcing any input pins to "L" state, system
reset occurs and it starts to operate from the reset address.

Port E
Port E is a 4-bit input port with pull-up resistor. Forcing any input pins to
reset occurs and it starts to operate from the reset address.

Port F
Port F is an 8-bit output port with N-channel open drain. Each output which specified

by the

lower 3-bit of register L can be set and reset individually. All F pins are put into the low
state in stop mode.

Port G
Port G is a 1-bit output port with N-channel open drain. When stop mode is specified, this
pin still remains in the previous state. Set this pin to appropriate state before entering
stop mode for visible LED or key scan application.

Port K
Port K is a 1-bit output port with N-channel open drain. When stop mode is specified, this
pin still remains in the previous state. Set this pin to appropriate state before entering stop
mode for visible LED or key scan application.

SD6830

KSI-W002-000

6.10 Carrier frequency generator

One of seven carrier frequencies can be selected and transmitted through the C/REM pin by
programming the register Z and port C.

Figure 6-3 PORT C/REM and Carrier Output

Fsys

(Fsys/12, 1/2 duty)

(Fsys/12, 1/3 duty)

(Fsys/12, 1/4 duty)

(Fsys/8, 1/2 duty)

(Fsys/8, 1/4 duty)

V S S

MUX

/ 3

Fosc/8 (1/2 duty )
Fosc/8 (1/4 duty )

Fosc/11 (4/11 duty )

Vdd ( No carrier )

SD6830

KSI-W002-000

6.11 Watchdog timer (WDT)

The watchdog timer provides the means to return to a reset condition when a system
malfunction occurs and the program enters an infinite loop caused by noise or any
abnormal state.
Also this timer have a function of oscillation stabilization timer. This is a 13-bit counter,
counts the clock which is divided twelve (F

SYS

/12). In the stop mode the oscillation circuit

stops but when a key input is detected (Port D, Port E) oscillation starts. When 12288 clock
cycles have been counted, the program will be executed from reset address (000H). If the
port C data register's value does not change from "L" to "H" before the timer counts 98304
clock cycles, a device reset condition is generated.
The oscillator stabilization time : 12/F

SYS

* 2

= 1/F

SYS

* 12288 = 27mS (@455KHz)

The time-out period : 12/F

SYS

* 2

= 1/F

SYS

* 98304 = 216mS (@455KHz)

Figure 6-4. Function of Watchdog Timer

SD6830

Watchdog Timer (13-bit)

CLK

RESET

OPSTART

Operating Start

Fsys/12

Power-on Reset Active

Stop Mode Active

PORT C Data : Low to High Transition

OVERFLOW

To Reset Logic

OSCOUT

27mS(Min.)

Normal

mode

Stop

mode

Normal

mode

STOP
Instruction

Watchdog Timer
Overflow

PORT C Data
Low to High

WDT

counting value

98304

12288

Time

PORT C Data
Low to High

KSI-W002-000

6.12 Power-on reset

The SD6830 incorporates an on-chip power-on reset circuitry which provides internal chip
reset for most power-up situations. The power-on reset circuit and the watchdog timer are
closely related. On power-up the power-on reset circuit is active and watchdog timer is
reset. After the reset time, which is in proportion to the rate of rise of VDD, watchdog timer
begins counting. After the oscillator stabilization time, which is typically 27mS in
F

SYS

=455KHz, program execution proceeds from reset address (000H).

Figure 6-5. Built-in Power-on Reset

6.13 Stop mode

The SD6830 support the stop mode to reduce power consumption. This mode is entered
when the STOP instruction is executed during key inputs are not active. Activating any key
inputs (Port D, Port E) the device is awakened from stop mode and restarts to operate from
reset address. When the device is released from stop mode, following module
set to appropriate value in reset routine: PORT G and PORT K.
In stop mode, the oscillator is stopped and the each port state is as follows.

Port C/REM become inactive state. (

for including I.R.LED driver,

after the reset release)

Port G and Port K retain previous state.

SD6830

VDD

VSS

Internal /POR

DMC6830

7pF

2Mohm

RESET TIME

1.8V

0.3VDD

VDD

VDD PIN

Internal

/POR

SD6830

KSI-W002-000

Figure 6-6. Rest structure and Release Timing for STOP Mode to Normal Mode

6.14 OSC Divide Option

The OSC divide option provides a maximum 1MHz system clock (F

SYS

). F

OSC

which is

generated in oscillation circuit is divided eight or non-divide to produce F

SYS

This dividing ratio will be selected by mask option.

OSC

: Oscillator clock, F

SYS

: System clock (F

OSC

or F

OSC

/8)

Figure 6-7 OSC Divide Option

7. Electrical Specifications

7.1 Absolute maximum ratings

Symbols

Parameters

Conditions

Ratings

Units

Supply Voltage

-0.3 ~ 6.0

Input Voltage

-0.3 ~ V

+ 0.3

Output Voltage

Ta=25

-0.3 ~ V

+ 0.3

OPR

Operating temperature

-20 ~ 85

STG

Storage Temperature

-40 ~ 125

SD6830

Internal

/STOP

Key input

( PORT D or

PORT E )

OSCOUT

STOP instruction

27mS(Min.)

Normal

mode

Stop

mode

Stop

mode

VDD

PORT D

PORT E

4
4

STOP

RESET

STOP

instruction

internal /POR

WDT overflow

DMC6830

OSC

DIVIDE-8

M A S K O P T I O N

OSC OUT

OSC

SYS

OSC IN

SD6830

KSI-W002-000

7.2 Recommended operating conditions

= 3V ± 10%, Ta=-20 ~ 70, unless otherwise noted)

Symbols

Parameters

Min.

Typ.

Max.

Units

Supply Voltage

1.8

3.6

IH1

"H" input Voltage, all input pins

except OSCIN

0.7V

-V

IH2

"H" input Voltage, OSCIN

-0.3

IL1

"L" input Voltage, all input pins

except OSCIN

0.3 V

IL2

"L" input Voltage, OSCIN

0.3

Non-divide

option

250

1000

KHz

OSC

Oscillating

frequency

Divide-8 option

MHz

7.3 Electrical characteristics

= 3V ± 10%, Ta= 25 , unless otherwise noted)

Symbols

Parameters

Test Conditions

Min. Typ. Max. Units

250KHzF

OSC

3.9MHz

1.8

3.0

3.6

Supply Voltage

3.9MHzF

OSC

6.0MHz

2.2

3.0

3.6

"H" output current

= 2.0V, Port C

-6

-9

-14

OL0

"L" output current

= 0.4V, Port C

1.5

4.5

OL1

= 0.4V, Port C

180

210

240

OL2

= 0.4V, Port F

0.5

1.0

2.0

OL3

"L" output current

= 0.4V, Port G/K

1.5

3.0

4.5

LIH1

= V

, Port D/E

LIH2

"H" input leakage current

= V

, OSCIN

LIL

"L" input leakage current

= V

, OSCIN

-0.6

-3

-10

LOH

"H"output leakage current

= V

, Port C/F/G/K

PULL-UP

Pull-up resistance of input Port

= 0V, V

=3V

150

Supply current at normal mode

0.5

1.0

DDS

Supply current at stop mode

1.0

SYS

Clock frequency

250

1000

KHz

Non-divide option

250

1000

KHz

OSC

Oscillator frequency

Divide-8 option

MHz

SD6830

KSI-W002-000

8. Packing Outlines and Dimensions

SD6830

0 . 2 9 8 0 ( 7 . 5 6 9 )
0 . 2 9 2 0 ( 7 . 4 1 7 )

0 . 4 1 6 0 ( 1 0 . 5 6 6 )
0 . 3 9 8 0 ( 1 0 . 1 0 9 )

0.0200(0.508)

0.0138(0.351)

0 . 1 0 4 0 ( 2 . 6 4 2 )
0 . 0 9 4 0 ( 2 . 3 8 8 )

BASE PLANE

SEATING PLANE

0.6100(15.494)

0.6040(15.342)

0 . 0 1 1 8 ( 0 . 3 0 0 )
0 . 0 0 4 0 ( 0 . 1 0 2 )

0.0500 BSC

(1.270)

0 . 0 1 2 5 ( 0 . 3 1 8 )
0 . 0 0 9 1 ( 0 . 2 3 1 )

0.0350(0.889)

0.0160(0.406)

0.0100(0.254)

45°

°
~8°

2 4 S O P - 3 0 0

U N I T : I N C H ( M M )

0.0200(0.508)

0.0138(0.351)

0.5080(12.903)

0.5020(12.751)

0 . 1 0 4 0 ( 2 . 6 4 2 )
0 . 0 9 4 0 ( 2 . 3 8 8 )

BASE PLANE

SEATING PLANE

0.0500 BSC

(1.270)

0 . 0 1 1 8 ( 0 . 3 0 0 )
0 . 0 0 4 0 ( 0 . 1 0 2 )

0 . 2 9 8 0 ( 7 . 5 6 9 )
0 . 2 9 2 0 ( 7 . 4 1 7 )

0 . 4 1 6 0 ( 1 0 . 5 6 6 )
0 . 3 9 8 0 ( 1 0 . 1 0 9 )

2 0 S O P - 3 0 0

U N I T : I N C H ( M M )

0 . 0 1 2 5 ( 0 . 3 1 8 )
0 . 0 0 9 1 ( 0 . 2 3 1 )

0.0350(0.889)

0.0160(0.406)

0.0100(0.254)

45°

0°

~8°

KSI-W002-000

SD6830

0.300 BSC

(7.620)

0.270(6.858)

0.250(6.350)

3 ~ 11

0.014(0.356)

0.008(0.200)

1.043(26.492)

1.023(25.984)

0 . 1 8 0 ( 4 . 5 7 2 )
0 . 1 5 5 ( 3 . 9 3 7 )

0 . 1 4 5 ( 3 . 6 8 3 )
0 . 1 3 5 ( 3 . 4 2 9 )

0 . 0 3 5 ( 0 . 8 8 9 )
0 . 0 2 0 ( 0 . 5 0 8 )

0 . 1 4 0 ( 3 . 5 5 6 )
0 . 1 2 0 ( 3 . 0 4 8 )

0.079(2.007)

0.059(1.499)

0.065(1.650)

0.050(1.270)

0.021(0.533)

0.015(0.381)

0.100 BSC

(2.540)

0.300 BSC

(7.620)

0.270(6.858)

0.250(6.350)

3 ~ 11

0.014(0.356)

0.008(0.200)

2-EJECTION MARK (OPTION 1)

0.021(0.533)

0.015(0.381)

0 . 1 8 0 ( 4 . 5 7 2 )
0 . 1 5 5 ( 3 . 9 3 7 )

0 . 1 4 5 ( 3 . 6 8 3 )
0 . 1 3 5 ( 3 . 4 2 9 )

0.090(2.286)

0.070(1.778)

0.065(1.650)

0.050(1.270)

0 . 0 3 5 ( 0 . 8 8 9 )
0 . 0 2 0 ( 0 . 5 0 8 )

0 . 1 4 0 ( 3 . 5 5 6 )
0 . 1 2 0 ( 3 . 0 4 8 )

0.100 BSC

(2.540)

2 4 D I P - 3 0 0

U N I T : I N C H ( M M )

2 0 D I P - 3 0 0

U N I T : I N C H ( M M )

1.265(32.131)

1.245(31.623)

KSI-W002-000

9. Instructions

9.1 Symbol Description

SYMBOL

DESCRIPTIONS

A , B , L

4 Bit Register

1-Bit Register

3-Bit Register

PCH

The Higher 4-Bit of the Program Counter

PCL

The Lower 6-Bit of the Program Counter

10-Bit Program Counter ( Consisting of the PCH and PCL )

10-Bit Stack Register

1-Bit Carry Flag

1-Bit Skip Flag

C, G, K

1-Bit Port

D, E

4-Bit Port

8-Bit Port

Direction of Data Flow

M[(HL)] or @HL

The Contents of Data Memory Addressed by Reg HL

M[(HL)].b or @HL.b The Specified Bit's Content of Data Memory Addressed by Reg HL

@HL+

As a result of execution, increment L by one

addr

Address

immediate data

SD6830

KSI-W002-000

9.2 Opcode Map

0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b~

1011b

1100b~

1111b

MSB

LSB

8h~Bh Ch~Fh

0000b

NOP

ADDC

@HL

XCH

@HL+

0001b

STOP

LDA

XCH

@HL

0010b

LDA

INC

0011b

STA

RRC

LDA

@HL

CALL

addr

0100b

LDA

CLRB

0101b

LDA

SETB

0110b

LDA

0111b

IF0

@HL.b

NOT

LDZ

JMPL

addr

1000b

CLRB

STA

@HL+

1001b

SETB

STA

@HL

1010b

CLRB

1011b

SETB

CLRB

@HL.b

1100b

STA

IF0

CLRB

1101b

RET

SETB

1110b

IFEQU

STA

CLRB

1111b

IFEQU

@HL

STA

SETB

LDL

SETB

@HL.b

ADD

LDA

JMP

addr

CAL

addr

SD6830

KSI-W002-000

9.3 Instruction Descriptions

ADD n

Binary code : 0110xxxx
Syntax : [<label>] ADD n
Operation : (A) (A) + n, n=0~15 ( n must be decimal number )
Flags : CY: Unaffected. SF: Set to one if carry occurs, cleared otherwise.
Words/Cycles : 1/1
Description : Adds an immediate data to the accumulator and stores the result in
the accumulate.
Example : ADD 8 ; Add 8 to A.
JMP 035 ; Jump to 035 if 0A7
JMP 05F ; Jump to 05F if 8A15
ADDC @HL
Binary code 00010000
Syntax : [<label>] ADDC @HL
Operation : (A) (A) + M[(HL)] + (CY), (CY) Carry
Flags : CY: Set on carry-out of (A) + M[(HL)] + (CY)
SF: Unaffected
Words/Cycles : 1/1

Description : Adds the contents of the accumulator, the contents of data memory
addressed by registers H and L, and the carry bit. It stores the result in
the accumulator and the carry flag.

Example : CLRB CY ; Clear CY to zero
LDA 5 ; Load 5 to A
CLRB H ; Clear H to zero
LDL 6 ; Load 6 to L
ADDC @HL ; Add the content of A, M[(06)], and the content of CY
CAL addr
Binary code : 11xxxxxx
Syntax : [<label>] CAL addr
Operation : (SK1) (SK0), (SK0) (PC) + 1, (PCL) addr, addr = 000 ~ 03F

( addr must be hexadecimal number )

Flags : CY: Unaffected SF: Unaffected
Words/Cycles : 1/1
Description : Calls a subroutine located at the indicated address and pushes the current
contents of the program counter to the top of stack. The indicated address
must be within the current page.
Example : CAL 100 : Call subroutine located at the 100. The 100 must be logical
address and within the current page.

SD6830

KSI-W002-000

CALL addr

Binary code : 010100xx xxxxxxxx
Syntax : [<label>] CALL addr
Operation : (SK1) (SK0), (SK0) (PC) + 1, (PC) addr, addr = 000 ~ 3FF
( addr must be hexadecimal number )
Flags : CY: Unaffected
SF: Unaffected
Words/Cycles : 2/2
Description : Calls a subroutine located at the indicated address and pushes the
current contents of the program counter to the top of stack. The
indicated address can be anywhere in the full 1Kbyte memory space.
Example : CALL 2FF ; Call subroutine located at the 2FF.
The 2FF must be logical address.
CLRB @HL.b

Binary code : 010110xx
Syntax : [<label>] CLRB @HL.b
Operation : M[(HL)].b 0
Flags : CY: Unaffected
SF: Unaffected
Words/Cycles : 1/1
Description : Clears the specified bit of data memory addressed by registers H and L
to zero.
Example : CLRB H ; Clear H to 0
LDL 10 ; Load 10 to L. The 10 must be decimal number.
CLRB @HL.0 ; Clear the bit 0 of M[(0A)] to 0.
CLRB CY

Binary code : 00001000
Syntax : [<label>] CLRB CY
Operation : (CY) 0
Flags : CY: Set to zero
SF: Unaffected
Words/Cycles: 1/1
Description : Clears the carry flag to zero.
Example : CLRB CY ; Clear CY to zero

SD6830

KSI-W002-000

CLRB F
Binary code : 00001010
Syntax : [<label>] CLRB F
Operation : F.(L) 0
Flags : CY: Unaffected SF: Unaffected

Words/Cycles :

1/1

Description : Clears the specified bit of port F addressed by the lower 3-bit of register
L to zero.
Example : LDL 13 ; Load 13 to L
CLRB F : Clears the bit 5 of F to zero

CLRB G
Binary code : 00101100
Syntax : [<label>] CLRB G
Operation : G.(L) 0
Flags : CY: Unaffected
SF: Unaffected

Words/Cycles :

1/1

Description : Clears the port G to zero.
Example : CLRB G ; Clear G to zero

CLRB H
Binary code : 00100100
Syntax : [<label>] CLRB H
Operation : (H) 0
Flags : CY: Unaffected
SF: Unaffected

Words/Cycles :

1/1

Description : Clears the contents of register H to zero. Skip this instruction if it or
SETB H was used just before.
Example : IFEQU 1
CLRB H ;

Clear H to zero and skip continuous SETB H/CLRB H, if (A)1

SETB H ;

Sets H to one and skip continuous SETB H/CLRB H, if (A)=1

SD6830

KSI-W002-000

CLRB K
Binary code : 00101110
Syntax : [<label>] CLRB K
Operation : (K) 0
Flags : CY: Unaffected
SF: Unaffected

Words/Cycles :

1/1

Description : Clears the port K to zero.
Example : CLRB K ; Clear K to zero.

IF0 @HL.b
Binary code : 000001xx
Syntax : [<label>] IF0 @HL.b
Operation : M[(HL)b] = 0
Flags : CY: Unaffected
SF: Set to one if equal, cleared otherwise

Words/Cycles :

1/1

Description : Compares the specified bit of data memory addressed by registers H
and L with zero.
Example : SETB H ; Set H to one
LDL 4 ; Load 4 to L
IF0 @HL.3 ; Compare the bit 3 of M[(14)] with zero
JMP 020 ; Jump to 020 if not equal
JMP 030 ; Jump to 030 if equal

IF0 CY
Binary code : 00011100
Syntax : [<label>] IF0 CY
Operation : (CY) = 0
Flags : CY : Unaffected
SF : Set to one if equal, cleared otherwise
Words/Cycles

1/1

Description : Compares the carry flag with zero.
Example : IF0

CY ;

Compare the content of CY to zero

JMP

030 ;

Jump to 030 if not equal

JMP

040 ;

Jump to 040 if equal

SD6830

KSI-W002-000

IFEQU @HL
Binary code : 00001111
Syntax : [<label>] IFEQU @HL
Operation : (A) = M[(HL)]
Flags : CY : Unaffected
SF : Set to one if equal, cleared otherwise

Words/Cycles :

1/1

Description : Compares the contents of accumulator with the contents of data
memory addressed by registers H and L.
Example : LDA 14 ; Load 14 to A, and 14 must be decimal number
SETB H ; Sets H to one
LDL 4 ; Loads 4 to L
IFEQU @HL ; Compares 14 with M[(14)]
JMP 050 ; Jump to 050 if not equal
JMP 060 ; Jump to 060 if equal
IFEQU n
Binary code : 00001110 0111xxxx
Syntax : [<label>] IFEQU n
Operation : (A) = n, n = 0 ~15 ( n must be decimal number )
Flags : CY: Unaffected
SF: Set to one if equal, cleared otherwise

Words/Cycles : 2/2

Description : Compares the contents of accumulator with an immediate data.
Example : IFEQU 15 ; Compare the contents of accumulator with 15
JMP 070 ; Jump to 070 if not equal
JMP 080 ; Jump to 080 if equal
INC L
Binary code : 00100010
Syntax : [<label>] INC L
Operation : (L) (L) + 1
Flags : CY : Unaffect SF:As a result of execution, set to one if the contents
of register L are zero, cleared otherwise.

Words/Cycles : 1/1

Description : The contents of register L are incremented by one.
Example : LDL 14 ; Load 14 to L
INC L ; The contents of L are incremented by one
INC L ; The contents of L are incremented by one
JMP 090 ; It is skipped because the contents of L is

JMP 0A0 ; Jump to 0A0

SD6830

KSI-W002-000

JMP addr
Binary code : 10xxxxxx
Syntax : [<label>] JMP addr
Operation : (PCL) addr, addr = 00 ~ 3F ( addr must be hexadecimal number )
Flags : CY : Unaffected
SF : Unaffected

Words/Cycles : 1/1

Description : Jumps unconditionally to the indicated address. The indicated address
must be within the current page.
Example : JMP 2EF ; Jump unconditionally to the 2EF. The 2EF address must be
within the current page.

JMPL addr
Binary code : 010101xx xxxxxxxx
Syntax : [<label>] JMPL addr
Operation : (PC) addr, addr = 000 ~ 3FF (addr must be hexadecimal number. )
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

2/2

Description : Jumps unconditionally to the indicated address. The indicated address
can be anywhere in the full 1K-byte memory space.
Example : JMPL 100 ; Jump unconditionally to 100

LDA @HL
Binary code : 00100011
Syntax : [<label>] LDA @HL
Operation : (A) M[(HL)]
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads the contents of memory addressed by registers H and L into the
accumulator.
Example : SETB H ; Set H to 1
LDL 0 ; Load 0 to L
LDA @HL ; Load M[(10)] into A

SD6830

KSI-W002-000

LDA n
Binary code : 0111xxxx
Syntax : [<label>] LDA n
Operation : (A) n, n=0~15 ( n must be decimal number. )
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads an immediate data into the accumulator. Skip this instruction if it
was used just before.
Example : STA B
LDA 15 ; Load 15 into A.
LDA 4 ; It is skipped because this instruction was used just before
LDA 7 ; It is skipped because this instruction was used just before
JMP 0B0 ; Jump to 0B0

LDA B
Binary code : 00010101
Syntax : [<label>] LDA B
Operation : (A) (B)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads the contents of register B into the accumulator.
Example : LDA B ; Load the contents of B into A

LDA D
Binary code : 00010100
Syntax : [<label>] LDA D
Operation : (A) (D)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads the contents of port D into the accumulator.
Example : LDA D ; Load the contents of D into A

SD6830

KSI-W002-000

LDA E

Binary code : 00010010
Syntax : [<label>] LDA E
Operation : (A) (E)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1.

Description : Loads the contents of port E into the accumulator
Example : LDA E ; Load the contents of E into A

LDA H

Binary code : 00010001
Syntax : [<label>] LDA H
Operation : (A) (H)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads the contents of register H into the bit 0 of accumulator.
Example : LDA H ; Load the content of H into the bit 0 of A

LDA L

Binary code : 00010110
Syntax : [<label>] LDA L
Operation : (A) (L)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads the contents of register L into the accumulator.
Example : LDA L ; Load the contents of L into A

SD6830

KSI-W002-000

LDL n

Binary code : 0100xxxx
Syntax : [<label>] LDL n
Operation : (A) n, n = 0 ~ 15 ( n must be decimal number )
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Loads an immediate data to the register L. Skip this instruction if it was
used just before.
Example : LDA 3
LDL 8 ; Load 8 to L
LDL 4 ; It is skipped because this instruction was used just before
JMP 0C0 ; Jump to 0C0

LDZ n

Binary code : 00110xxx
Syntax : [<label>] LDZ n
Operation : (A) n, n = 0 ~ 7 ( n must be decimal number )
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Load an immediate data into the register Z.
Example : LDZ 0 ; Load 0 into Z. The 0 must be decimal number

NOP

Binary code : 00000000
Syntax : [<label>] NOP
Operation : (PC) (PC) + 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : No operation.
Example : NOP ; No operation

SD6830

KSI-W002-000

NOT

Binary code : 00010111
Syntax : [<label>] NOT
Operation : (A) /(A)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : The contents of accumulator are 1
Example : LDA 7
NOT ; 1's complement 7, then leaves 8 in A

RET

Binary code : 00011101
Syntax : [<label>] RET
Operation : (PC) (SK0), (SK0) (SK1)
Flags : CY: Unaffected
SF: Unaffected
Words/Cycles

1/1

Description : Returns from the subroutine to main routine.
Example : RET ; Returns from the subroutine to main routine

RRC

Binary code : 00010011
Syntax : [<label>] RRC
Operation : (A.b) (A.b+1) (A.3) (CY) (CY) (A.0)
Flags : CY : Set to bit 0 of the accumulator
SF : Unaffected
Words/Cycles

1/1

Description : Shifts the contents of accumulator 1-bit to the right through the carry.

The carry bit content shifts into the bit 3 of accumulator, and the bit 0 of
accumulator is shifted into the carry bit.

Example : SETB CY ; Set CY to one.
LDA 5 ; Load 5 to A
RRC ; CY becomes zero, and the contents of A is 11

SD6830

KSI-W002-000

SETB @HL.b

Binary code : 010111xx
Syntax : [<label>] SETB @HL.b
Operation : M[(HL)].b 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Sets the specified bit of memory addressed by registers H and L to one.
Example : CLRB H ; Clear H to zero
LDL 5 ; Load 5 to L
SETB @HL.2 ; Set the bit 2 of M[(05)] to one

SETB CY

Binary code : 00001001
Syntax : [<label>] SETB CY
Operation : (CY) 1
Flags : CY : Set to one
SF : Unaffected
Words/Cycles

1/1

Description : Sets the contents of carry flag to one.
Example : SETB CY ; Sets the content of CY to one

SETB F

Binary code : 00001011
Syntax : [<label>] SETB F
Operation : F.(L) 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Sets the specified bit of the port F addressed by register L to one.
Example : LDL 4 ; Loads 4 to L
SETB F ; Sets the bit 4 of F to one

SD6830

KSI-W002-000

SETB G

Binary code : 00101101
Syntax : [<label>] SETB G
Operation : (G) 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Sets the port G to one.
Example : SETB G ; Sets the port G to one

SETB H

Binary code : 00100101
Syntax : [<label>] SETB H
Operation : (H) 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Sets the contents of register H to one. Skip this instruction if it or SETB
H was used just before.
Example : IFEQU 1
SETB H ;

Sets H to one and skip continuous CLRB H/SETB H, if (A)1

CLRB H ;

Clear H to zero and skip continuous CLRB H/SETB H, if (A)=1

SETB K

Binary code : 00101111
Syntax : [<label>] SETB K
Operation : (K) 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Sets the port K to one.
Example : SETB K ; Sets the port K to one

SD6830

KSI-W002-000

STA @HL

Binary code : 00101001
Syntax : [<label>] STA @HL
Operation : M[(HL)] (A)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Stores the contents of accumulator in memory addressed by registers
H and L.
Example : LDL 0 ; Load 0 to L
SETB H ; Set H to one
STA @HL ; Stores the contents of A in M[(10)]

STA @HL+

Binary code : 00101000
Syntax : [<label>] STA @HL+
Operation : M[(HL)] (A), (L) (L) + 1
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Stores the contents of accumulator in memory addressed by registers
H and L. And then the contents of register L are incremented by one.
Example : LDL 15 ; Load 15 to L
SETB H ; Set H to one
STA @HL+ ; Stores the contents of A in M[(1F)]. L becomes
JMP 035 ; It is skipped because L is "0"
JMP 045 ; Jump to 045

STA B
Binary code : 00011110
Syntax : [<label>] STA B
Operation : (B) (A)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Stores the contents of accumulator in the register B.
Example : STA B ; Stores the contents of A in B

SD6830

KSI-W002-000

STA C

Binary code : 00001100
Syntax : [<label>] STA C
Operation : (C) (A)

Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Stores the bit 3 of accumulator in the port C.
Example : STA C ; Stores the bit 3 of A in C

STA H

Binary code : 00000011
Syntax : [<label>] STA H
Operation : (H) (A)0
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Stores the bit 0 of accumulator in the register H.
Example : STA H ; Store the bit 0 of A in H

STA L

Binary code : 00011111
Syntax : [<label>] STA L
Operation : (L) (A)
Flags : CY : Unaffected
SF : Unaffected
Words/Cycles

1/1

Description : Stores the contents of accumulator in the register L.
Example : STA L ; Stores the contents of A in L

SD6830

KSI-W002-000

STOP
Binary code : 00000001
Syntax : [<label>] STOP
Operation : Stop the oscillation of the oscillator, and reset PORT F to zero
Flags : CY : Unaffected SF : Unaffected
Words/Cycles

1/1

Description : Stops the oscillation of the oscillator.
Example : STOP
XCH @HL
Binary code : 00100001
Syntax : [<label>] XCH @HL
Operation : (A) M[(H,L)]
Flags : CY : Unaffected SF : Unaffected
Words/Cycles

1/1

Description : Exchanges the accumulator with the contents of the data memory
addressed by registers H and L without going through an
intermediate location.
Example : LDL 3 ; Load 3 to L
SETB H ; Set H to one
XCH @HL ; Exchanges the contents of A with M[(13)] without
going through an intermediate location
XCH @HL+
Binary code : 00100000
Syntax : [<label>] XCH @HL+
Operation : (A) M[(H,L)], (L) (L) + 1
Flags : CY : Unaffected
SF: As a result of execution, set to one if the contents of register L are
zero, cleared otherwise
Words/Cycles

1/1

Description : Exchanges the accumulator with the contents of the data memory
addressed by registers H and L without going through an intermediate
location. As a result of execution, the contents of register L are
incremented by one.
Example : SETB H ;
LDL 15 ; Load 15 into L

CH @HL+ ; Exchanges A with M[(1F)] without going through an
intermediate location. As a result of execution, the
contents of L are "0"

JMP 055 ; It is skipped because L is "0"
JMP 065 ; Jump to 065

SD6830

Part Number SD6830