Features

Programmable DMUX Ratio:

1:4: Data Rate Max = 1 Gsps
PD (8b/10b) < 4.3/4.7 W (ECL 50

output)

1:8: Data Rate Max = 2 Gsps
PD (8b/10b) < 6/6.9 W (ECL 50

output)

 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX

Parallel Output Mode

8-/10-bit

ECL Differential Input Data

DataReady or DataReady/2 Input Clock

Input Clock Sampling Delay Adjust

Single-ended Output Data:

Adjustable Common Mode and Swing
Logic Threshold Reference Output
(ECL, PECL, TTL)

Asynchronous Reset

Synchronous Reset

ADC + DMUX Multi-channel Applications:

 Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment

Differential Data Ready Output

Built-in Self Test (BIST)

Dual Power Supply V

= -5V, V

= +5V

Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)

TBGA 240 (Cavity Down) Package

Description

The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor,
designed to run with all kinds of ADCs and more specifically with Atmel's high-speed
ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B.

The TS81102G0 uses an innovative architecture, including a sampling delay adjust
and tunable output levels. It allows users to process the high-speed output data
stream down to processor speed and uses the very high-speed bipolar technology (25
GHz NPN cut-off frequency).

DMUX 8-/10-bit
2 GHz 1:4/8

TS81102G0

Rev. 2105CBDC11/03

TS81102G0

2105CBDC11/03

Block Diagram

Figure 1. Block Diagram

B 2

Counter

(8 stage

shift register)

DataReady
generation

Data Path

Clock Path

mux

Port Selection Clock

Data

Output

Clock

A[0..7/9]

C[0..7/9]

E[0..7/9]

G[0..7/9]

B[0..7/9]

D[0..7/9]

F[0..7/9]

H[0..7/9]

RefA

RefC

RefE

RefG

RefB

RefD

RefF

RefH

Even Ports

Odd Ports

mux

ClkIn

DEMUXDelAdjCtrl

ClkInT

ype

AsyncReset

RatioSel

delay

ADCDelAdjOut

ADCDelAdjCtrl

ADCDelAdjIn

SwiAdj

VplusDOut

VEE

GND

BIST

I[0..7/9]

NbBit

Latch Sel Even/Odd [1..8/10]

even

master

latch

even

slave

latch

odd

master

latch

odd

slave

latch

8/10

Counter

NAP

RatioSel

8/10

Status

ClkPar

VCC

DR/DR

FS/8

BIST

8/10

Phase

control

SyncReset

RstGen

Reset

DIODE

(to be confirmed)

TS81102G0

2105CBDC11/03

Internal Timing
Diagram

This diagram corresponds to an established operation of the DMUX with Synchronous Reset.

Figure 2. Internal Timing Diagram

Data In

DR In = Fs

DR/2 In = Fs/2 = ClkPar

Master Even Latch

Master Odd Latch

Slave Even Latch

Slave Odd Latch

Synchronous reset = Fs/8

Internal reset pulse

Port Select A

Port Select B

Port Select C

Port Select D

Port Select E

Port Select F

Port Select G

Port Select H

Latch Select A

Latch Select B

Latch Select C

Latch Select D

Latch Select E

Latch Select F

Latch Select G

Latch Select H

A to H Port Out

A to H LatchOut

DROut

500 ps min

N+2

N+3

N+4

N+5

N+6

N+7

N+8

N+9

N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24

N+8

N+16

N+24

N+1

N+9

N+17

N+25

N+2

N+10

N+18

N+26

N+3

N+11

N+19

N+27

N+4

N+12

N+20

N+5

N+13

N+21

N+6

N+14

N+22

N+7

N+15

N+23

N to N+7

N+8 to N+15

N+16 to N+23

N+25 N+26 N+27 N+28 N+29 N+30 N+31

N+24

N+26

N+28

N+30

N+14

N+16

N+18

N+20

N+22

N+6

N+8

N+10

N+12

N+2

N+4

N+3

N+5

N+7

N+9

N+11

N+13

N+15

N+17

N+19

N+21

N+23

N+25

N+27

N+29

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N+8

N+9

N+10

N+11

N+12

N+13

N+14

N+15

N+16

N+17

N+18

N+19

N+20

N+21

N+22

N+23

N+24

N+25

N+26

N+27

N+28

N+29

N+1

N+31

N+30

N+1

TS81102G0

2105CBDC11/03

Functional
Description

The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology fea-
turing a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be
processed at the DMUX output.

The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1
Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio.

The TS81102G0 is able to process 8 or 10-bit data flows.

The input clock can be an ECL differential signal or single-ended DC coupled signal. Moreover
it can be a DataReady or DataReady/2 clock.

The input digital data must be an ECL differential signal.

The output signals (Data Ready, digital data and reference voltage) are adjustable with
VplusD independent power supply. Typical output modes are ECL, PECL or TTL.

The Data Ready output is a differential signal. The digital output data and reference voltages
are single-ended signals.

The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the
user to re-synchronize the output port selection and to minimize loss of data that could occur
within the DMUX.

A delay adjust cell is available to ensure a good phase between the DMUX' input clock and
input data.

Another delay adjust cell is available to control the ADCss sampling instant alignment, in case
of the ADCs interleaving.

A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test
sequence is very useful for testing the DMUX at first use.

A fine tuning of the output swing is also available.

The TS81102G0 can be used with the following Atmel ADCs:

TS8388B(F/FS/GL), 8-bit 1 Gsps ADC

TS83102G0B, 10-bit 2 Gsps ADC

TS81102G0

2105CBDC11/03

Main Function
Description

Programmable
DMUX Ratio

The conversion ratio is programmable: 1:4 or 1:8.

Figure 3. Programmable DMUX Ratio

Parallel Output
Mode

Figure 4. Parallel Mode

Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL)

The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to
ensure a proper phase between the clock and input data of the DMUX.

1,2,3,4,5,6,7,8,...

PortA

PortB

PortC

PortD

PortE

PortF

PortG

PortH

...

not used

1:4

Input Words:

Output Words:

1,2,3,4,5,6,7,8,...

PortA

PortB

PortC

PortD

PortE

PortF

PortG

PortH

1:8

...

PortA

PortB

PortC

PortD

PortE

PortF

PortG

PortH

N+1

N+2

N+3

N+4

N+5

N+6

N+7

ClkIn

Part Number TS81102G0