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Part Number T87C5112

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Rev. B - November 10, 2000
1
Preliminary
T80C5112
8-bit Microcontroller with A/D converter
1. Description
The T80C5112 is a high performance ROM/OTP version
of the 80C51 8-bit microcontroller.
The T80C5112 retains all the features of the standard
80C51 with 8 Kbytes ROM/OTP program memory, 256
bytes of internal RAM, a 8-source , 4-level interrupt
system, an on-chip oscillator and two timer/counters.
The T80C5112 is dedicated for analog interfacing
applications. For this, it has an 10-bit, 8 channels A/D
converter and a five channels Programmable Counter
Array.
In addition, the T80C5112 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial
channel
that
facilitates
multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed
improvement mechanism. The X2 feature allows to keep
the same CPU power at a divided by two oscillator
frequency.
The fully static design of the T80C5112 allows to reduce
system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T80C5112 has 3 software-selectable modes of
reduced
activity
for
further
reduction
in
power
consumption. In the idle mode the CPU is frozen while
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
The T80C5112 is proposed in 48/52 pin count packages
with Port 0 and Port 2 (address / data busses).
2. Features
·
80C51 Compatible
·
Five I/O ports
·
Two 16-bit timer/counters
·
256 bytes RAM
·
8Kbytes ROM/OTP program memory with 64 bytes
encryption array and 3 security levels.
·
High-Speed Architecture
·
33MHz @ 5V (66 MHz equivalent)
·
20MHz @ 3V (40 MHz equivalent)
·
X2 Speed Improvement capability (6 clocks/
machine cycle)
·
10-bit, 8 channels A/D converter
·
Hardware Watchdog Timer with integrated low
power oscillator (20
µ
A) and Reset-Out
·
Programmable I/O mode: standard C51, input only,
push-pull, open drain.
·
Asynchronous port reset, Power On Reset
·
Full duplex Enhanced UART with baud rate generator
·
SPI, master/slave mode
·
Dual system clock
·
Crystal or ceramic oscillator with hardware set
up (32 KHz or 33/40 MHz)
·
Internal RC oscillator (12 MHz)
·
Programmable prescaler
·
Active oscillator during reset defined by hardware
set up
·
Timer 0 subclock mode for Real Time Clock.
·
Programmable counter array with High speed output,
Compare / Capture, Pulse Width Modulation and
Watchdog timer capabilities
·
Interrupt Structure with:
·
8 Interrupt sources,
·
4 interrupt priority levels
·
Power Control modes:
·
Idle mode
·
Power-down mode
·
Power-off Flag, Power fail detect, Power on Reset
·
Power supply: 2.7 to 5.5V
·
Temperature ranges: Commercial (0 to 70C) and
Industrial (-40 to 85 C), optionnal extented
·
Package:LQFP48 (body 7*7*1.4mm), PLCC52
2
Rev. B - November 10, 2000
Preliminary
T80C5112
3. Block Diagram
Timer 0
INT
RAM
256
T0
T1
RxD
TxD
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
C51
CORE
(2) (3)
(2) (3)
Port 1 Port 3
Parallel I/O Ports
P1
P4
IB-bus
Vpp
Watch
Dog
Vss
Vcc
(2)
(2)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
ROM /OTP
8 K *8
A/D
Converter
Vref
AIN0-7
x8
ECI
CEX0-4
Xtal
Osc
RC
Osc
(1)
(1)
(3)
(3): Alternate function of Port 4
Port 4
P3
(2)
(2)
(2)
PCA
MISO
(3)
MOSI
(3)
SPSCK
(3)
SPI
RC
Osc
BRG
Port 0
Port 2
SS
(3)
P0
P2
EA
Vref
generator
ALE
PSEN
RST
Rev. B - November 10, 2000
3
Preliminary
T80C5112
4. alias SFR Mapping
The Special Function Registers (SFRs) of the T80C5112 belongs to the following categories:
·
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR, AUXR1
·
I/O port registers: P0, P1, P2, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2
·
Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
·
Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON
·
Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL
·
Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1
·
WatchDog Timer: WDTRST, WDTPRG
·
SPI: SPCON, SPSTA, SPDAT
·
PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H,
CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON
·
ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF
Table 1. SFR Addresses and Reset Values
Notes: "C", value defined by the configuration byte, see Section "Configuration byte", page 11
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
CH
0000 0000
CCAP0H
XXXX XXXX
CCAP1H
XXXX XXXX
CCAP2H
XXXX XXXX
CCAP3H
XXXX XXXX
CCAP4H
XXXX XXXX
FFh
F0h
B
0000 0000
ADCLK
0000 0000
ADCON
0000 0000
ADDL
XXXXXX00
ADDH
0000 0000
ADCF
0000 0000
F7h
E8h
CL
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAP2L
XXXX XXXX
CCAP3L
XXXX XXXX
CCAP4L
XXXX XXXX
CONF
1111 111X
EFh
E0h
ACC
0000 0000
P1M2
0000 0000
P3M2
0000 0000
P4M2
0000 0000
E7h
D8h
CCON
00X0 0000
CMOD
X000 0000
CCAPM0
00XX X000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
DFh
D0h
PSW
0000 0000
P1M1
0000 0000
P3M1
0000 0000
P4M1
0000 0000
D7h
C8h
CFh
C0h
P4
1111 1111
SPCON
0001 0100
SPSTA
XXXXXXXX
SPDAT
XXXX XXXX
C7h
B8h
IPL0
0000 0000
SADEN
0000 0000
BFh
B0h
P3
1111 1111
IE1
0000 0000
IPL1
0000 0000
IPH1
0000 0000
IPH0
X000 0000
B7h
A8h
IE0
0000 0000
SADDR
0000 0000
CKCON1
XXXX XXX0
AFh
A0h
P2
1111 1111
AUXR1
XXXXXXX0
WDRST
0000 0000
WDTPRG
0000 0000
A7h
98h
SCON
0000 0000
SBUF
XXXX XXXX
BRL
0000 0000
BDRCON
0000 0000
9Fh
90h
P1
1111 1111
CKRL
1111 1111
97h
88h
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
XXXXXXX0
CKCON0
X000X000
8Fh
80h
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
CKSEL
XXXX XXXC
OSCCON
XXXX XXCC
PCON
00X1 0000
87h
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
4
Rev. B - November 10, 2000
Preliminary
T80C5112
5. Pin Configuration
*NIC: No Internal Connection
21 22
26
25
24
23
29
28
27
30 31
6 5 4 3 2
7
1
52 51 50 49
47 46 45 44 43
48
42 41 40 39 38
P4.7/AIN7
RST
P4.4/AIN4/MISO
P4.6/AIN6/SPSCK
P4.5/AIN5/MOSI
EA
P1.0/
WR
P1.1/
RD
P4.2/AIN2/
SS
P4.1/AIN1/T1
P4.3/AIN3/
INT1
P3.0/RxD
P0.0
P3.1/TxD
P0.1
P0.5
P0.2
P0.3
P0.6
P1.2/ECI
P0.7
P2.1
VPP
P3.6
XT
AL2/P3.5
XT
AL1/P3.4
ALE
PSEN
P3.3/T0
P3.2/
INT0
P1.5/CEX2
P1.6/CEX3
8
9
10
11
12
13
14
15
16
17
18
46
45
44
43
42
41
40
39
38
37
36
PLCC52
13 14
18
17
16
15
21
20
19
22 23
36
35
34
33
32
31
30
29
28
27
26
LQFP48
1
2
3
4
5
6
7
8
9
10
P1.3
/CEX0
25
P1.4/CEX1
24
37
P4.0/AIN0
32 33
35
34
48 47
19
20
11
12
P0.4
P1.7/CEX4
P4.7/AIN7
RST
P4.4/AIN4/MISO
P4.6/AIN6/SPSCK
P4.5/AIN5/MOSI
EA
P1.0/
WR
P1.1/
RD
P4.2/AIN2/
SS
P4.1/AIN1/T1
P4.3/AIN3/
INT1
P4.0/AIN0
VREF
VSS + AVSS
P2.7
P2.6
P2.5
P2.4
P2.3
V2.2
VCC + AVCC
P2.0
P3.7
P2.0
VSS
AVSS
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
AVCC + VCC
P3.7
VPP
NIC
P3.1/TxD
P3.0/RxD
P0.0
P0.5
P0.1
P0.2
P0.6
P1.2/ECI
P0.7
P1.3/CEX0
P0.4
VREF
P2.1
P0.3
7*7*1.4 mm
P3.5
XT
AL2
XT
AL1
ALE
PSEN
P3.3/T0
P3.2/
INT0
P1.5/CEX2
P1.6/CEX3
P1.4/CEX1
P1.7/CEX4
P3.4
P3.6
Rev. B - November 10, 2000
5
Preliminary
T80C5112
MNEMONIC
PIN
NUMBER
TYPE
NAME AND FUNCTION
LQFP
48
PLCC
52
V
SS
X
X
I
Ground: 0V reference.
V
CC
X
X
I
Power Supply: This is the power supply voltage for normal, idle and power-
down operation.
AV
SS
X
I
Analog Ground: 0V reference.
AV
CC
I
Analog Power Supply: This is the power supply voltage for normal and idle
operation of the A/D
VREF
X
X
I
VREF : A/D converter positive reference input.
VPP
X
X
I
Vpp : Programming Supply Voltage:
This pin also receives the 12V programming pulse which will start the EPROM
programming and the manufacturer test modes.
P1.0-P1.7
X
X
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs.
Alternate functions for Port 1 include:
I/O
WR (P1.0): External data memory write strobe
I/O
RD (P1.1): External data memory readstrobe
I/O
ECI (P1.2): External Clock for the PCA
I/O
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
I/O
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
I/O
CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
I/O
CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
I/O
CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
P3.0-P3.7
X
X
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs.
P3.4 and P3.5 are valid I/O pins only when the T80C5112 is using the internal
RC oscillator, OSCB.
P3.6 is an input only pin
Port 3 also serves the special features of the 80C51 family, as listed below.
I/O
RXD (P3.0): Serial input port
I/O
TXD (P3.1): Serial output port
I/O
INT0 (P3.2): External interrupt 0
I/O
T0 (P3.3): Timer 0 external input
I/O
XTAL1 (P3.4): Input to the inverting oscillator amplifier and input to the internal
clock generator circuits, selected by hardware set up
a
I/O
XTAL2 (P3.5): Output from the inverting oscillator amplifier, selected by
hardware set up
P4.0-P4.7
X
X
I/O
Port 4: Port 4 is an 8-bit bidirectional I/O port. Each bit can be set as pure
CMOS input or as push-pull output.
Port 4 is also the input port of the Analog to digital converter and used for
oscillator and reset.
I/O
AIN0 (P4.0): A/D converter input 0
I/O
AIN1 (P4.1): A/D converter input 1
T1: Timer 1 external input
I/O
AIN2 (P4.2): A/D converter input 2
SS: Slave select input of the SPI controller