T44C080

Rev. A2, 15-Jan-01

1 (56)

Low-Current Microcontroller for Wireless Communication

The T44C080 is a member of Atmel Wireless & Microcontrollers' family of 4-bit single-chip microcontrollers. It con-
tains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function,
voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external
clock input, integrated RC-, 32-kHz crystal- and 4-MHz crystal-oscillators.

Features / Benefits

D Very low power consumption in active, power-down

and sleep mode

D 2-Kbyte ROM, 256 x 4-bit RAM
D 12 bidirectional I/Os
D Up to 6 external / internal interrupt sources
D Multifunction timer/counter
D Programmable system-clock with prescaler and five

different clock sources

D Wide supply voltage range (1.8 to 6.5 V)

D Very low sleep current (< 1

D Synchronous serial interface (2-wire, I

C, 3-wire)

D Watchdog, POR and brown-out function

D Voltage monitoring incl. Lo_BAT detect

D Flash controller T48C893 available (SSO20)

Voltage monitor
External input

MARC4

UTCM

OSC1

NRST/

I/O bus

ROM

RAM

4-bit CPU core

256 x 4 bit

VDD

VSS

Data direction +
alternate function

Data direction +
interrupt control

Port 4

Port 5

Brown-out protect.
RESET

Clock management

Timer 1

watchdog timer

Timer 2

Serial interface

Port 2

Data direction

T2O

BP20/NTE

BP21

BP22

BP23

BP40
INT3
SC BP41

VMI
T2I

BP42
T2O BP43

INT3
SD

BP50
INT6

BP51
INT6

BP52
INT1

BP53
INT1

oscillators

Crystal

oscillators

2 K x 8 bit

VMI

with modulator

SSI

External

clock input

interval- and

8/12-bit timer

T2I

OSC2

Figure 1. Block diagram of the T44C080

T44C080

Rev. A2, 15-Jan-01

2 (56)

T44C080

BP40/INT3/SC

BP53/INT1

BP52/INT1

BP51/INT6

BP50/INT6

OSC1

NRST/ OSC2

n.c.

BP43/INT3/SD

BP42/T2O

BP41/VMI/T2I

BP23

BP22

BP21

BP20/NTE

n.c.

14200

Figure 2. Pinning SSO20 package

Table 1 Pin description

Name

Type

Function

Alternate Function

Pin-No.

SSO20

Reset

State

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Supply voltage

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Circuit ground

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

n.c.

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Not connected

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

n.c.

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Not connected

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

BP20

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 2.0

ÁÁÁÁÁÁÁÁÁÁÁ

NTEtest mode enable

ÁÁÁÁ

Input

ÁÁÁÁ

BP21

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 2.1

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

Input

ÁÁÁÁ

BP22

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 2.2

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

Input

ÁÁÁÁ

BP23

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 2.3

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

Input

ÁÁÁÁ

BP40

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 4.0

ÁÁÁÁÁÁÁÁÁÁÁ

SC-serial clock or INT3 external in-
terrupt input

ÁÁÁÁ

Input

ÁÁÁÁ

BP41

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 4.1

ÁÁÁÁÁÁÁÁÁÁÁ

VMI voltage monitor input or T2I
external clock input Timer 2

ÁÁÁÁ

Input

ÁÁÁÁ

BP42

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 4.2

ÁÁÁÁÁÁÁÁÁÁÁ

T2O Timer 2 output

ÁÁÁÁ

Input

ÁÁÁÁ

BP43

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 4.3

ÁÁÁÁÁÁÁÁÁÁÁ

SD serial data I/O or INT3external
interrupt input

ÁÁÁÁ

Input

ÁÁÁÁ

BP50

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 5.0

ÁÁÁÁÁÁÁÁÁÁÁ

INT6 external interrupt input

ÁÁÁÁ

Input

ÁÁÁÁ

BP51

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 5.1

ÁÁÁÁÁÁÁÁÁÁÁ

INT6 external interrupt input

ÁÁÁÁ

Input

ÁÁÁÁ

BP52

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 5.2

ÁÁÁÁÁÁÁÁÁÁÁ

INT1 external interrupt input

ÁÁÁÁ

Input

ÁÁÁÁ

BP53

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Bidirectional I/O line of Port 5.3

ÁÁÁÁÁÁÁÁÁÁÁ

INT1 external interrupt input

ÁÁÁÁ

Input

ÁÁÁÁ

n.c.

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Not connected

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

n.c.

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Not connected

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

OSC1

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Oscillator input

ÁÁÁÁÁÁÁÁÁÁÁ

4-MHz crystal input or 32-kHz crys-
tal input or external clock input or
external trimming resistor input

ÁÁÁÁ

Input

ÁÁÁÁ

NRST/

OSC2

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁ

Reset input/ output

Oscillator output

ÁÁÁÁÁÁÁÁÁÁÁ

4-MHz crystal output or 32-kHz
crystal output or NRST (mask op-
tion)

ÁÁÁÁ

T44C080

Rev. A2, 15-Jan-01

3 (56)

Table of Contents

Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MARC4 Architecture

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1

General Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

Components of MARC4 Core

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1

ROM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2

RAM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3

Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4

ALU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5

I/O Bus

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.6

Instruction Set

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7

Interrupt Structure

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Interrupts

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Interrupts

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

Master Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1

Power-on Reset and Brown-out Detection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2

Watchdog Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3

External Clock Supervisor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4

Voltage Monitor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1

Voltage Monitor Control / Status Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5

Clock Generation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1

Clock Module

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2

Oscillator Circuits and External Clock Input Stage

. . . . . . . . . . . . . . . . . . . . . . . .

RC-Oscillator 1 Fully Integrated

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Input Clock

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RC-Oscillator 2 with External Trimming Resistor

. . . . . . . . . . . . . . . . . . . . . . . . .

4-MHz Oscillator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32-kHz Oscillator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3

Clock Management

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Management Register (CM)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Configuration Register (SC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6

Power-down Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Modules

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1

Addressing Peripherals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

Bidirectional Ports

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1

Bidirectional Port 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 2 Data Register (P2DAT)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 2 Control Register (P2CR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2

Bidirectional Port 5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3

Bidirectional Port 4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3

Universal Timer/Counter / Communication Module (UTCM)

. . . . . . . . . . . . . . . . . . . . . . . .

3.3.1

Timer 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T44C080

Rev. A2, 15-Jan-01

4 (56)

Table of Contents (continued)

Timer 1 Control Register 1 (T1C1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 1 Control Register 2 (T1C2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Watchdog Control Register (WDC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2

Timer 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Output Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Output Signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Control Register (T2C)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Mode Register 1 (T2M1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Mode Register 2 (T2M2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Compare and Compare Mode Registers

. . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 Compare Mode Register (T2CM)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 COmpare Register 1 (T2CO1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer 2 COmpare Register 2 (T2CO2) Byte Write

. . . . . . . . . . . . . . . . . . . . . . . .

3.3.3

Synchronous Serial Interface (SSI)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSI Peripheral Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General SSI Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-bit Synchronous Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-bit Shift Mode (I2C compatible)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-bit Pseudo I2C Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C Bus Protocol

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSI Interrupt

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Modulation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Interface Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Interface Control Register 1 (SIC1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Interface Control Register 2 (SIC2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Interface Status and Control Register (SISC)

. . . . . . . . . . . . . . . . . . . . . . .

Serial Transmit Buffer (STB) Byte Write

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Receive Buffer (SRB) Byte Read

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.4

Combination Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Combination Mode Timer 2 and SSI

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

DC Operating Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

AC Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ordering Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T44C080

Rev. A2, 15-Jan-01

5 (56)

Introduction

The T44C080 is a member of Atmel Wireless &
Microcontrollers's family of 4-bit single-chip micro-
controllers. They contain ROM, RAM, parallel I/O ports,
one 8-bit programmable multifunction timer/counter,
voltage supervisor, interval timer with watchdog function
and a sophisticated on-chip clock generation with inte-
grated RC-, 32-kHz crystal- and 4-MHz
crystal-oscillators.

MARC4 Architecture

2.1

General Description

The MARC4 microcontroller consists of an advanced
stack-based, 4-bit CPU core and on-chip peripherals. The

CPU is based on the HARVARD architecture with
physically separate program memory (ROM) and data
memory (RAM). Three independent buses, the
instruction bus, the memory bus and the I/O bus, are used
for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes both, an expression and a
return stack. This architecture enables high-level
language programming without any loss of efficiency or
code density.

ĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎĎ

ĎĎ

Instruction
decoder

CCR

TOS

ALU

RAM

X
Y

Program

256 x 4-bit

MARC4 CORE

Clock

Reset

Sleep

Memory bus

I/O bus

Instruction
bus

Reset

System
clock

Interrupt

controller

Onchip peripheral modules

94 8973

memory

Figure 3. MARC4 core

Part Number T44C080

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