1
Features
·
6.6 SPEC int 95, 5.5 SPECfp95 at 266 MHz (Estimated)
·
Superscalar 603e Core
·
Integer Unit (IU), Floating-Point Unit (FPU) (User Enabled or Disabled), Load/Store Unit
(LSU), System Register Unit (SRU), and a Branch Processing Unit (BPU)
·
16-Kbyte Instruction Cache
·
16-Kbyte Data Cache
·
Lockable L1 Caches - Entire Cache or on a Per-way Basis up to 3 of 4 Ways
·
Dynamic Power Management
·
High-bandwidth Bus (32/64 bits Data Bus) to DRAM
·
Supports 1-Mbyte to 1-Gbyte DRAM Memory
·
32-bit PCI Interface Operating up to 66 MHz
·
PCI 2.1-compliant, 5.0V Tolerance
·
Fint Max = 200 MHz
·
FBus Max = 66 MHz
Description
The PC8240 combines a PowerPC
TM
603e core microprocessor with a PCI bridge. The
PC8240's PCI support will allow system designers to rapidly design systems using peripherals
already designed for PCI and the other standard interfaces. The PC8240 also integrates a high-
performance memory controller which supports various types of DRAM and ROM. The PC8240
is the first of a family of products that provides system level support for industry standard inter-
faces with a PowerPC microprocessor core.
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt
controller, I
2
O controller, and a two-wire interface controller. The 603e core is a full-featured,
high-performance processor with floating-point support, memory management, 16-Kbyte
instruction cache, 16-Kbyte data cache, and power management features. The integration
reduces the overall packaging requirements and the number of discrete devices required for an
embedded system.
The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the
peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade
off performance for power consumption. The 603e core is clocked from a separate PLL, which
is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral
logic block to operate at different frequencies, while maintaining a synchronous bus interface.
The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit
address bus along with control signals that enable the interface between the processor and
peripheral logic to be optimized for performance. PCI accesses to the PC8240's memory space
are passed to the processor bus for snooping purposes when snoop mode is enabled.
The PC8240's features serve a variety of embedded applications. In this way, the 603e core
and peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or
an agent controller.
Screening/Quality/Packaging
This product is manufactured in full compliance with:
·
Upscreening based upon Atmel standards
·
Industrial temperature range
(T
c
= -40°C, T
c
= +110
°
C)
(T
c
= -40°C, T
c
= +125
°
C): ZD3 suffix
·
Core power supply:
2.5 ± 5 % V (L-Spec for 200 MHz)
·
I/O power supply: 3.0V to 3.6V
·
352 Tape Ball Grid Array (TBGA)
TP suffix
TBGA352
Tape Ball Grid Array
Integrated
Processor
Family
PC8240
Rev. 2149AHIREL05/02
2
PC8240
2149AHIREL05/02
General Description
Block Diagram
The PC8240 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar PowerPC 603e core, as shown in Figure 1.
Figure 1. Block Diagram
Peripheral Logic
Instruction Unit
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
Message
Controller
(I2O)
I2C
Controller
DMA
Controller
EPIC
Interrupt
Controller
/Timers
PCI Bus
Interface Unit
Data Path
ECC Controller
Memory
Controller
Central
Control
Unit
Oscillator
Input
Five Request/
Grant Pairs
I2C
5 IRQs/
16 Serial
Interrupts
603e Processor Core Block
Peripheral Logic Block
Processor
PLL
Instruction
MMU
(64-bit) Two-instruction fetch
(64-bit) Two-instruction dispatch
Peripheral Logic
PLL
SDRAM
Clocks
PCI
Clock In
PCI Bus
Clocks
Data (64-bit)
Address
(32-bit)
Data Bus
(32- or 64-bit)
with 8-bit Parity
or ECC
Memory/ROM/PortX
Address and Control
64-bit
32-bit
PCI Interface
Branch
Processing
Unit
(BPU)
System
Register
Unit
(SRU)
Floating
Point
Unit
(FPU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Bus
Configuration
Registers
Data
MMU
16-Kbyte
Data
Cache
16-Kbyte
Instruction
Cache
Additional features:
· JTAG/COP interface
· Power management
PC8240
3
PC8240
2149AHIREL05/02
Pinout Listing
Table 1 provides the pinout listing for the PC8240, 352 TBGA package.
Table 1. PC8240 Pinout Listing
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output Driver
Type
Notes
PCI Interface Signals
C/BE[0
3]
A25 F23 K23 P25
I/O
OVdd
DRV_PCI
(6)(15)
DEVSEL
H26
I/O
OVdd
DRV_PCI
(8)(15)
FRAME
J24
I/O
OVdd
DRV_PCI
(8)(15)
IRDY
K25
I/O
OVdd
DRV_PCI
(8)(15)
LOCK
J26
Input
OVdd
(8)
AD[0
31]
C22 D22 B22 B23 D19 B24 A24 B26
A26 C26 D25 D26 E23 E25 E26 F24
L26 L25 M25 M26 N23 N25 N26 R26
R25 T26 T25 U23 U24 U26 U25 V25
I/O
OVdd
DRV_PCI
(6)(15)
PAR
G25
I/O
OVdd
DRV_PCI
(15)
GNT[0
3]
V26 W23 W24 W25
Output
OVdd
DRV_PCI
(6)(15)
GNT4/DA5
W26
Output
OVdd
DRV_PCI
(7)(15)
REQ[0
3]
AB26 AA25 AA26 Y25
Input
OVdd
(6)(12)
REQ4/DA4
Y26
Input
OVdd
(12)
PERR
G26
I/O
OVdd
DRV_PCI
(8)(15)(18)
SERR
F26
I/O
OVdd
DRV_PCI
(8)(15)(16)
STOP
H25
I/O
OVdd
DRV_PCI
(8)(15)
TRDY
K26
I/O
OVdd
DRV_PCI
(8)(15)
INTA
AC26
Output
OVdd
DRV_PCI
(15)(16)
IDSEL
P26
Input
OVdd
Memory Interface Signals
MDL[0
31]
AD17 AE17 AE15 AF15 AC14 AE13
AF13 AF12 AF11 AF10 AF9 AD8 AF8
AF7 AF6 AE5 B1 A1 A3 A4 A5 A6 A7
D7 A8 B8 A10 D10 A12 B11 B12 A14
I/O
GVdd
DRV_MEM_DATA
(5)(6)(13)
MDH[0
31]
AC17 AF16 AE16 AE14 AF14 AC13
AE12 AE11 AE10 AE9 AE8 AC7 AE7
AE6 AF5 AC5 E4 A2 B3 D4 B4 B5 D6
C6 B7 C9 A9 B10 A11 A13 B13 A15
I/O
GVdd
DRV_MEM_DATA
(6)(13)
CAS/DQM[0
7]
AB1 AB2 K3 K2 AC1 AC2 K1 J1
Output
GVdd
DRV_MEM_ADDR
(6)
RAS/CS[0
7]
Y4 AA3 AA4 AC4 M2 L2 M1 L1
Output
GVdd
DRV_MEM_ADDR
(6)
FOE
H1
I/O
GVdd
DRV_MEM_ADDR
(3)(4)
RCS0
N4
I/O
GVdd
DRV_MEM_ADDR
(3)(4)
RCS1
N2
Output
GVdd
DRV_MEM_ADDR
5
PC8240
2149AHIREL05/02
TBEN
B14
Input
OVdd
(10)
QACK/DA0
F2
Output
OVdd
DRV_STD
(3)(4)
CHKSTOP_IN
D14
Input
OVdd
(10)
MAA[0
2]
AF2 AF1 AE1
Output
DRV_MEM_DATA
(3)(4)(6)
MIV
A16
Output
OVdd
DRV_STD
PMAA[0
2]
AD18 AF18 AE19
Output
OVdd
DRV_STD
(3)(4)(6)(15)
Test/Configuration Signals
PLL_CFG[0
4]/
DA[10
6]
A22 B19 A21 B18 B17
Input
OVdd
(4)(6)
TEST[0
1]
AD22 B20
Input
OVdd
(1)(6)(9)
TEST2
Y2
Input
(11)
TEST3
AF20
Input
OVdd
(10)
TEST4
AC18
I/O
OVdd
DRV_STD
(10)
TCK
AF22
Input
OVdd
(9)(12)
TDI
AF23
Input
OVdd
(9)(12)
TDO
AC21
Output
OVdd
DRV_PCI
TMS
AE22
Input
OVdd
(9)(12)
TRST
AE23
Input
OVdd
(9)(12)
Power and Ground Signals
GND
AA2 AA23 AC12 AC15 AC24 AC3
AC6 AC9 AD11 AD14 AD16 AD19
AD23 AD4 AE18 AE2 AE21 AE25 B2
B25 B6 B9 C11 C13 C16 C23 C4 C8
D12 D15 D18 D21 D24 D3 F25 F4
H24 J25 J4 L24 L3 M23 M4 N24 P3
R23 R4 T24 T3 V2 V23 W3
Ground
52 terminals
LVdd
AC20 AC23 D20 D23 G23 P23 Y23
Reference
voltage
3.3V, 5.0V
LVdd
GVdd
AB3 AB4 AC10 AC11 AC8 AD10
AD13 AD15 AD3 AD5 AD7 C10 C12
C3 C5 C7 D13 D5 D9 E3 G3 H4 K4
L4 N3 P4 R3 U3 V4 Y3
Power for
Memory
Drivers
2.5V, 3.3V
GVdd
OVdd
AB24 AD20 AD24 C14 C20 C24 E24
G24 J23 K24 M24 P24 T23 Y24
PCI/Stnd
3.3V
OVdd
Vdd
AA24 AC16 AC19 AD12 AD6 AD9
C15 C18 C21 D11 D8 F3 H23 J3 L23
M3 R24 T4 V24 W4
Power for
Core 2.5V
Vdd
LAVdd
D17
Power for
DLL 2.5V
LAVdd
Table 1. PC8240 Pinout Listing (Continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output Driver
Type
Notes
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