1
Features
·
PC7410 RISC Microprocessor
·
Dedicated 2 MB SSRAM L2 Cache, Configured as 256Kx72
·
21 mm x 25 mm, 255 Ceramic Ball Grid Array
·
Maximum Core Frequency = 400 MHz
·
Maximum L2 Cache Frequency = 200 MHz
·
Maximum 60x Bus Frequency = 100 MHz
Description
The PC7410M16 multichip package is targeted for high performance, space sensitive,
low power systems and supports the following power management features: doze,
nap, sleep and dynamic power management.
The PC7410M16 is offered in industrial and military temperature ranges and is well
suited for embedded applications.
Screening
·
CBGA Upscreening Based on Atmel Standards
·
Full Military Temperature Range (T
j
= -55
°C, +125°C),
Industrial Temperature Range (T
j
= -40
°C, +110°C)
SSRAM
SSRAM
PC7410
RISC
Microprocessor
Multichip
Package
Preliminary
Specification
-site
PC7410M16
Rev. 2183AHIREL12/02
2
PC7410M16
2183AHIREL12/02
Block Diagram
Figure 1. PC7410M16 Microprocessor Block Diagram
Reservation
Station
Reservation
Station
Fetcher
Dispatch Unit
Reservation
Station
V
ector
Permute
Unit
VSCR
V
e
ctor ALU
VSIU
V
CIU
VFPU
Reservation
Station
VR File
6 Rename
Buf
fers
Reservation
Station
Interger
Unit 1
. .
+ x
Interger
Unit 2
. .
GPR File
6 Rename
Buf
f
ers
. .
FPR File
6 Rename
Buf
f
ers
. .
System
Register
Unit
V
e
ctor
T
o
uch
Queue
Reservation
Station
Floating-Point
Unit
Reservation
Station (2 Entry)
Load/Store Unit
(EA
Calculation)
Finished
Stores
Complete
Stores
L1
Operations
Load Fold
Queue
+
+
. .
+ x
FPSCR
Additional Features
T
i
me Base
Counter/Decrementer
Clock Muliplier
JT
AG/COP
Interface
Thermal/Power Management
Performance Monitor
Instruction Queue
(6 W
o
rd)
Completion Queue
(8 Entry)
Completion Unit
Branch Processing Unit
BTIC
(64 Entry)
BHT
(512 Entry)
LR
CTR
Instruction MMU
SRs
(Shadow)
128-Entry
DTLB
IBA
T
Array
Data MMU
SRs
(Original)
128-Entry
DTLB
DBA
T
Array
Ta
g
s
32-Kbyte
I Cache
Ta
g
s
32-Kbyte
I Cache
Ability to complete up
to two instructions per clock
L2 Data
T
ransaction
Queue
L2 Controller
L2 T
a
gs
L2CR
L2PMCR
L2 Miss
L2 Castout
Data
T
ransaction
Queue
Bus Interface Unit
Data Reload
Buf
f
er
Instruction
Reload Buf
f
er
Instruction
Reload T
a
ble
Data Reload
Ta
b
l
e
Memory Subsystem
SSRAM
S
SRAM
19-bit L2
Address Bus
64- 32-bit L2 Data Bus
64-bit Data Bus
32-bit Address
Bus
32-bit
32-bit
32-bit
64-bit
64-bit
128-bit
128-bit
EA
PA
128-bit
(4 Instructions)
3
PC7410M16
2183AHIREL12/02
Features
This section summarizes features of the PC7410M16's implementation of the PowerPC
architecture. Major features of the PC7410M16 are as follows:
·
Branch Processing Unit
Four instructions fetched per clock
One branch processed per cycle (plus resolving two speculations)
Up to one speculative stream in execution, one additional speculative stream
in fetch
512-entry branch history table (BHT) for dynamic prediction
64-entry, 4-way set associative branch target instruction cache (BTIC) for
eliminating branch delay slots
·
Dispatch Unit
Full hardware detection of dependencies (resolved in the execution units)
Dispatch two instructions to eight independent units (system, branch,
load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec
permute, AltiVec ALU)
Serialization control (predispatch, postdispatch, execution serialization)
·
Decode
Register file access
Forwarding control
Partial instruction decode
·
Completion
8-entry completion buffer
Instruction tracking and peak completion of two instructions per cycle
Completion of instructions in program order while supporting out-of-order
instruction execution, completion serialization and all instruction flow
changes
·
Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
Fixed-point unit 1 (FXU1) -- multiply, divide, shift, rotate, arithmetic, logical
Fixed-point unit 2 (FXU2) shift, rotate, arithmetic, logical
Single-cycle arithmetic, shifts, rotates, logical
Multiply and divide support (multi-cycle)
Early out multiply
·
Three-stage Floating-point Unit and a 32-entry FPR File
Support for IEEE-754 standard single- and double-precision floating-point
arithmetic
Three-cycle latency, one-cycle throughput (single or double precision)
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
·
System Unit
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
4
PC7410M16
2183AHIREL12/02
·
AltiVec Unit
Full 128-bit data paths
Two dispatchable units: vector permute unit and vector ALU unit
Contains its own 32-entry 128-bit vector register file (VRF) with six renames
The vector ALU unit is further sub-divided into the vector simple integer unit
(VSIU), the vector complex integer unit (VCIU) and the vector floating-point
unit (VFPU).
Fully pipelined
·
Load/Store Unit
One-cycle load or store cache access (byte, half-word, word, double-word)
Two-cycle load latency with one-cycle throughput
Effective address generation
Hits under misses (multiple outstanding misses)
Single-cycle unaligned access within double-word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Executes the cache and TLB instructions
Big- and little-endian byte addressing supported
Misaligned little-endian supported
Supports FXU, FPU, and AltiVec load/store traffic
Complete support for all four architecture AltiVec DST streams
·
Level 1 (L1) Cache Structure
32K 32-byte line, 8-way set associative instruction cache (iL1)
32K 32-byte line, 8-way set associative data cache (dL1)
Single-cycle cache access
Pseudo least-recently-used (LRU) replacement
Data cache supports AltiVec LRU and transient instructions algorithm
Copy-back or write-through data cache (on a page-per-page basis)
Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache
Separate copy of data cache tags for efficient snooping
No snooping of instruction cache except for ICBI instruction
·
Memory Management Unit
128 entry, 2-way set associative instruction TLB
128 entry, 2-way set associative data TLB
Hardware reload for TLBs
Four instruction BATs and four data BATs
Virtual memory support for up to four petabytes (2
52
) of virtual memory
Real memory support for up to four gigabytes (2
32
) of physical memory
Snooped and invalidated for TLBI instructions
5
PC7410M16
2183AHIREL12/02
·
Efficient Data Flow
All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are
128 bits wide
dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF
L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
Up to eight outstanding out-of-order cache misses between dL1 and L2/bus
Up to seven outstanding out-of-order transactions on the bus
Load folding to fold new dL1 misses into older outstanding load and store
misses to the same line
Store miss merging for multiple store misses to the same line. Only
coherency action taken (i.e., address only) for store misses merged to all 32
bytes of a cache line (no data tenure needed).
Two-entry finished store queue and four-entry completed store queue
between load/store unit and dL1
Separate additional queues for efficient buffering of outbound data (castouts,
write throughs, etc.) from dL1 and L2
·
Bus Interface
MPX bus extension to 60X processor interface
Mode-compatible with 60x processor interface
32-bit address bus
64-bit data bus
Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x,
6.5x, 7x, 7.5x, 8x, 9x supported
Selectable interface voltages of 1.8V, 2.5V and 3.3V
·
Power Management
Low-power design with thermal requirements very similar to PC740 and
PC750
Low voltage 1.8V processor core
Selectable interface voltages of 1.8V can reduce power in output buffers
Three static power saving modes: doze, nap, and sleep
Dynamic power management
·
Testability
LSSD scan design
IEEE 1149.1 JTAG interface
Array built-in self test (ABIST) factory test only
Redundancy on L1 data arrays and L2 tag arrays
·
Reliability and Serviceability
Parity checking on 60x and L2 cache buses
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