Document Outline
- Features / Benefits
- Table of Contents
- MARC4 Architecture
- General Description
- Components of MARC4 Core
- Interrupt Structure
- Hardware Reset
- Clock Generation
- Peripheral Modules
- Addressing Peripherals
- Bidirectional Ports
- Interval Timers / Prescaler
- Watchdog Timer
- Timer/Counter Module (TCM)
- Buzzer Module
- Emulation
- MTP Support
- Noise Considerations
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Operating Characteristics
- AC Characteristics
- Pad Layout
- Application Examples
- Ordering Information
M44C510E
Preliminary Information
Rev. A2, 26-Feb-01
1 (60)
MARC4 4-bit Universal Microcontroller
The M44C510E is a member of the Atmel Wireless & Microcontrollers' family of 4-bit single-chip microcontrollers.
It contains ROM, RAM, up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal
interrupts, a watchdog timer, interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software con-
figurable on-chip system clock module.
Features / Benefits
D Programmable system clock with prescaler and five
different clock sources:
4-MHz crystal oscillator
32-kHz crystal oscillator
RC-oscillator fully integrated
RC-oscillator with external resistor adjustment
External clock input
D Wide supply voltage range (2.2 V to 6.2 V)
D Very low halt current (< 1 mA)
D 4 KByte ROM, 256 x 4-bit RAM
D 8 hard and software interrupt priority levels
D Up to 10 external and 4 internal interrupts, bitwise
maskable with programmable priority level
D Up to 34 I/O lines including 8 high drive I/O-lines
(20 mA, V
DD
= 5 V)
D I/O ports bitwise configurable with combined inter-
rupt handling (for serial I/O applications)
D 2 x 8-bit multifunction timer/counters
D Coded reset and watchdog timer **
D Power-on reset and "brown out" function
D Various power-down modes
D Efficient, hardware-controlled interrupt handling
D High-level programming language in qFORTH
D Comprehensive library of useful routines
D Windows 95/ NT based development tools
(** mask option)
MARC4
System
clock
Timer/
counter
Timer 0
Timer 1
Master
reset
TE
Port 0 Port 1 Port 5
Port B
SCLIN
I/O bus
ROM
RAM
4bit CPU core
4K x 8 bit
256 x 4 bit
Watch
dog
I/O
I/O
I/O
Test
Sleep
NRST
VDD
VSS
Port 7
Port A
I/O
Port 4
I/O
Interrupt
& reset
Prescaler
AVDD
I/O
I/O
Interrupt
I/O
Interrupt
Port 6
Real time
clock
OSCIN OSCOUT
Melody
& buzzer
TIM1
13374
I/O
Port C
4
4
4
4
4
4
4
4
2
Figure 1. Block diagram
M44C510E
Rev. A2, 26-Feb-01
Preliminary Information
2 (60)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SC
L
I
N
BPC
0
BP0
0
BP1
2
BP1
1
BP1
0
OSCIN
OSCOUT
BP0
1
BP0
2
BP0
3
NRS
T
V
SS
VDD
BP4
3
BP4
2
BP4
1
BP4
0
BP
B
3
BP
B
2
BP
B
1
BP
B
0
BP
7
0
BP
7
1
BP
7
2
BP
7
3
BP5
3
BP5
2
BP5
1
BP5
0
TI
M
1
BP
A
3
BP
A
2
BP
A
1
BP
A
0
TE
AVD
D
BP
6
1
BP
6
0
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
23
24
41
42
43
44
BPC1
BP
1
3
VS
S
BPC3
BPC2
M44C510E
Figure 2. Pin connections SSO44-package
Table 1 Pin description
Name
Function
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
V
DD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power supply voltage +2.2 V to +6.2 V
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
AV
DD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Analog power supply voltage +2.2 V to +6.2V
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
V
SS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Circuit ground
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP00 BP03
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of Port 0 automatic nibblewise configurable
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP10 BP13
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of Port 1(*) automatic nibblewise configurable
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP50 BP53
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of high current Port 5(*) bitwise configurable
ÁÁÁÁÁÁ
BP70 BP73
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of high current Port 7(*) bitwise configurable
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BPA0 BPA3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of Port A(*) bitwise configurable, as inputs for port monitor module and optional
coded reset inputs
(*)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BPB0 BPB3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of Port B(*) bitwise configurable I/O and as inputs for port monitor module
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BPC0 BPC3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
4 I/O lines of Port C (*) bitwise configurable I/O
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP60 BP61
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
2 I/O lines of Port 6
(*) bitwise configurable I/O or as external programmable interrupts
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP40
(T0OUT0)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O line BP40 of Port 4(*) configurable or timer/counter I/O T0OUT0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP41
(T0OUT1)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I/O line BP41 of Port 4(*) configurable or timer/counter I/O T0OUT1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP42 (BUZ)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
High current I/O line BP42 of Port 4(*) configurable or buzzer output BUZ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BP43 (NBUZ)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
High current I/O line BP43 of Port 4(*) configurable or buzzer output NBUZ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TIM1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Dedicated I/O for Timer 1
ÁÁÁÁÁÁ
SCLIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
External trimming resistor or external clock input
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
OSCIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
32-kHz quartz crystal or 4-MHz quartz crystal input pin
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
OSCOUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
32-kHz quartz crystal or 4-MHz quartz crystal output pin
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Testmode input, used to control the production test modes (internal pull-down)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
NRST
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reset input (/output), a logic low on this pin resets the device. An internal watchdog or coded
reset can generate a low pulse on this pin.
(*) For mask options, please see the order information.
M44C510E
Preliminary Information
Rev. A2, 26-Feb-01
3 (60)
Table of Contents
1
MARC4 Architecture
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
General Description
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Components of MARC4 Core
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
ROM
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2
RAM
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3
Registers
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.4
ALU
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.5
Instruction Set
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.6
I/O Bus
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Interrupt Structure
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Hardware Interrupts
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Software Interrupts
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Hardware Reset
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Clock Generation
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
Clock Module
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2
Oscillator Circuits and External Clock Input Stage
14
. . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor
14
. . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3
Clock Management Register (CM)
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC)
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4
Power-down Modes
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.5
Clock Monitor Mode
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Peripheral Modules
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Addressing Peripherals
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Bidirectional Ports
20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Bidirectional Port 0 and Port 1
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Bidirectional Port 5, Port 7 and Port C
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Bidirectional Port A and Port B with Port Monitor Function
22
. . . . . . . . . . . . . . . .
2.2.4
Bidirectional Port 6
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Bidirectional Port 4
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
TIM1 Dedicated Timer 1 I/O Pin
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Interval Timers / Prescaler
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Interval Timer Registers
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Watchdog Timer
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Timer/Counter Module (TCM)
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
General Timer/Counter Control Registers
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Timer/Counter in 16-bit Mode
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Timer 0 Modes
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
Timer 1 Modes
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M44C510E
Rev. A2, 26-Feb-01
Preliminary Information
4 (60)
2.6
Buzzer Module
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Emulation
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
MTP Support
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9
Noise Considerations
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1
Noise Immunity
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2
Electromagnetic Emission
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3
Electrical Characteristics
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3.1
Absolute Maximum Ratings
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3.2
DC Operating Characteristics
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3.3
AC Characteristics
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4
Pad Layout
56
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5
Application Examples
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6
Ordering Information
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M44C510E
Preliminary Information
Rev. A2, 26-Feb-01
5 (60)
1
MARC4 Architecture
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Instruction
decoder
CCR
TOS
ALU
RAM
PC
RP
SP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
Onchip peripheral modules
94 8973
memory
Figure 3. MARC4 core
1.1
General Description
The MARC4 microcontroller consists of an advanced
stack based 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with physi-
cally separate program memory (ROM) and data memory
(RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus are used for parallel commu-
nication between ROM, RAM and peripherals. This
enhances program execution speed by allowing both
instruction prefetching, and a simultaneous communica-
tion to the on-chip peripheral circuitry. The extremely
powerful integrated interrupt controller with associated
eight prioritized interrupt levels supports fast and effi-
cient processing of hardware events. The MARC4 is
designed for the high-level programming language
qFORTH. The core includes an expression and a return
stack. This architecture allows high-level language pro-
gramming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, a program counter,
RAM address registers, an instruction decoder and an
interrupt controller. The following sections describe each
functional block in more detail:
1.2.1
ROM
The program memory (ROM) is mask programmed with
the customer application program during the fabrication
of the microcontroller. The ROM is addressed by a 12-bit
wide program counter, thus predefining a maximum pro-
gram bank size of 4 Kbytes. An additional 1 Kbyte of
ROM exists which is used partly for a quality control self-
test program. The remaining space is available for the
application program. The access to this additional ROM
section is done by using a ROM-bank switch.
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