Features

High-performance, Low-power AVR

8-bit Microcontroller

Advanced RISC Architecture

90 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation

Nonvolatile Program and Data Memories

 1K Byte In-System Programmable Flash Program Memory

Endurance: 1,000 Write/Erase Cycles

 64 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

 Programming Lock for Flash Program Data Security

Peripheral Features

Interrupt and Wake-up on Pin Change
Two 8-bit Timer/Counters with Separate Prescalers
One 150 kHz, 8-bit High-speed PWM Output
4-channel 10-bit ADC

One Differential Voltage Input with Optional Gain of 20x

On-chip Analog Comparator
Programmable Watchdog Timer with On-chip Oscillator

Special Microcontroller Features

In-System Programmable via SPI Port
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit
Internal, Calibrated 1.6 MHz Tunable Oscillator
Internal 25.6 MHz Clock Generator for Timer/Counter
External and Internal Interrupt Sources
Low-power Idle and Power-down Modes

Power Consumption at 1.6 MHz, 3V, 25

°C

Active: 3.0 mA
Idle Mode: 1.0 mA
Power-down: < 1 µA

I/O and Packages

 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines

Operating Voltages

 2.7V - 5.5V

Internal 1.6 MHz System Clock

Pin Configuration

(RESET/ADC0) PB5

(ADC3) PB4

(ADC2) PB3

GND

VCC

PB2 (ADC1/SCK/T0/INT0)

PB1 (AIN1/MISO/OC1A)

PB0 (AIN0/AREF/MOSI)

PDIP/SOIC

8-bit

Microcontroller
with 1K Byte
Flash

ATtiny15L

Rev. 1187DS12/01

Note: This is a summary document. A complete document is
available on our web site at www.atmel.com.

ATtiny15L

1187DS12/01

Description

The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny15L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.

The ATtiny15L provides 1K byte of Flash, 64 bytes EEPROM, six general purpose I/O
lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with high-
speed PWM output, internal oscillators, internal and external interrupts, programmable
Watchdog Timer, 4-channel 10-bit Analog-to-Digital Converter with one differential volt-
age input with optional 20x gain, and three software-selectable Power-saving modes.
The Idle mode stops the CPU wh ile a llowin g the ADC, analog comp arator,
Timer/Counters and interrupt system to continue functioning. The ADC Noise Reduction
mode facilitates high-accuracy ADC measurements by stopping the CPU while allowing
the ADC to continue functioning. The Power-down mode saves the register contents but
freezes the oscillators, disabling all other chip functions until the next interrupt or hard-
ware reset. The wake-up or interrupt on pin change features enable the ATtiny15L to be
highly responsive to external events, still featuring the lowest power consumption while
in the Power-saving modes.

The device is manufactured using Atmel's high-density, nonvolatile memory technology.
By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a pow-
erful microcontroller that provides a highly flexible and cost-efficient solution to many
embedded control applications. The peripheral features make the ATtiny15L particularly
suited for battery chargers, lighting ballasts and all kinds of intelligent sensor
applications.

The ATtiny15L AVR is supported with a full suite of program and system development
tools including macro assemblers, program debugger/simulators, In-circuit emulators
and evaluation kits.

ATtiny15L

1187DS12/01

Block Diagram

Figure 1. The ATtiny15L Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

HARDWARE

STACK

MCU CONTROL

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTER0

INSTRUCTION

DECODER

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PROGRAMMING

LOGIC

TIMING AND

CONTROL

TIMER/

COUNTER1

MCU STATUS

STATUS

ALU

PORT B DRIVERS

PB0-PB5

VCC

GND

CONTROL

LINES

ANALOG

COMPARATOR

8-BIT DATA BUS

ISP MODULE

INTERRUPT

UNIT

DATA

EEPROM

INTERNAL

OSCILLATOR

TUNABLE

ANALOG MUX

ADC

ATtiny15L

1187DS12/01

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB5..PB0)

Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected
for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse
and the special function associated with this pin is external Reset. The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.

Port B also accommodates analog I/O pins. The Port B pins with alternate functions are
shown in Table 1.

Analog Pins

Up to four analog inputs can be selected as inputs to Analog-to-Digital Converter (ADC).

Internal Oscillators

The internal oscillator provides a clock rate of nominally 1.6 MHz for the system clock
(CK). Due to large initial variation (0.8 -1.6 MHz) of the internal oscillator, a tuning capa-
bility is built in. Through an 8-bit control register OSCCAL the system clock rate can
be tuned with less than 1% steps of the nominal clock.

There is an internal PLL that provides a 16x clock rate locked to the system clock (CK)
for the use of the Peripheral Timer/Counter1. The nominal frequency of this peripheral
clock, PCK, is 25.6 MHz.

Table 1. Port B Alternate Functions

Port Pin

Alternate Function

PB0

MOSI (Data Input Line for Memory Downloading)

AREF (ADC Voltage Reference)

AIN0 (Analog Comparator Positive Input)

PB1

MISO (Data Output Line for Memory Downloading)

OC1A (Timer/Counter PWM Output)

AIN1 (Analog Comparator Negative Input)

PB2

SCK (Serial Clock Input for Serial Programming)

INT0 (External Interrupt0 Input)

ADC1 (ADC Input Channel 1)

T0 (Timer/Counter0 External Counter Input)

PB3

ADC2 (ADC Input Channel 2)

PB4

ADC3 (ADC Input Channel 3)

PB5

RESET (External Reset Pin)

ADC0 (ADC Input Channel 0)

ATtiny15L

1187DS12/01

ATtiny15L Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F

SREG

page 11

$3E

Reserved

$3C

Reserved

$3B

GIMSK

INT0

PCIE

page 19

$3A

GIFR

INTF0

PCIF

page 19

$39

TIMSK

OCIE1A

TOIE1

TOIE0

page 20

$38

TIFR

OCF1A

TOV1

TOV0

page 21

$37

Reserved

$36

Reserved

$35

MCUCR

PUD

SM1

SM0

ISC01

ISC00

page 22

$34

MCUSR

WDRF

BORF

EXTRF

PORF

page 17

$33

TCCR0

CS02

CS01

CS00

page 27

$32

TCNT0

Timer/Counter0 (8-Bit)

page 28

$31

OSCCAL

Oscillator Calibration Register

page 24

$30

TCCR1

CTC1

PWM1

COM1A1

COM1A0

CS13

CS12

CS11

CS10

page 30

$2F

TCNT1

Timer/Counter1 (8-Bit)

page 31

$2E

OCR1A

Timer/Counter1 Output Compare Register A (8-Bit)

page 31

$2D

OCR1B

Timer/Counter1 Output Compare Register B (8-Bit)

page 33

$2C

SFIOR

FOC1A

PSR1

PSR0

page 26

$2B

Reserved

$2A

Reserved

$29

Reserved

$28

Reserved

$27

Reserved

$26

Reserved

$25

Reserved

$24

Reserved

$23

Reserved

$22

Reserved

$21

WDTCR

WDTOE

WDE

WDP2

WDP1

WDP0

page 34

$20

Reserved

$1F

Reserved

$1E

EEAR

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

page 36

$1D

EEDR

EEPROM Data Register (8-Bit)

page 36

$1C

EECR

EERIE

EEMWE

EEWE

EERE

page 36

$1B

Reserved

$1A

Reserved

$19

Reserved

$18

PORTB

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

page 51

$17

DDRB

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

page 51

$16

PINB

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 51

$15

Reserved

$14

Reserved

$13

Reserved

$12

Reserved

$11

Reserved

$10

Reserved

$0F

Reserved

$0E

Reserved

$0D

Reserved

$0C

Reserved

$0B

Reserved

$0A

Reserved

$09

Reserved

$08

ACSR

ACD

ACBG

ACO

ACI

ACIE

ACIS1

ACIS0

page 39

$07

ADMUX

REFS1

REFS0

ADLAR

MUX2

MUX1

MUX0

page 46

$06

ADCSR

ADEN

ADSC

ADFR

ADIF

ADIE

ADPS2

ADPS1

ADPS0

page 47

$05

ADCH

ADC Data Register High Byte

page 48

$04

ADCL

ADC Data Register Low Byte

page 48

...

Reserved

$00

Reserved

Part Number ATtiny15L

Document Outline