2502FSAVR06/04

Features

High-performance, Low-power AVR

8-bit Microcontroller

Advanced RISC Architecture

130 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

 8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

 Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program
True Read-While-Write Operation

 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

512 Bytes Internal SRAM
Programming Lock for Software Security

Peripheral Features

Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC

8 Single-ended Channels
7 Differential Channels for TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP
Package Only

Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator

Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

I/O and Packages

32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad MLF

Operating Voltages

2.7 - 5.5V for ATmega8535L
4.5 - 5.5V for ATmega8535

Speed Grades

0 - 8 MHz for ATmega8535L
0 - 16 MHz for ATmega8535

8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash

ATmega8535
ATmega8535L

Preliminary
Summary

Rev. 2502FSAVR06/04

Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.

ATmega8535(L)

2502FSAVR06/04

Pin Configurations

Figure 1. Pinout ATmega8535

Disclaimer

Typical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.

(XCK/T0) PB0

(T1) PB1

(INT2/AIN0) PB2

(OC0/AIN1) PB3

(SS) PB4

(MOSI) PB5
(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2
XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2
(INT1) PD3

(OC1B) PD4
(OC1A) PD5

(ICP1) PD6

PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5
PC4
PC3
PC2
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)

(MOSI) PB5
(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2
XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5
PC4

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP1) PD6

(OC2) PD7

VCC

GND

(SCL) PC0

(SDA) PC1

PC2

PC3

PB4 (SS)

PB3 (AIN1/OC0)

PB2 (AIN0/INT2)

PB1 (T1)

PB0 (XCK/T0)

GND

VCC

P
A0 (ADC0)

P
A1 (ADC1)

P
A2 (ADC2)

P
A3 (ADC3)

(MOSI) PB5
(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2
XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5
PC4

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP1) PD6

(OC2) PD7

VCC

GND

(SCL) PC0

(SDA) PC1

PC2

PC3

PB4 (SS)

PB3 (AIN1/OC0)

PB2 (AIN0/INT2)

PB1 (T1)

PB0 (XCK/T0)

GND

VCC

P
A0 (ADC0)

P
A1 (ADC1)

P
A2 (ADC2)

P
A3 (ADC3)

PLCC

NOTE: MLF Bottom pad should be soldered to ground.

ATmega8535(L)

2502FSAVR06/04

Overview

The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing instructions in a single clock cycle, the
ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

OSCILLATOR

TIMERS/

COUNTERS

INTERRUPT

UNIT

STACK

POINTER

EEPROM

SRAM

STATUS

USART

PROGRAM

COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

PROGRAMMING

LOGIC

SPI

ADC

INTERFACE

COMP.

INTERFACE

PORTA DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

GENERAL

PURPOSE

REGISTERS

ALU

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

RESET

CONTROL

LINES

GND

MUX &

ADC

AREF

PA0 - PA7

PC0 - PC7

PD0 - PD7

PB0 - PB7

AVR CPU

TWI

AVCC

INTERNAL

CALIBRATED
OSCILLATOR

ATmega8535(L)

2502FSAVR06/04

The AVR core combines a rich instruction set with 32 general purpose working registers.
All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.

The ATmega8535 provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32
general purpose I/O lines, 32 general purpose working registers, three flexible
Timer/Counters with compare modes, internal and external interrupts, a serial program-
mable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with
optional differential input stage with programmable gain in TQFP package, a program-
mable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software
selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the
asynchronous timer continues to run, allowing the user to maintain a timer base while
the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and
all I/O modules except asynchronous timer and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption. In Extended Standby mode, both the main Oscillator and the asynchro-
nous timer continue to run.

The device is manufactured using Atmel's high density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535
is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.

The ATmega8535 AVR is supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debugger/simulators, In-
Circuit Emulators, and evaluation kits.

AT90S8535 Compatibility

The ATmega8535 provides all the features of the AT90S8535. In addition, several new
features are added. The ATmega8535 is backward compatible with AT90S8535 in most
cases. However, some incompatibilities between the two microcontrollers exist. To
solve this problem, an AT90S8535 compatibility mode can be selected by programming
the S8535C fuse. ATmega8535 is pin compatible with AT90S8535, and can replace the
AT90S8535 on current Printed Circuit Boards. However, the location of fuse bits and the
electrical characteristics differs between the two devices.

AT90S8535 Compatibility
Mode

Programming the S8535C fuse will change the following functionality:

The timed sequence for changing the Watchdog Time-out period is disabled. See
"Timed Sequences for Changing the Configuration of the Watchdog Timer" on page
43 for details.

The double buffering of the USART Receive Register is disabled. See "AVR USART
vs. AVR UART Compatibility" on page 143 for details.

ATmega8535(L)

2502FSAVR06/04

Pin Descriptions

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port A output
buffers have symmetrical drive characteristics with both high sink and source capability.
When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source
current if the internal pull-up resistors are activated. The Port A pins are tri-stated when
a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega8535 as listed
on page 58.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8535 as listed
on page 62.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 35. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally
connected to V

, even if the ADC is not used. If the ADC is used, it should be con-

nected to V

through a low-pass filter.

AREF

AREF is the analog reference pin for the A/D Converter.

Part Number ATmega8535L

Document Outline