2512GAVR03/05
Features
·
High-performance, Low-power AVR
®
8-bit Microcontroller
·
RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
·
Nonvolatile Program and Data Memories
8K Bytes of In-System Self-programmable Flash
Endurance: 10,000 Write/Erase Cycles
Optional Boot Code Section with Independent Lock bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
512 Bytes Internal SRAM
Up to 64K Bytes Optional External Memory Space
Programming Lock for Software Security
·
Peripheral Features
One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Three PWM Channels
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
·
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Three Sleep Modes: Idle, Power-down and Standby
·
I/O and Packages
35 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
·
Operating Voltages
2.7 - 5.5V for ATmega8515L
4.5 - 5.5V for ATmega8515
·
Speed Grades
0 - 8 MHz for ATmega8515L
0 - 16 MHz for ATmega8515
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega8515
ATmega8515L
Rev. 2512GAVR03/05
4
ATmega8515(L)
2512GAVR03/05
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega8515 provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an
External memory interface, 35 general purpose I/O lines, 32 general purpose working
registers, two flexible Timer/Counters with compare modes, Internal and External inter-
rupts, a Serial Programmable USART, a programmable Watchdog Timer with internal
Oscillator, a SPI serial port, and three software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt
system to continue functioning. The Power-down mode saves the Register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of
the device is sleeping. This allows very fast start-up combined with low-power
consumption.
The device is manufactured using Atmel's high density nonvolatile memory technology.
The On-chip ISP Flash allows the Program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515
is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega8515 is supported with a full suite of program and system development
tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-cir-
cuit Emulators, and Evaluation kits.
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
AT90S4414/8515 and
ATmega8515
Compatibility
The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several
n e w f e a t u r e s a r e a d d e d . T h e A T m e g a 8 5 1 5 i s b a c k w a r d c o m p a t i b l e w i t h
AT90S4414/8515 in most cases. However, some incompatibilities between the two
microcontrollers exist. To solve this problem, an AT90S4414/8515 compatibility mode
can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compati-
ble with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed
circuit boards. However, the location of Fuse bits and the electrical characteristics dif-
fers between the two devices.
AT90S4414/8515 Compatibility
Mode
Programming the S8515C Fuse will change the following functionality:
·
The timed sequence for changing the Watchdog Time-out period is disabled. See
"Timed Sequences for Changing the Configuration of the Watchdog Timer" on page
52 for details.
·
The double buffering of the USART Receive Registers is disabled. See "AVR
USART vs. AVR UART Compatibility" on page 135 for details.
·
PORTE(2:1) will be set as output, and PORTE0 will be set as input.
5
ATmega8515(L)
2512GAVR03/05
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. When pins PA0 to PA7 are used as inputs and are externally
pulled low, they will source current if the internal pull-up resistors are activated. The Port
A pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Port A also serves the functions of various special features of the ATmega8515 as listed
on page 66.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8515 as listed
on page 66.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8515 as listed
on page 71.
Port E(PE2..PE0)
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega8515 as listed
on page 73.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
18 on page 45. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
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