Features
·
High Performance, Low Power AVR
®
8-bit Microcontroller
·
Advanced RISC Architecture
124 Powerful Instructions - Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 1 MIPS Throughput at 1 MHz
·
Nonvolatile Program and Data Memories
40K Bytes of In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase
Cycles
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
512 bytes EEPROM, Endurance: 100,000 Write/Erase Cycles
2K Bytes Internal SRAM
Programming Lock for Software Security
·
On-chip Debugging
Extensive On-chip Debug Support
Available through JTAG interface
·
Battery Management Features
Two, Three, or Four Cells in Series
Deep Under-voltage Protection
Over-current Protection (Charge and Discharge)
Short-circuit Protection (Discharge)
Integrated Cell Balancing FETs
High Voltage Outputs to Drive Charge/Precharge/Discharge FETs
·
Peripheral Features
One 8-bit Timer/Counter with Separate Prescaler, Compare Mode, and PWM
One 16-bit Timer/Counter with Separate Prescaler and Compare Mode
12-bit Voltage ADC, Eight External and Two Internal ADC Inputs
High Resolution Coulomb Counter ADC for Current Measurements
TWI Serial Interface for SM-Bus
Programmable Wake-up Timer
Programmable Watchdog Timer
·
Special Microcontroller Features
Power-on Reset
On-chip Voltage Regulator
External and Internal Interrupt Sources
Four Sleep Modes: Idle, Power-save, Power-down, and Power-off
·
Packages
48-pin LQFP
·
Operating Voltage: 4.0 - 25V
·
Maximum Withstand Voltage (High-voltage pins): 28V
·
Temperature Range: -30°C to 85°C
Speed Grade: 1 MHz
8-bit
Microcontroller
with 40K Bytes
In-System
Programmable
Flash
ATmega406
Preliminary
Summary
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
2548ASAVR01/05
2
2548ASAVR01/05
ATmega406
1.
Pin Configurations
Figure 1-1.
Pinout ATmega406.
1.1
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
SGND
(ADC0/PCINT0) PA0
(ADC1/PCINT1) PA1
(ADC2/PCINT2) PA2
(ADC3/PCINT3) PA3
VREG
VCC
GND
(ADC4/INT0/PCINT4) PA4
(INT1/PCINT5) PA5
(INT2/PCINT6) PA6
(INT3/PCINT7) PA7
PVT
OD
VFET
OC
OPC
BATT
PC0
GND
PD1
PD0 (T0)
PB7 (OC0B/PCINT15)
PB6 (OC0A/PCINT14)
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
RESET
XTAL1
XTAL2
GND
(TDO/PCINT8) PB0
(TDI/PCINT9) PB1
(TMS/PCINT10) PB2
(TCK/PCINT11) PB3
(PCINT12) PB4
(PCINT13) PB5
SCL
SDA
NNI
NI
PI
PPI
VREFGND
VREF
NV
PV1
PV2
PV3
PV4
GND
Top View
3
2548ASAVR01/05
ATmega406
2.
Overview
The ATmega406 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega406
achieves throughputs approaching 1 MIPS at 1 MHz.
2.1
Block Diagram
Figure 2-1.
Block Diagram
The ATmega406 provides the following features: a Voltage Regulator, dedicated Battery Protec-
tion Circuitry, integrated cell balancing FETs, high-voltage analog front-end, and an MCU with
two ADCs with On-chip voltage reference for battery fuel gauging.
The voltage regulator operates at a wide range of voltages, 4.0 - 25 volts. This voltage is regu-
lated to a constant supply voltage of nominally 3.3 volts for the integrated logic and analog
functions.
The battery protection monitors the battery voltage and charge/discharge current to detect illegal
conditions and protect the battery from these when required. The illegal conditions are deep
under-voltage during discharging and short-circuit during discharging, and over-current during
charging and discharging.
PORTA (8)
TWI
SRAM
Flash
CPU
EEPROM
PV2
NV
OPC
OC
OD
FET
Control
Battery
Protection
Voltage
ADC
Voltage
Reference
Coulumb
Counter ADC
GND
VCC
RESET
Power
Supervision
POR &
RESET
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
PPI
NNI
PVT
SGND
VREF
VREFGND
PI
NI
PA7..0
PA3..0
16 bit T/C1
8 bit T/C0
PORTB (8)
PB7..0
JTAG
Wake-Up
Timer
Voltage
Regulator
Charger
Detect
VFET
VREG
BATT
PV1
DATA BUS
PORTC (1)
PC0
SCA
SCL
Cell
Balancing
PV3
PV4
PORTD (2)
PD1..0
XTAL1
XTAL2
4
2548ASAVR01/05
ATmega406
The integrated cell balancing FETs allow cell balancing algorithms to be implemented in
software.
The MCU provides the following features: 40K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose working
registers, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chip
Debugging support and programming, two flexible Timer/Counters with PWM and compare
modes, one Wake-up Timer, an SM-Bus compliant TWI module, internal and external interrupts,
a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma
Delta ADC for Coulomb Counting and instantaneous current measurements, a programmable
Watchdog Timer with internal Oscillator, and four software selectable power saving modes.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The Idle mode stops the CPU while allowing the other chip function to continue functioning. The
Power-down mode allows the voltage regulator, battery protection, regulator current detection,
Watchdog Timer, and Wake-up Timer to operate, while disabling all other chip functions until the
next Interrupt or Hardware Reset. In Power-save mode, the Wake-up Timer and Coulomb
Counter ADC continues to run.
The device is manufactured using Atmel's high voltage high density non-volatile memory tech-
nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, by
a conventional non-volatile memory programmer or by an On-chip Boot program running on the
AVR core. The Boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash section will continue to run while the
Application Flash section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash, fuel gauging ADCs, dedicated bat-
tery protection circuitry, Cell Balancing FETs, and a voltage regulator on a monolithic chip, the
Atmel ATmega406 is a powerful microcontroller that provides a highly flexible and cost effective
solution for Li-ion Smart Battery applications.
The ATmega406 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip
Debugger.
5
2548ASAVR01/05
ATmega406
2.2
Pin Descriptions
2.2.1
VFET
Input to the internal voltage regulator.
2.2.2
VCC
Digital supply voltage. Normally connected to VREG.
2.2.3
VREG
Output from the internal voltage regulator.
2.2.4
VREF
Internal Voltage Reference for external decoupling.
2.2.5
VREFGND
Ground for decoupling of Internal Voltage Reference.
2.2.6
GND
Ground
2.2.7
SGND
Signal Ground.
2.2.8
Port A (PA7:PA0)
PA3:PA0 serves as the analog inputs to the Voltage A/D Converter.
Port A also serves as a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega406 as listed in
"Alter-
nate Functions of Port A" on page 69
.
2.2.9
Port B (PB7:PB0)
Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega406 as listed in
"Alter-
nate Functions of Port B" on page 71
.
2.2.10
Port C (PC0)
Port C is a high voltage Open Drain output port.
2.2.11
Port D (PD1:PD0)
Port D is a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port D pins that are externally pulled low will source current if the pull-up
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