Features

Available in Gate Array or Embedded Array

High-speed, 100 ps Gate Delay, 2-input NAND, FO = 2 (nominal)

Up to 6.9 Million Used Gates and 976 Pins

0.25µ Geometry in up to Five-level Metal

System-level Integration Technology

 Cores: ARM7TDMI

, ARM920T

, ARM946E-S

and MIPS64

5Kf

RISC

Microprocessors; AVR

RISC Microcontroller; OakDSPCore

, Teak

and

PalmDSPCore

Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284,

CAN and Other Assorted Processor Peripherals

Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs
Soft Macro Memory: Gate Array

SRAM -- ROM -- DPSRAM -- FIFO

 Hard Macro Memory: Embedded Array

SRAM -- ROM -- DPSRAM -- FIFO -- Stacked E

-- Stacked Flash

 I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 16 mA

@2.5V; 2.5V Native I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O

Description

The ATL25 Series ASIC family is fabricated on a 0.25µ CMOS process with up to five
levels of metal. This family features arrays with up to 6.9 million routable gates and
976 pins. The high density and high pin count capabilities of the ATL25 family, coupled
with the ability to add embedded microprocessor cores, DSP engines and memory on
the same silicon, make the ATL25 series of ASICs an ideal choice for system-level
integration.

Figure 1. ATL25 Gate Array ASIC

Figure 2. ATL25 Embedded Array ASIC

Standard

Gate Array

Architecture

Standard

Gate Array

Architecture

Analog

ASIC

ATL25 Series

1414CASIC-08/02

ATL25 Series ASIC

1414CASIC-08/02

Table 1. ATL25 Array Organization

Notes:

1. One gate = NAND2
2. Routing site = 4 transistors
3. Nominal 2-input NAND gate FO = 2 at 2.5V

Device

Number

4LM Routable

Gates

(1)

5LM Routable

Gates

(1)

Available

Routing Sites

(2)

Max Pad

Count

Max I/O Count

Gate

Speed

(3)

ATL25/44

9,535

10,727

15,892

100 ps

ATL25/68

30,096

33,858

50,161

100 ps

ATL25/84

50,410

56,712

84,018

100 ps

ATL25/100

75,472

84,906

125,788

100

100 ps

ATL25/120

106,278

120,449

188,940

120

112

100 ps

ATL25/132

131,670

149,226

234,080

132

124

100 ps

ATL25/144

159,778

181,081

284,050

144

136

100 ps

ATL25/160

200,998

227,797

357,330

160

152

100 ps

ATL25/184

270,663

306,751

481,179

184

176

100 ps

ATL25/208

329,281

376,321

627,203

208

200

100 ps

ATL25/228

401,010

458,298

763,830

228

220

100 ps

ATL25/256

512,398

585,598

975,998

256

248

100 ps

ATL25/304

733,635

838,440

1,397,400

304

296

100 ps

ATL25/352

925,815

1,068,248

1,899,108

352

344

100 ps

ATL25/388

1,133,594

1,307,994

2,325,323

388

380

100 ps

ATL25/432

1,417,125

1,635,145

2,906,925

432

424

100 ps

ATL25/484

1,651,406

1,926,640

3,669,792

484

476

100 ps

ATL25/540

2,069,052

2,413,894

4,597,895

540

532

100 ps

ATL25/600

2,567,790

2,995,755

5,706,200

600

592

100 ps

ATL25/700

3,520,954

4,107,780

7,824,344

700

692

100 ps

ATL25/800

4,231,979

5,001,430

10,259,344

800

792

100 ps

ATL25/900

5,378,257

6,356,122

13,038,200

900

892

100 ps

ATL25/976

5,765,320

6,918,384

15,374,188

976

968

100 ps

ATL25 Series ASIC

1414CASIC-08/02

Design

Atmel supports several major software systems for design with complete cell libraries, as well
as utilities for netlist verification, test vector verification and accurate delay simulations

Table 2. Design Systems Supported

Atmel's ASIC design flow is structured to allow the designer to consolidate the greatest num-
ber of system components onto the same silicon chip, using widely available third-party design
tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage
and process, and includes the effects of metal loading, interlevel capacitance, and edge rise
and fall times. The design flow includes clock tree synthesis to customer-specified skew and
latency goals. RC extraction is performed on the final design database and incorporated into
the timing analysis.

The ASIC design flow, shown on page 4, provides a pictorial description of the typical interac-
tion between Atmel's design staff and the customer. Atmel will deliver design kits to support
the customer's synthesis, verification, floorplanning and scan insertion activities. Leading-
edge tools from vendors such as Synopsys and Cadence are fully supported in our design
flow. In the case of an embedded array design, Atmel will conduct a design review with the
customer to define the partition of the embedded array ASIC and to define the location of the
memory blocks and/or cores so an underlayer layout model can be created.

Following database acceptance, automated test pattern generation (ATPG) is performed, if
required, on scan paths using Synopsys tools; the design is routed; and post-route RC data is
extracted. After post-route verification and a final design review, the design is taped out for
fabrication.

System

Tools

Version

Cadence

Design
Systems, Inc.

Opus

Schematic and Layout

NC Verilog

Verilog Simulator

Pearl

Static Path

Verilog-XL

Verilog Simulator

BuildGates

Synthesis (Ambit)

4.46

3.3-s008

4.3-s095

3.3-s006

4.0-p003

Mentor
Graphics

ModelSim

Verilog and VHDL (VITAL) Simulator

Leonardo Spectrum

Logic Synthesis

5.5e

2001.1d

Synopsys

Design Compiler

Synthesis

DFT Compiler 1-Pass Test Synthesis

BSD Compiler Boundary Scan Synthesis

TetraMax

Automatic Test Pattern Generation

PrimeTime

Static Path

VCS

Verilog Simulator

Floorplan Manager

01.01-SP1

01.08-SP1

01.08

01.08-SP1

5.2

01.08-SP1

Novas
Software, Inc.

Debussy

5.1

Silicon
Perspective

First Encounter

v2001.2.3

ATL25 Series ASIC

1414CASIC-08/02

Table 3. Design Flow

Final Design

Review

Place and Route/

Clock Tree

Verification/

Resimulation

Define

Underlayer

Fabricate

Underlayer

Create

Underlayer

Tape Out

Underlayer

Scan/JTAG

Floorplan

Simulation/

Static Path

Synthesis/

Design Entry

Deliver

Design Kit

Kickoff

Meeting

Atmel

Joint

Database

Handoff

If Embedded Array

Customer

Database

Acceptance

If Embedded Array

(Preliminary Netlist)

Fabricate

Personality

Tape Out

Metal Masks

Proto Assembly

and Test

Rev. 2.2-03/02

Fabricate

Tape Out

Full Mask Set

If Embedded/Gate Array

If Standard Cell

Proto Shipment

ATL25 Series ASIC

1414CASIC-08/02

Pin Definition
Requirements

The corner pads are reserved for power and ground only. All other pads are fully programma-
ble as input, output, bidirectional, power, or ground. When implementing a design with 3.3V
compliant buffers, an appropriate number of pad sites must be reserved for the V

3 pins,

which are used to distribute 3.3V power to the compliant buffers.

Design Options

Logic Synthesis

Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synop-
sys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and
VHDL, Atmel's preferred HDL format for ASIC design is Verilog.

ASIC Design
Translation

Atmel has successfully translated existing designs from most major ASIC vendors into Atmel
ASICs. These designs have been optimized for speed and gate count and modified to add
logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement.

FPGA and PLD
Conversions

Atmel has successfully translated existing FPGA/PLD designs from most major vendors into
Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC:

Conversion of high-volume devices for a single or combined design is cost effective.

Performance can often be optimized for speed or low power consumption.

Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing
on-board space requirements.

In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may
provide a lower cost answer for long-term volume production.

Part Number ATL25

Document Outline