1
Features
·
Designed to Store Configurator Programs for Field Programmable System Level
Integrated Circuits (FPSLICs)
·
In-System Programmable (ISP) via 2-wire Bus
·
Spare Memory Available for System Parameters Storage
·
Low-power CMOS EEPROM Process
·
Available in 6 mm x 6 mm x 1 mm 8-lead LAP Package (Pin Compatible Across Product
Family)
·
Emulation of Atmel's AT24CXXX Serial EEPROMs
·
Available in 3.3V ± 10% LV
·
Low-power Standby Mode
·
High-reliability
Endurance: 100,000 Write Cycles
Data Retention: 90 Years for Industrial Parts (at 85
°C) and 190 Years for
Commercial Parts (at 70
°C)
Description
The FPSLIC Support Devices provide an easy-to-use, cost-effective configuration
memory for programming Field Programmable System Level Integrated Circuits by
using a simple serial-access procedure to configure one or more FPSLIC devices.
See Table 1 for a list of supported FPSLIC devices.
The FPSLIC Support Device can be programmed with industry-standard program-
mers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable.
Pin Configurations
8-lead LAP
Table 1. ATFS FPSLIC Support Devices
FPSLIC Device
FPSLIC Support Device
Configuration Data
Spare Memory
AT94K05
ATFS05
226520 Bits
35624 Bits
AT94K10
ATFS10
430488 Bits
93800 Bits
AT94K40
ATFS40
815382 Bits
233194 Bits
8
7
6
5
1
2
3
4
DATA
CLK
RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
Support Device
ATFS05
ATFS10
ATFS40
Advance
Information
Rev. 3017CFPSLI07/02
2
ATFS05/10/40
3017CFPSLI07/02
Block Diagram
Device Description
The control signals for the FPSLIC Support Device (CE, RESET/OE and CCLK) inter-
face directly with the FPSLIC control signals. All FPSLIC devices can control the entire
configuration process and retrieve data from the FPSLIC Support Device without requir-
ing an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven Low, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also con-
trols the output of the FPSLIC Support Device. If CE is held High after the RESET/OE
reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is
subsequently driven High, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is
tri-stated, regardless of the state of CE.
When the FPSLIC Support Device has driven out all of its data and CEO is driven Low,
the device tri-states the DATA pin to avoid contention with other FPSLIC Support
Devices. Upon power-up, the address counter is automatically reset.
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
CE
CLK
RESET/OE
CEO(A2)
DATA
BIT
COUNTER
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER ON
RESET
SER_EN
3
ATFS05/10/40
3017CFPSLI07/02
Pin Description
8 LAP
Pin
Name
I/O
Description
1
DATA
I/O
Tri-state DATA output for configuration. Open-collector bi-directional pin for programming.
2
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and programming.
3
RESET/
OE
I
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver.
4
CE
I
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the
address counter and enables the data output driver. A High level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will
not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low).
5
GND
Ground pin. A 0.2 µF decoupling capacitor between
V
CC
and GND is recommended.
6
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
7
SER_EN
I
Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to V
CC
.
8
V
CC
+3.3V power supply pin
4
ATFS05/10/40
3017CFPSLI07/02
FPSLIC Master Serial
Mode Summary
The I/O and logic functions of the FPSLIC devices are established by a configuration
program. The program is loaded either automatically upon power-up, or on command,
depending on the state of the mode pins. In Master Mode, the FPSLIC automatically
loads the configuration program from an external memory. The FPSLIC Support Device
has been designed for compatibility with the Master Mode.
Control of
Configuration
Most connections between the FPSLIC device and the FPSLIC Support Device are sim-
ple and self-explanatory:
·
The DATA output of the FPSLIC Support Device drives DIN of the FPSLIC devices.
·
The master FPSLIC CCLK output drives the CLK input of the FPSLIC Support
Device.
·
SER_EN must be connected to V
CC
(except during ISP).
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at V
CC
supply only.
Programming super voltages are generated inside the chip.
Standby Mode
The FPSLIC Support Device enters a low-power standby mode whenever CE is
asserted High. In this mode, the ATFS05 consumes less than 50 µA of current at 3.3V.
The output remains in a high-impedance state regardless of the state of the OE input.
5
ATFS05/10/40
3017CFPSLI07/02
Example Circuits
Figure 1. FPSLIC Support Device for Programming FPSLIC Devices
The FPSLIC's bi-directional CON pin drives the CE input of the FPSLIC Support Device, while the RESET/OE input is
driven by the FPSLIC's bi-directional INIT pin. This connection works under all normal circumstances, even when the user
aborts the configuration before CON has gone High. A Low level on the RESET/OE input, during FPSLIC reset, clears the
FPSLIC Support Device's internal address pointer so that the reconfiguration starts at the beginning.
The spare memory can be accessed by in-system programming the ATFS through a two-wire serial interface built in the
FPSLIC device. For more information, refer to the "C Code for Interfacing the FPSLIC AVR Core to AT17 Series Configura-
tion Memories" application note, available on the Atmel web site (www.atmel.com).
Figure 2. In-System Programming of FPSLIC Support Devices
V
CC
DATA0
CCLK
CON
INIT
FPSLIC Support Device
SER_EN
DATA
CLK
CE
RESET/OE
RESET
AT94K
GND
RESET
M2
M1
M0
V
2
4
6
8
10
DATA
1
CLK
3
5
7
9
SER_EN
CC
V
CC
V
CC
4.7 k
9
4.7 k
9
GND
FPSLIC Support Device
AT94K
DATA0
CCLK
CON
INIT
SER_EN
DATA
CLK
CE
RESET/OE
RESET
GND
RESET
M2
M1
M0
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