Rev. 4535C4BMCU02/04
Features
·
4-Kbyte ROM, 256
×
4-bit RAM
·
16 Bidirectional I/Os
·
Up to 7 External/Internal Interrupt Sources
·
Multifunction Timer/Counter with
IR Remote Control Carrier Generator
Bi-phase-, Manchester- and Pulse-width Modulator and Demodulator
Phase Control Function
·
Programmable System Clock with Prescaler and Five Different Clock Sources
·
Wide Supply-voltage Range (1.8 V to 6.5 V)
·
Very Low Sleep Current (< 1 µA)
·
32
×
16-bit EEPROM (ATAR892 only)
·
Synchronous Serial Interface (2-wire, 3-wire)
·
Watchdog, POR and Brown-out Function
·
Voltage Monitoring Inclusive Lo_BAT Detect
·
Flash Controller ATAM893 Available (SSO20)
Description
The ATAR092 and ATAR892 are members of Atmel's family of 4-bit single-chip micro-
controllers. They offer highest integration for IR and RF data communication, remote-
control and phase-control applications. The ATAR092 and ATAR892 are suitable for
the transmitter side as well as the receiver side. They contain ROM, RAM, parallel I/O
ports, two 8-bit programmable multifunction timer/counters with modulator and
demodulator function, voltage supervisor, interval timer with watchdog function and a
sophisticated on-chip clock generation with external clock input, integrated RC-,
32-kHz crystal- and 4-MHz crystal-oscillators. The ATAR892 has an additional
EEPROM as a second chip in one package.
Figure 1. Block Diagram
V
DD
T2I
SD
Voltage monitor
External input
MARC4
UTCM
OSC1
OSC2
I/O bus
ROM
RAM
4-bit CPU core
256 x 4 bit
V
SS
Data direction +
alternate function
Data direction +
interrupt control
Port 4
Port 5
Data direction +
alternate function
Port 6
Timer 3
Brown-out protect.
RESET
Clock management
Timer 1
watchdog timer
Timer 2
Serial interface
Port 1
P
o
r
t
2
D
a
t
a
d
i
r
e
c
t
i
o
n
T2O
SD
SC
T3O
T3I
BP10
BP13
BP20/NTE
BP21
BP22
BP23
BP40
INT3
SC
BP41
VMI
BP42
T2O
BP43
INT3
BP50
INT6
BP51
INT6
BP52
INT1
BP53
INT1
BP60
T3O
BP63
T3I
RC
oscillators
Crystal
oscillators
4 K x 8 bit
VMI
with modulator
SSI
External
clock input
interval- and
8/12-bit timer
8-bit
timer/counter
with modulator
and demodulator
T2I
Low-current
Microcontroller
for Wireless
Communication
ATAR092
ATAR892
2
ATAR092/ATAR892
4535C4BMCU02/04
Pin Configuration
Figure 2. Pinning SSO20
VDD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
OSC2
BP60/T3O
BP10
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
BP63/T3I
BP13
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Pin Description
Name
Type
Function
Alternate Function
Pin No.
Reset State
VDD
Supply
voltage
1
NA
VSS
Circuit ground
20
NA
BP10
I/O
Bidirectional I/O line of Port 1.0
10
Input
BP13
I/O
Bidirectional I/O line of Port 1.3
11
Input
BP20
I/O
Bidirectional I/O line of Port 2.0
NTE-test mode enable, see section "Master Reset"
13
Input
BP21
I/O
Bidirectional I/O line of Port 2.1
14
Input
BP22
I/O
Bidirectional I/O line of Port 2.2
15
Input
BP23
I/O
Bidirectional I/O line of Port 2.3
16
Input
BP40
I/O
Bidirectional I/O line of Port 4.0
SC-serial clock or INT3 external interrupt input
2
Input
BP41
I/O
Bidirectional I/O line of Port 4.1
VMI voltage monitor input or T2I external clock
input Timer 2
17
Input
BP42
I/O
Bidirectional I/O line of Port 4.2
T2O Timer 2 output
18
Input
BP43
I/O
Bidirectional I/O line of Port 4.3
SD serial data I/O or INT3-external interrupt input
19
Input
BP50
I/O
Bidirectional I/O line of Port 5.0
INT6 external interrupt input
6
Input
BP51
I/O
Bidirectional I/O line of Port 5.1
INT6 external interrupt input
5
Input
BP52
I/O
Bidirectional I/O line of Port 5.2
INT1 external interrupt input
4
Input
BP53
I/O
Bidirectional I/O line of Port 5.3
INT1 external interrupt input
3
Input
BP60
I/O
Bidirectional I/O line of Port 6.0
T3O Timer 3 output
9
Input
BP63
I/O
Bidirectional I/O line of Port 6.3
T3I Timer 3 input
12
Input
OSC1
I
Oscillator input
4-MHz crystal input or 32-kHz crystal input or
external clock input or external trimming resistor
input
7
Input
OSC2
O
Oscillator output
4-MHz crystal output or 32-kHz crystal output or
external clock input
8
NA
3
ATAR092/ATAR892
4535C4BMCU02/04
Introduction
The ATAR092/ATAR892 are members of Atmel's family of 4-bit single-chip microcon-
trollers. They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multi-
function timer/counters, voltage supervisor, interval timer with watchdog function and a
sophisticated on-chip clock generation with integrated RC-, 32-kHz crystal- and 4-MHz
crystal oscillators.
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and
on-chip peripherals. The CPU is based on the HARVARD architecture with physically
separate program memory (ROM) and data memory (RAM). Three independent buses,
the instruction bus, the memory bus and the I/O bus, are used for parallel communica-
tion between ROM, RAM and peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous communication to the on-chip
peripheral circuitry. The extremely powerful integrated interrupt controller with associ-
ated eight prioritized interrupt levels supports fast and efficient processing of hardware
events. The MARC4 is designed for the high-level programming language qFORTH.
The core includes both an expression and a return stack. This architecture enables
high-level language programming without any loss of efficiency or code density.
Figure 3. MARC4 Core
Table 1. Available Variants of ATAxx9x
Version
Type
ROM
E2PROM Peripheral
Packages
Flash device
ATAM893
4-Kbyte EEPROM
64 byte
SSO20
Production
ATAR092 4-Kbyte
mask
ROM
SSO20
Production
ATAR892
4-Kbyte mask ROM
64 byte
SSO20
Instruction
decoder
CCR
TOS
ALU
RAM
RP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
On-chip peripheral modules
memory
SP
PC
4
ATAR092/ATAR892
4535C4BMCU02/04
Components of MARC4
Core
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruc-
tion decoder and interrupt controller. The following sections describe each functional
block in more detail.
ROM
The program memory (ROM) is mask programmed with the customer application pro-
gram during the fabrication of the microcontroller. The ROM is addressed by a 12-bit
wide program counter, thus predefining a maximum program bank size of 4 Kbytes. An
additional 1 Kbyte of ROM exists which is reserved for quality control self-test software
The lowest user ROM address segment is taken up by a 512-byte zero page which con-
tains predefined start addresses for interrupt service routines and special subroutines
accessible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4 Look-up tables of constants can
also be held in ROM and are accessed via the MARC4's built-in table instruction.
Figure 4. ROM Map
RAM
The ATAR092 and ATAR892 contain 256 x 4-bit wide static random access memory
(RAM). It is used for the expression stack, the return stack and data memory for vari-
ables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address
registers SP, RP, X and Y.
Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands from, and return
their results to the expression stack. The MARC4 performs the operations with the top of
stack items (TOS and TOS-1). The TOS register contains the top element of the expres-
sion stack and works in the same way as an accumulator. This stack is also used for
passing parameters between subroutines and as a scratch pad area for temporary stor-
age of data.
Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
ROM
(4 K x 8 bit)
Zero page
FFFh
7FFh
1FFh
000h
1F0h
1F8 h
010 h
018 h
000h
008h
020h
1E8h
1E0h
S
C
A
LL addresses
140h
180h
040h
0 C 0h
008h
$AUTOSLEEP
$RESET
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
1E0h
1 C 0h
1 00h
0 80h
page
0 00h
Zero
5
ATAR092/ATAR892
4535C4BMCU02/04
Figure 5. RAM Map
Registers
The MARC4 controller has seven programmable registers and one condition code regis-
ter. They are shown in the following programming model.
Program Counter (PC)
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from the ROM. Instructions currently being executed are decoded in
the instruction decoder to determine the internal micro-operations. For linear code (no
calls or branches) the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the table instruction
to fetch 8-bit wide ROM constants.
Figure 6. Programming Model
RAM
FCh
00h
Autosleep
FFh
03h
04h
X
Y
SP
RP
TOS-1
Expression
stack
Return
stack
Global
variables
R
A
M address r
egister:
07h
(256 x 4-bit)
Global
variables
4-bit
TOS
TOS-1
TOS-2
3
0
SP
Expression stack
Return stack
0
11
12-bit
RP
v
TOS
CCR
0
3
0
3
0
7
0
7
7
0
11
RP
SP
X
Y
PC
--
B
I
Program counter
Return stack pointer
Expression stack pointer
RAM address register (X)
RAM address register (Y)
Top of stack register
Condition code register
Carry/borrow
Branch
Interrupt enable
Reserved
0
7
C
0
0
0
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