Features/Benefits
·
Very Low Power Consumption in Active, Power-down and Sleep Mode
·
2-Kbyte ROM, 256
×
4-bit RAM
·
12 Bi-directional I/Os
·
Up to 6 External/Internal Interrupt Sources
·
Multifunction Timer/Counter
·
Programmable System-clock with Prescaler and Five Different Clock Sources
·
Wide Supply-voltage Range (1.8 V to 6.5 V)
·
Very Low Sleep Current (< 1 µA)
·
Synchronous Serial Interface (2-wire, 3-wire)
·
Watchdog, POR and Brown-out Function
·
Voltage Monitoring Inclusive Lo_BAT Detection
·
Flash Controller ATAM893 available (SSO20)
Description
The ATAR080 is a member of Atmel's family of 4-bit single-chip microcontrollers. It
contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter with modulator function, voltage supervision, interval timer with watch-
dog function and a sophisticated on-chip clock generation with external clock input,
integrated RC-, 32-kHz and 4-MHz crystal-oscillators.
Figure 1. Block Diagram
Voltage Monitor
External input
MARC4
4-bit CPU core
UTCM
OSC1
NRST/
OSC2
I/O bus
ROM
2 K
×
8 bit
RAM
256
×
4 bit
VSS
Data direction +
alternate function
Port 4
Port 5
Clock management
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
P
o
r
t
2
D
a
t
a
d
i
r
e
c
t
i
o
n
T2O
SD
SC
BP20/NTE
BP21
BP22
BP23
BP40
INT3
SC
BP41
VMI
T2I
BP43
INT3
SD
BP42
T2O
RC
oscillators
VMI
T2I
VDD
Brown-out
protect RESET
Crystal
oscillators
External
clock input
Data direction +
interrupt control
SSI
Serial interface
BP50
INT6
BP51
INT6
BP52
INT1
BP53
INT1
Low-current
Microcontroller
for Wireless
Communication
ATAR080
Rev. 4675D4BMCU12/04
2
ATAR080
4675D4BMCU12/04
Pin Configuration
Figure 2. Pinning SSO20
VDD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
NRST/OSC2
NC
NC
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Pin Description
Pin
Type
Function
Alternate Function
Pin No.
SSO20
Reset
State
VDD
Supply voltage
1
NA
VSS
Circuit ground
20
NA
NC
Not connected
10
NC
Not connected
11
BP20
I/O
Bi-directional I/O line of Port 2.0
NTE test mode enable, see section "Master Reset"
13
Input
BP21
I/O
Bi-directional I/O line of Port 2.1
14
Input
BP22
I/O
Bi-directional I/O line of Port 2.2
15
Input
BP23
I/O
Bi-directional I/O line of Port 2.3
16
Input
BP40
I/O
Bi-directional I/O line of Port 4.0
SC serial clock or INT3 external interrupt input
2
Input
BP41
I/O
Bi-directional I/O line of Port 4.1
VMI voltage monitor input or T2I external clock input
Timer 2
17
Input
BP42
I/O
Bi-directional I/O line of Port 4.2
T2O Timer 2 output
18
Input
BP43
I/O
Bi-directional I/O line of Port 4.3
SD serial data I/O or INT3-external interrupt input
19
Input
BP50
I/O
Bi-directional I/O line of Port 5.0
INT6 external interrupt input
6
Input
BP51
I/O
Bi-directional I/O line of Port 5.1
INT6 external interrupt input
5
Input
BP52
I/O
Bi-directional I/O line of Port 5.2
INT1 external interrupt input
4
Input
BP53
I/O
Bi-directional I/O line of Port 5.3
INT1 external interrupt input
3
Input
NC
Not connected
9
NC
Not connected
12
OSC1
I
Oscillator input
4-MHz crystal input or 32-kHz crystal input or external
clock input or external trimming resistor input
7
Input
NRST/
OSC2
I/O
O
Reset input/output
Oscillator output
4-MHz crystal output or 32-kHz crystal output or
NRST (mask option) or external clock input
8
NA
3
ATAR080
4675D4BMCU12/04
Introduction
The ATAR080 is a member of Atmel's family of 4-bit single-chip microcontrollers. They
contain ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction
timer/counter, voltage supervision, interval timer with watchdog function and a sophisti-
cated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal-
oscillators.
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and
on-chip peripherals. The CPU is based on the Harvard architecture with physically sep-
arated program memory (ROM) and data memory (RAM). Three independent buses,
the instruction bus, the memory bus and the I/O bus, are used for parallel communica-
tion between ROM, RAM and peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous communication to the on-chip
peripheral circuitry. The extremely powerful integrated interrupt controller with associ-
ated eight prioritized interrupt levels supports fast and efficient processing of hardware
events. The MARC4 is designed for the high-level programming language qFORTH.
The core includes both, an expression and a return stack. This architecture enables
high-level language programming without any loss of efficiency or code density.
Figure 3. MARC4 Core
ALU
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
On-chip peripheral modules
System
clock
Reset
Interrupt
controller
Instruction
decoder
Program
memory
PC
RAM
256 x 4-bit
X
Y
SP
RP
CCR
TOS
ALU
4
ATAR080
4675D4BMCU12/04
Components of MARC4
Core
Figure 4. ROM Map
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruc-
tion decoder and interrupt controller. The following sections describe each functional
block in more detail.
ROM
The program memory (ROM) is mask programmed with the customer application pro-
gram during fabrication of the microcontroller. The 2 Kbyte ROM size is addressed by a
12-bit wide program counter. An additional 1-Kbyte of ROM exists, which is reserved for
quality control self-test software The lowest user ROM address segment is taken up by
a 512-byte Zero page which contains predefined start addresses for interrupt service
routines and special subroutines accessible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4. Look-up tables of constants can
also be held in ROM and are accessed via the MARC4's built-in table instruction.
RAM
The ATAR080 contains 256
×
4-bit wide static random access memory (RAM), which is
used for the expression stack. The return stack and data memory are used for variables
and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers
SP, RP, X and Y.
Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands, and return their
results to the expression stack. The MARC4 performs the operations with the top of
stack items (TOS and TOS-1). The TOS register contains the top element of the expres-
sion stack and works in the same way as an accumulator. This stack is also used for
passing parameters between subroutines and as a scratch pad area for temporary stor-
age of data.
Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
7FFh
1FFh
000h
1F0h
1F8h
010h
018h
000h
008h
020h
1E8h
1E0h
S
C
A
LL addres
s
e
s
140h
180h
040h
0C0h
008h
$AUTOSLEEP
$RESET
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
1E0h
1C0h
100h
080h
000h
ROM
(2 K
×
8 bit)
Zero page
Zero
page
5
ATAR080
4675D4BMCU12/04
Figure 5. RAM Map
Registers
The microcontroller has seven programmable registers and one condition code register
(see Figure 6).
Program Counter (PC)
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches), the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the table instruction
to fetch 8-bit wide ROM constants.
Figure 6. Programming Model
RAM
FCh
00h
FFh
03h
04h
X
Y
SP
RP
Expression
stack
Return
stack
Global
variables
07h
(256
×
4-bit)
Autosleep
Global
variables
3
0
SP
Expression Stack
Return Stack
0
11
RA
M
addres
s
regi
s
t
er:
TOS-1
TOS-2
TOS-1
TOS
4-bit
RP
12-bit
0
7
0
11
RP
PC
Program Counter
Return Stack Pointer
Expression Stack Pointer
RAM Address Register (X)
RAM Address Register (Y)
Top of Stack Register
Condition Code Register
Carry/borrow
Branch
Interrupt enable
Reserved
0
0
0
7
SP
0
7
X
0
7
Y
0
3
TOS
0
3
CCR
C
--
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I
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