1
Features
ˇ
Utilizes the AVR
Ž
RISC Architecture
ˇ
AVR High-performance and Low-power RISC Architecture
118 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General-purpose Working Registers
Up to 10 MIPS Throughput at 10 MHz
ˇ
Data and Nonvolatile Program Memory
2K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
128 Bytes Internal RAM
128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
Programming Lock for Flash Program and EEPROM Data Security
ˇ
Peripheral Features
One 8-bit Timer/Counter with Separate Prescaler
Programmable Watchdog Timer with On-chip Oscillator
SPI Serial Interface for In-System Programming
ˇ
Special Microcontroller Features
Low-power Idle and Power-down Modes
External and Internal Interrupt Sources
Power-on Reset Circuit
Selectable On-chip RC Oscillator
ˇ
Specifications
Low-power, High-speed CMOS Process Technology
Fully Static Operation
ˇ
Power Consumption at 4 MHz, 3V, 25
°C
Active: 2.4 mA
Idle Mode: 0.5 mA
Power-down Mode: <1 ľA
ˇ
I/O and Packages
Three Programmable I/O Lines for AT90S/LS2323
Five Programmable I/O Lines for AT90S/LS2343
8-pin PDIP and SOIC
ˇ
Operating Voltages
4.0 - 6.0V for AT90S2323/AT90S2343
2.7 - 6.0V for AT90LS2323/AT90LS2343
ˇ
Speed Grades
0 - 10 MHz for AT90S2323/AT90S2343-10
0 - 4 MHz for AT90LS2323/AT90LS2343-4
0 - 1 MHz for AT90LS2343-1
Pin Configuration
PDIP/SOIC
1
2
3
4
8
7
6
5
RESET
XTAL1
XTAL2
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
AT90S/LS2323
1
2
3
4
8
7
6
5
RESET
(CLOCK) PB3
PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
AT90S/LS2343
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
AT90LS2323
AT90S2343
AT90LS2343
Rev. 1004D09/01
2
AT90S/LS2323/2343
1004D09/01
Description
The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers
based on the AVR RISC architecture. By executing powerful instructions in a single
clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general-purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Block Diagram
Figure 1. The AT90S/LS2343 Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC
TIMING AND
CONTROL
INTERRUPT
UNIT
EEPROM
SPI
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PB0 - PB4
RESET
VCC
GND
CONTROL
LINES
8-BIT DATA BUS
3
AT90S/LS2323/2343
1004D09/01
Figure 2. The AT90S/LS2323 Block Diagram
The AT90S2323/2343 provides the following features: 2K bytes of In-System Program-
m a bl e F la s h , 1 2 8 b y t es E E P R O M , 12 8 b y t e s S R A M , 3 ( A T9 0 S /L S 2 3 2 3 ) / 5
(AT90S/LS2343) general-purpose I/O lines, 32 general-purpose working registers, an 8-
bit timer/counter, internal and external interrupts, programmable Watchdog Timer with
internal oscillator, an SPI serial port for Flash Memory downloading and two software-
selectable power-saving modes. The Idle mode stops the CPU while allowing the
SRAM, timer/counters, SPI port and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the oscillator, disabling all
other chip functions until the next interrupt or hardware reset.
The device is manufactured using Atmel's high-density nonvolatile memory technology.
The On-chip Flash allows the program memory to be reprogrammed in-system through
an SPI serial interface. By combining an 8-bit RISC CPU with ISP Flash on a monolithic
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PB0 - PB2
RESET
VCC
GND
CONTROL
LINES
8-BIT DATA BUS
4
AT90S/LS2323/2343
1004D09/01
chip, the Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly
flexible and cost-effective solution to many embedded control applications.
The AT90S2323/2343 AVR is supported with a full suite of program and system devel-
opment tools including: C compilers, macro assemblers, program debugger/simulators,
in-circuit emulators and evaluation kits.
Comparison between
AT90S/LS2323 and
AT90S/LS2343
The AT90S/LS2323 is intended for use with external quartz crystal or ceramic resonator
as the clock source. The start-up time is fuse-selectable as either 1 ms (suitable for
ceramic resonator) or 16 ms (suitable for crystal). The device has three I/O pins.
The AT90S/LS2343 is intended for use with either an external clock source or the inter-
nal RC oscillator as clock source. The device has five I/O pins.
Table 1 summarizes the differences in features of the two devices.
Pin Descriptions
AT90S/LS2323
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB2..PB0)
Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins
are tri-stated when a reset condition becomes active.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Table 1. Feature Difference Summary
Part
AT90S/LS2323
AT90S/LS2343
On-chip Oscillator Amplifier
yes
no
Internal RC Clock
no
yes
PB3 available as I/O pin
never
internal clock mode
PB4 available as I/O pin
never
always
Start-up time
1 ms/16 ms
16 ľs fixed
5
AT90S/LS2323/2343
1004D09/01
Pin Descriptions
AT90S/LS2343
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB4..PB0)
Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins
are tri-stated when a reset condition becomes active.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
CLOCK
Clock signal input in external clock mode.
Clock Options
Crystal Oscillator
The AT90S/LS2323 contains an inverting amplifier that can be configured for use as an
On-chip oscillator, as shown in Figure 3. XTAL1 and XTAL2 are input and output
respectively. Either a quartz crystal or a ceramic resonator may be used. It is recom-
mended that the AT90S/LS2343 be used if an external clock source is used, since this
gives an extra I/O pin.
Figure 3. Oscillator Connection
External Clock
The AT90S/LS2343 can be clocked by an external clock signal, as shown in Figure 4, or
by the On-chip RC oscillator. This RC oscillator runs at a nominal frequency of 1 MHz
(V
CC
= 5V). A fuse bit (RCEN) in the Flash memory selects the On-chip RC oscillator as
the clock source when programmed ("0"). The AT90S/LS2343 is shipped with this bit
programmed. The AT90S/LS2343 is recommended if an external clock source is used,
because this gives an extra I/O pin.
The AT90S/LS2323 can be clocked by an external clock as well, as shown in Figure 4.
No fuse bit selects the clock source for AT90S/LS2323.
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