1
Features
·
Compatible with MCS-51
®
Products
·
32K Bytes of Reprogrammable Flash Memory
·
Endurance: 1000 Write/Erase Cycles
·
4V to 5.5V Operating Range
·
Fully Static Operation: 0 Hz to 33 MHz
·
Three-level Program Memory Lock
·
512 x 8-bit Internal RAM
·
32 Programmable I/O Lines
·
Three 16-bit Timer/Counters
·
Eight Interrupt Sources
·
Programmable Serial Channel
·
Low-power Idle and Power-down Modes
·
Interrupt Recovery from Power-down Mode
·
Hardware Watchdog Timer
·
Dual Data Pointer
·
Power-off Flag
Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read only memory and 512 bytes of RAM. The
device is manufactured using Atmel's high-density nonvolatile memory technology and
is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout.
The on-chip Flash allows the program memory to be user programmed by a conven-
tional nonvolatile memory programmer. A total of 512 bytes of internal RAM are
available in the AT89C51RC. The 256-byte expanded internal RAM is accessed via
MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The other
256-byte RAM segment is accessed the same way as the Atmel AT89-series and
other 8052-compatible products. By combining a versatile 8-bit CPU with Flash on a
monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next external interrupt or hardware reset.
8-bit
Microcontroller
with 32K Bytes
Flash
AT89C51RC
Rev. 1920BMICRO11/02
2
AT89C51RC
1920BMICRO11/02
Pin Configurations
TQFP
PDIP
PLCC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(T2) P1.0
(T2EX) P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
3
AT89C51RC
1920BMICRO11/02
Block Diagram
PORT 2 DRIVERS
PORT 2
LATCH
P2.0 - P2.7
FLASH
PORT 0
LATCH
RAM
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DUAL
DPTR
RAM ADDR.
REGISTER
INSTRUCTION
REGISTER
B
REGISTER
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
STACK
POINTER
ACC
TMP2
TMP1
ALU
PSW
TIMING
AND
CONTROL
PORT 3
LATCH
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1
LATCH
PORT 1 DRIVERS
P1.0 - P1.7
OSC
GND
V
CC
PSEN
ALE/PROG
EA / V
PP
RST
PORT 0 DRIVERS
P0.0 - P0.7
WATCH
DOG
4
AT89C51RC
1920BMICRO11/02
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code
bytes during program verification. External pull-ups are required during program
verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are exter-
nally being pulled low will source current (I
IL
) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count
input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and
verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are exter-
nally being pulled low will source current (I
IL
) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits
the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are exter-
nally being pulled low will source current (I
IL
) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89C51RC, as
shown in the following table.
Port Pin
Alternate Functions
P1.0
T2 (external count input to Timer/Counter 2), clock-out
P1.1
T2EX (Timer/Counter 2 capture/reload trigger and direction control)
5
AT89C51RC
1920BMICRO11/02
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives High for 98 oscillator periods after the Watchdog times
out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In
the default state of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and
may be used for external timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the
bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT89C51RC is executing code from external program memory, PSEN is acti-
vated twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to V
CC
for internal program executions.
This pin also receives the 12-volt programming enable voltage (V
PP
) during Flash
programming.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Port Pin
Alternate Functions
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
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