1
Features
·
One of a Family of Devices with User Memories from 1 Kbit to 1 Mbit
·
4-Kbit (512-byte) EEPROM User Memory
Four 128-byte (1-Kbit) Zones
Self-timed Write Cycle (5 ms)
Single Byte or 16-byte Page Write Mode
Programmable Access Rights for Each Zone
·
2-Kbit Configuration Zone
37-byte OTP Area for User-defined Codes
160-byte Area for User-defined Keys and Passwords
·
High Security Features
64-bit Patented Dynamic Symetric Mutual Authentication Protocol (Under
Exclusive Patent License from ELVA)
Encrypted Checksum
Stream Encryption
Four Key Sets for Authentication and Encryption
Eight Sets of Two 24-bit Passwords
Anti-tearing Function
Voltage and Frequency Monitor
·
Smart Card Features
ISO 7816 Class A (5V) or Class B (3V) Operation
ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus Patent)
Multiple Zones, Key Sets and Passwords for Multi-application Use
Synchronous 2-wire Serial Interface for Faster Device Initialization
Programmable 8-byte Answer-To-Reset Register
ISO 7816-2 Compliant Modules
·
Embedded Application Features
Low Voltage Operation: 2.7V to 5.5V
Secure Nonvolatile Storage for Sensitive System or User Information
2-wire Serial Interface
1.5 MHz Compatibility for Fast Operation
Standard 8-lead Plastic Packages
Same Pinout as 2-wire Serial EEPROMs
·
High Reliability
Endurance: 100,000 Cycles
Data Retention: 10 years
ESD Protection: 4,000V min
Table 1. Pin Configuration
Pad
Description
ISO Module Contact
Standard Package Pin
VCC
Supply Voltage
C1
8
GND
Ground
C5
4
SCL/CLK
Serial Clock Input
C3
6
SDA/IO
Serial Data Input/Output
C7
5
RST
Reset Input
C2
NC
CryptoMemory
®
4 Kbit
AT88SC0404C
Summary
Rev. 2023ESSMEM07/04
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
Bottom view
Smart Card Module
VCC=C1
RST=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=SDA/IO
C8=NC
8-lead SOIC, PDIP
NC
NC
NC
GND
VCC
NC
SCL
SDA
8-lead SAP
VCC
NC
SCL
SDA
NC
NC
NC
GND
2
AT88SC0404C
2023ESSMEM07/04
Description
The AT88SC0404C member of the CryptoMemory family is a high-performance secure
memory providing 4 Kbits of user memory with advanced security and cryptographic
features built in. The user memory is divided into four 128-byte zones, each of which
may be individually set with different security access rights or combined together to pro-
vide space for 1 to 4 data files.
Smart Card Applications
The AT88SC0404C provides high security, low cost, and ease of implementation with-
out the need for a microprocessor operating system. The embedded cryptographic
engine provides for dynamic, symmetric-mutual authentication between the device and
host, as well as performing stream encryption for all data and passwords exchanged
between the device and host. Up to four unique key sets may be used for these opera-
tions. The AT88SC0404C offers the ability to communicate with virtually any smart card
reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO 7816-3.
Embedded Applications
Through dynamic, symmetric-mutual authentication, data encryption, and the use of
encrypted checksums, the AT88SC0404C provides a secure place for storage of sensi-
tive information within a system. With its tamper detection circuits, this information
remains safe even under attack. A 2-wire serial interface running at 1.5 MHz is used for
fast and efficient communications with up to 15 devices that may be individually
addressed. The AT88SC0404C is available in industry standard 8-lead packages with
the same familiar pinout as 2-wire serial EEPROMs.
Figure 1. Block Diagram
Pin Descriptions
Supply Voltage (V
CC
)
The V
CC
input is a 2.7V to 5.5V positive voltage supplied by the host.
Clock (SCL/CLK)
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device
with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an
"elementary time unit" (ETU) and is equal to 372/f.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge
clock data into the device and negative edge clock data out of the device.
Random
Generator
Authentication,
Encryption and
Certification Unit
EEPROM
Answer to Reset
Data Transfer
Password
Verification
Reset Block
Asynchronous
ISO Interface
Synchronous
Interface
Power
Management
VCC
GND
SCL/CLK
SDA/IO
RST
3
AT88SC0404C
2023ESSMEM07/04
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and
may be wired with any number of other open drain or open collector devices. An exter-
nal pull-up resistor should be connected between SDA and V
CC
. The value of this
resistor and the system capacitance loading the SDA bus will determine the rise time of
SDA. This rise time will determine the maximum frequency during read operations. Low
value pull-up resistors will allow higher frequency operations while drawing higher aver-
age power supply current.
Reset (RST)
The AT88SC0404C provides an ISO 7816-3 compliant asynchronous answer to reset
sequence. When the reset sequence is activated, the device will output the data pro-
grammed into the 64-bit answer-to-reset register. An internal pull-up on the RST input
pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC0404C does not support the synchronous answer-to-reset sequence.
Device Architecture
User Zones
The EEPROM user memory is divided into 4 zones of 1024 bits each. Multiple zones
allow for different types of data or files to be stored in different zones. Access to the user
zones is allowed only after security requirements have been met. These security
requirements are defined by the user during the personalization of the device in the con-
figuration zone. If the same security requirements are selected for multiple zones, then
these zones may effectively be accessed as one larger zone.
Control Logic
Access to the user zones occurs only through the control logic built into the device. This
logic is configurable through access registers, key registers and keys programmed into
the configuration zone during device personalization. Also implemented in the control
logic is a cryptographic engine for performing the various higher-level security functions
of the device.
Table 2. User Zones
ZONE
$0
$1
$2
$3
$4
$5
$6
$7
User 0
$000
128 bytes
$078
User 1
$000
128 bytes
$078
User 2
$000
128 bytes
$078
User 3
$000
128 bytes
$078
4
AT88SC0404C
2023ESSMEM07/04
Configuration Zone
The configuration zone consists of 2048 bits of EEPROM memory used for storing pass-
words, keys and codes and defining security levels to be used for each user zone.
Access rights to the configuration zone are defined in the control logic and may not be
altered by the user.
Security Fuses
There are three fuses on the device that must be blown during the device personaliza-
tion process. Each fuse locks certain portions of the configuration zone as OTP
memory. Fuses are designed for the module manufacturer, card manufacturer and card
issuer and should be blown in sequence, although all programming of the device and
blowing of the fuses may be performed at one final step.
Table 3. Configuration Zone
Component
Address
Answer to Reset
$00
Fab Code
Memory Test Zone
Card Manufacturers Code
Lot History Code
Device Configuration Register
$18
Identification Number
Access Registers
Password/Key Registers
Issuer Code
Authentication Attempts Counters
$50
Cryptograms
Session Encryption Keys
Secret Seeds
Password Attempts Counters
$B0
Write Passwords
Read Passwords
Reserved
5
AT88SC0404C
2023ESSMEM07/04
Protocol Selection
The AT88SC0404C supports two different communication protocols.
·
Smart Card Applications: The asynchronous T = 0 protocol defined by ISO 7816-3
is used for compatibility with the industry's standard smart card readers.
·
Embedded Applications: A 2-wire serial interface is used for fast and efficient
communication with logic or controllers.
The power-up sequence determines which of the two communication protocols will be
used.
Asynchronous
T = 0 Protocol
This power-up sequence complies with ISO 7816-3 for a cold reset in smart card
applications.
·
V
CC
goes high; RST, I/O-SDA and CLK-SCL are low.
·
Set I/O-SDA in receive mode.
·
Provide a clock signal to CLK-SCL.
·
RST goes high after 400 clock cycles.
The device will respond with a 64-bit ATR code, including historical bytes to indicate the
memory density within the CryptoMemory family. Once the asynchronous mode has
been selected, it is not possible to switch to the synchronous mode without powering off
the device.
Figure 2. Asynchronous T = 0 Protocol (Gemplus Patent)
Synchronous
2-wire Serial Interface
The synchronous mode is the default after powering up V
CC
due to the internal pull-up
on RST. For embedded applications using CryptoMemory in standard plastic packages,
this is the only communication protocol.
·
Power-up V
CC
, RST goes high also.
·
After stable V
CC
, CLK-SCL and I/O-SDA may be driven.
Figure 3. Synchronous 2-wire Protocol
Note:
Five clock pulses must be sent before the first command is issued.
Vcc
I/O-SDA
RST
CLK-SCL
ATR
Vcc
I/O-SDA
RST
CLK-SCL
1
2
3
4
5
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