5347BBIOM08/04
Features
·
Thermal Sensitive Layer Over a 0.35 µm CMOS Array
·
Image Zone: 0.4 x 11.6 mm
·
Image Array: 8 × 232 = 1856 Pixels
·
Pixel Pitch: 50 × 50 µm = 500 dpi Resolution
·
On-chip 8-bit Analog to Digital Converter
·
Serial Peripheral Interface (SPI) - 2 Modes:
Fast Mode at 16 Mbps Max for Imaging
Slow Mode at 200 kbps Max for Navigation and Control
·
Die Size: 1.5 × 15 mm
·
Operating Voltage: 2.3 to 3.6V
·
Operating Temperature Range: -40
° C to 85° C
·
Finger Sweeping Speed from 2 to 20 cm/Second
·
Low Power: 4.5 mA (Image Acquisition), 1.5 mA (Navigation), <10 µA (Sleep Mode)
·
Hard Protective Coating (>4 Million Sweeps)
·
High Protection from Electrostatic Discharge
·
Small Form Factor Packaging
Description
This document describes the specifications of Atmel's AT77C104B fingerprint sensor
dedicated to PDA, cellular and smartphone applications. Based on FingerChip ther-
mal technology, the AT77C104B is a linear sensor that captures fingerprint images by
sweeping the finger over the sensing area. This product embeds true hardware-based
8-way navigation and click functions.
Applications
·
Scrolling, Menu and Item Selection for PDAs, Cellular or Smartphone Applications
·
Cellular and Smartphones-based Security (Device Protection, Network and ISP
Access, E-commerce)
·
Personal Digital Agenda (PDA) Access
·
User Authentication for Private and Confidential Data Access
·
Portable Fingerprint Acquisition
Chip-on-board Package
Actual size of sensor
FingerChip
®
Thermal
Fingerprint
Sweep Sensor,
Hardware
Based,
Navigation and
Click Function,
SPI Interface
AT77C104B
Sweep your finger
to make life easier
2
AT77C104B
5347BBIOM08/04
Note:
The die attach is connected to pin 6 and must be grounded. The FPL pin must also be grounded.
Table 1. Pin Description for Chip-on-board Package: AT77C104B-CB08V
Pin Number
Name
Type
Description
1
Not connected
2
Not connected
3
Not connected
4
Not connected
5
GNDD
G
Digital ground supply
6
GNDA
G
Analog ground supply - connect to GNDD
7
VDDD
P
Digital power supply
8
VDDA
P
Analog power supply - connect to V
DD
9
SCK
I
Serial Port Interface (SPI) clock
10
TESTA
IO
Reserved for the analog test, not connected
11
MOSI
I
Master-out slave-in data
12
TPP
P
Temperature stabilization power
13
MISO
O
Master-in slave-out data
14
SCANEN
I
Reserved for the scan test in factory, must be grounded
15
SSS
I
Slow SPI slave select (active low
16
IRQ
O
Interrupt line to host (active low). Digital test pin
17
FSS
I
Fast SPI slave select (active low)
18
RST
I
Reset and sleep mode control (active high)
19
FPL
I
Front plane, must be grounded
3
AT77C104B
5347BBIOM08/04
Figure 1. Typical Application
The pull-up must be implemented for the master controller. The noise should be lower
than 30 mV peak to peak on VDDA.
Figure 2. Pin Description
The TESTA pin is only used for testing and debugging. The SCANEN pin is not used in
the final application and must be connected to ground.
Warning : SSS and FSS must never be low at the same time. When both SSS and FSS
equal 0, the chip switches to scan test mode. With the SPI protocol, this
configuration is not possible as only one slave at a time can be selected.
However, this configuration works when debugging the system.
TESTA
IRQ
TPP
MISO
VDDD
MOSI
SCK
GNDD
SSS
VDDA
FSS
SCANEN
GNDA
FPL
RST
VDDA
10 k
10 k
VDDD
VDDD
10µF
GND
NC
10µ
GND
VDDD
F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
NC
NC
NC
GNDD
GNDA
VDDD
VDDA
SCK
TESTA
MOSI
TPP
MISO
SCANEN
SSS
IRQ
FSS
RST
FPL
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AT77C104B
5347BBIOM08/04
Specifications
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Comments
Value
Power supply voltage
VDDD, VDDA
-0.5 to 4.6V
Note: Stresses beyond those listed
under "Absolute Maximum
Ratings" may cause permanent
damage to the device. These are
stress ratings only and functional
operation of the device at these or
any other conditions beyond those
indicated in the operational
sections of this specification is not
implied. Exposure to absolute
maximum rating conditions for
extended periods may affect device
reliability.
Front plane
FPL
GND to V
DD
+0.5V
Digital input
SSS, FSS,
SCK, MOSI
GND to V
DD
+0.5V
Temperature stabilization
power
TPP
GND to V
DD
+0.5V
Storage temperature
Tstg
-50 to +100
° C
Lead temperature
(soldering 10 seconds)
Tleads
Do not solder
Forbidden
Table 3. Recommended Conditions of Use
Parameter
Symbol
Comments
Min
Typ
Max
Unit
Positive supply voltage
V
DD
2.5 ±5%
3.3 ±10%
2.3
2.5
3.3
3.6
V
Front plane
FPL
Must be grounded
GND
V
Digital input voltage
CMOS levels
V
Digital output voltage
CMOS levels
V
Digital load
C
L
20
50
pF
Operating temperature range
T
amb
Domestic "D" grade
-40 to +85
°C
Maximum current on TPP
ITPP
Use of TPP is optional
0
-
60
mA
Table 4. Resistance
Parameter
Min Value
Standard Method
ESD
On pins HBM (Human Body Model) CMOS I/O
2 kV
MIL-STD-883 method 3015.7
On die surface (zap gun) air discharge
±16 kV
NF EN 6100-4-2
Mechanical Abrasion
Number of cycles without lubricant
Multiply by a factor of 20 for correlation with a real finger
200 000
MIL E 12397B
Chemical Resistance
Cleaning agent, acid, grease, alcohol, diluted acetone
4 hours
Internal method
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AT77C104B
5347BBIOM08/04
Power Consumption and DC Characteristics
The following characteristics are applicable to the operating temperature -40
° C Ta +85° C.
Typical conditions are: power supply = 3.3V; T
amb
= 25
° C; F
SCK
= 12 MHz (1600 slices per second); duty cycle = 50%
C
LOAD
120 pF on digital outputs unless otherwise specified.
Table 5. Explanation of Test Levels
Level
Description
I
100% production tested at +25°C
II
100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)
III Sample
tested
only
IV
Parameter is guaranteed by design and/or characterization testing
V
Parameter is a typical value only
VI
100% production tested at temperature extremes
D
100% probe tested on wafer at T
amb
= +25°C
Table 6. Specifications
Parameter
Symbol
Test Level
Min
Typ
Max
Unit
Resolution
IV
50
Micron
Size
IV
8 × 232
Pixel
Yield: number of bad pixels
I
5
Bad pixels
Equivalent resistance on TPP pin
I
23
35
47
Ohm
Table 7. Power Requirements
Name
Parameter
Conditions
Test Level
Min
Typ
Max
Unit-
V
DD
Positive supply voltage
I
2.3
2.5/3.3
3.6
V
I
DD
Current on V
DD
in acquisition mode
I
3
4.5
6
mA
I
DDNAV
Current on V
DD
in navigation mode
I
1
1.5
2
mA
I
DDCLI
Current on V
DD
in click mode
I
0.2
0.3
0.5
mA
I
DDSLP
Current on V
DD
in sleep mode
I
10
µA
I
DDSTB
Current on V
DD
in stand-by mode
I
Refer to "Power Management" on page 29
Table 8. Digital Inputs
Logic Compatibility
CMOS
Name
Parameter
Conditions
Test Level
Min
Typ
Max
Unit
I
IL
Low level input current without pull-
up device
(1)
V
I
= 0V
I
1
µA
I
IH
High level input current without
pull-down device
(1)
V
I
= V
DD
I
1
µA
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