Features

Compatible with the JPEG Baseline Standard as Defined by ISO IS 109 18-1

Highly-integrated, Low-cost Single Chip Solution

Up to 40 Mbytes/sec Sustained Compression Rate

Maximum Processing Rate of 1.6 million pixels/sec

Supports 8-bit Grayscale and YUV 4:2:2 Color Space Input and Output Formats

Handles Images of Size up to 1024 x 1024 Pixels

Fast DCT/IDCT Processor On-chip

User-defined Quantization and Huffman Tables

Support for Fast as well as Slow/Inexpensive Memories

Provides Direct Interface for Microcontroller/Microprocessor Access

Applications

The AT76C101 JPEG Processor is optimized for use in the following applications:

· Digital Cameras

· Color Printers and Plotters

· Low-cost Image Compression Systems

· Video Editing (3-4 frames/sec at CCIR 720 x 480 Image Resolution)

Hardware Resources

· On-chip Video Interface

· Custom Discrete Cosine Transform and Quantization Processor

· Variable Length and Huffman Encoder/Decoder

· Programmable Memory Interface (Supports Slow Memories)

· Microcontroller/Microprocessor Access Bus

Pin Configuration

SRDATA

15-0

SRADDR

14-0

PXWE

PXRE

PXIN

PXOUT

STOP_PIXEL

SRDRIVE

H_SYNC

V_SYNC

PX_CLK

CLK_IN

M_ADDR

19-0

M_DATA

7-0

MEM_CS

TEST

RESET

FRAMEND

FREEZE

MASTER_CS

MASTER_WR

MASTER_OE

BUSY

BST_TEST

100-Pin QFP

JPEG Image
Compression
Processor

AT76C101

Rev. 0751A04/98

AT76C101

Description

The AT76C101 is an Image Compression/Decompression
Processor that performs the JPEG Baseline Algorithm. The
system is capable of high quality compression and decom-
pression of continues-tone color or monochrome images.
The AT76C101 performs the Discrete Cosine Transform,
Quantization, and Entropy Encoding during the compres-
sion stage and carries out all inverse operations during the
decompression phase. The AT76C101 uses an external
SRAM as working memory, which is accessed by an on-
chip video interface.

The AT76C101 is designed to operate with minimum host
intervention. A host processor is required to program the
chip in the required operating mode, and to extract the
JPEG header from the compressed bit stream during the
decompression phase. Based on this information, it then
initializes the internal registers. Once the chip has been ini-
tialized, the AT76C101 operates continuously until it has
completed compression/decompression of a image frame.
The image compression ratio is controlled by the user sup-
plied quantization tables, which are loaded before the com-
pression/decompression operation. Compression ratios
from 1:1 to 50:1 are possible depending on the quality and
storage requirements of the application.

Basic System Configuration

An AT76C101-based image compression system is shown
in Figure 1. The AT76C101 requires the following external
devices:

· A microcontroller to program and initialize the chip in the

required operating mode. This device is also used to
strip the JPEG header during decompression and to
provide the AT76C101 with the header information.

· An external working memory (SRAM) for handling

uncompressed/decompressed images. The size of this
memory depends on the size of the image being
processed. The formula to assess the memory size is
given in the Pixel Interface section of this manual.

· An external memory device to store the compressed

data stream. This external memory can be either a fast
memory or a slow inexpensive memory. The size of this
memory depends on the needs of the specific
application.

Figure 1. AT76C101-based Image Compression System

OUTPUT

BUFFER

INPUT

BUFFER

RAW_OUT

SAMPLING & COLOR

CONVERSION

SRDATA

15-0

SRADDR

14-0

PXWE

PXRE

PXIN

PXOUT

STOP_PIXEL

SRDRIVE

H_SYNC

V_SYNC

PX_CLK

CLK_IN

M_ADDR

19-0

M_DATA

7-0

MEM_CS

TEST

RESET

FRAMEND

FREEZE

MASTER_CS

MASTER_WR

MASTER_OE

BUSY

32K x 16

SRAM

DATA15-0

ADDR15-0

YUV

RGB

IMAGE TO

DISPLAY

VIDEO

INTERFACE

LOGIC

Image

Source

24-BIT

RGB

COMPRESSED

DATA

MEMORY

ADDR19-0

DATA7-0

MICROCONTROLLER

AT76C101

AT76C101

System Overview

Pixel Interface

The pixel interface is used to input uncompressed data dur-
ing the compression mode, or to output decompressed
data during the decompression mode. The AT76C101
expects uncompressed image data either in YUV 4:2:2 (for
color images), or in grayscale format. During decompres-
sion, the AT76C101 generates images in the same format.

This interface requires an external buffer as working mem-
ory (Figure 2). During compression, the external buffer is
used to store the incoming pixels. After 8 scan lines are
read in, the AT76C101 performs a raster to 8x8 block con-
version of the input data. During the inverse operation, the
AT76C101 converts the outgoing pixels into the raster for-
mat and stores them in the external buffer. The uncom-
pressed data is synchronized with the PX_CLK signal. This
clock runs at twice the pixel rate so that two transfers can
occur for each pixel, one to read pixel data from the exter-
nal SRAM and one to write pixel data to the external
SRAM.

Two signals synchronize video interface operation, HSync
and VSync. These are active low, bi-directional signals and
they are controlled from the Master bit of the Mode register
of the chip. When Master is high, HSync and VSync are
generated and driven by the chip. When Master is low,
these two signals are read as inputs by the chip. In Master
mode, the registers HPeriod, HSyncWidth, VPeriod, and
VSyncWidth are used to generate HSync and VSync. HPe-
riod contains the total number of pixels per scan line, and

HSyncWidth, the width of active HSync in number of pixels.
VPeriod and VSyncWidth provide the same type of infor-
mation for VSync in terms of scan lines, rather than pixels.

These registers and others are used to control the video
interface of the chip. The other registers are HDelay, HAc-
tive, VDelay, and VActive. HDelay contains the number of
pixels between falling HSync and the first active pixel of a
line. HActive contains the number of active blocks in a line.

The size of the working memory depends on the size of the
image being processed. The external buffer should be
deep enough to store 16 scan lines of data at the highest
horizontal resolution. The equations for determining the
external buffer size are:

· Buffer bus width = 16 bits [For YUV data], 8 bits [For

Grayscale data]

· Buffer size = 16 x (No. of pixels per line)

As an example, a system designed to process images of
the maximum size of 1024 x 1024 pixels would have the
following external buffer requirements:

· Buffer size = 16 x 1024 = 16,384 words

Thus, this system would require 16K x 16 working memory
to process YUV images (color) and 16K x 8 working mem-
ory to process grayscale images. As the minimum size of
available SRAM is 32K x 8, the SRAM requirements are as
follows: YUV/grayscale images: two 32K x 8 SRAM's to
form a 32K x 16 SRAM.

Figure 2. Memory Organization

32K x 16 SRAM

DATABANK A

NOT USED

DATABANK B

NOT USED

0000h

2000h

4000h

6000h

7FFFh

SCAN LINE 1

DATABANK B

SCAN LINE 2

SCAN LINE 8

4000h

4400h

5C00h

1024 PIXELS

SCAN LINE

16 BITS

000h

001h

002h

3FEh

3FFh

8 BITS

SRAM ORGANIZATION FOR MAXIMUM SCAN LINE SIZE OF 1024 PIXELS.

EACH DATABANK STORES 8 SCAN LINES OF THE RAW IMAGE.

8 BITS

AFTER COMPRESSION

AFTER DECOMPRESSION

AT76C101

Host Interface

This is a 8-bit interface that allows the AT76C101 to trans-
fer the compressed data to an external memory device.
This interfaces also allows an external microcontrol-
ler/microprocessor (complexity of AT89C51) to access the
internal memory (registers and tables) of the AT76C101.
Two types of transfers can be carried out through this inter-
face: the compressed data transfers and the microcontrol-
ler data accesses.

Compressed Data Mode
The host interface can work with a number of external
memory devices. It has two programmable registers
through which the user can specify up to eight wait states
that allows the chip to interface with slow memory devices.
Data transfers are 8 bit wide and are carried out through
the Data Bus, Address Bus and the control signals
M E M _ C S , M A S T E R _ O E a n d M A S T E R _ W R . T h e
AT76C101 is the bus master and controls all transfers to
the external memory. Other devices cannot access the
memory while the AT76C101 is in the operating mode.

The cycle time of the compressed data transfer varies from
one to eight CLK cycles. This cycle time is controlled by
two registers, the Read_Cnt_Reg which controls the read
cycle time, and Write_Cnt_Reg which controls the write
cycle time. These registers are programmed by the micro-
controller during initialization. The address bus is also ini-
tialized from the Mem_Start_Addr register, which holds the
start address of the compressed data memory.

Microcontroller Access Mode
In this mode, the main function of the host interface is to
allow external devices, (i.e. microcontroller or a host pro-
cessor) to access the internal memory of the JPEG chip.

This is required to program the AT76C101 in the desired
mode of operation, to load the internal quantization and
Huffman tables during initialization, and to read the status
of the chip for testing purposes.

All transfers to the internal memory and tables of the JPEG
codec are 8-bit wide. Data is transferred using the Data
Bus, Address Bus, and the control signals MASTER_WR,
MASTER_OE, MASTER_CS and BUS_BUSY. All transfers
carried out in this mode are controlled by the microcontrol-
l e r .

When the AT76C101 chip is operating in normal mode (i.e.
either compression or decompression), it acts as a bus
master on the external memory/microcontroller bus. Since
the AT76C101 has higher priority over the microcontroller
for these bus accesses, the microcontroller has to check
the availability of the bus (by checking BUS_BUSY) before
it can access it. Once all the internal registers of the
AT76C101 are set up and the tables are loaded, the
AT76C101 is activated by setting the Start_Reg register.
Once the compression/decompression operation starts, the
AT76C101 takes control of the bus, and gives it up only
after the chip has processed the image.The microcontroller
can access the internal memory of the AT76C101 only
between frames and not during normal mode of operation.

Data Control

During compression, the AT76C101 monitors the internal
image buffers and sends a stall signal (STOP) to prevent
the external video interface logic from generating new pix-
els, in case the internal buffers are full. During decompres-
sion, the AT76C101 controls the transfer rate from the
compressed data interface, based on the status of the com-
pressed data FIFO (Figure 3).

Figure 3. Data Control

PIXEL

BUFFER

PIXEL

BUFFER

QUANTIZATION

TABLE

DCT/IDCT &

QUANTIZATION

MODULE

DCT COEFFICIENT

BUFFER

ZIGZAG

UNIT

HUFFMAN

ENCODER

HUFFMAN

TABLES

HUFFMAN

DECODER

BIT STUFFER

UNIT

COMP. DATA

FIFO

HOST

INTERFACE

& TEST MODULE

PIXEL

INTERFACE

SRDATA [15:0]

PX_CLK

SRADDR [14:0]

PXRE

PXWE

PXIN

PXOUT

H_SYNC

V_SYNC

BLANK

STOP_PIXEL

TEST

MASTER_CS

MASTER_OE

MASTER_WR

M_ADDR

M_DATA

MEM_CS

BUS_BUSY

HIGH LEVEL

CONTROL

RESET

END_FRAME

FREEZE

CLK_IN

AT76C101

Compressed Data Memory Management

The AT76C101 starts reading/writing data from/to the com-
pressed data memory starting from the address location
specified by the Mem_Start_Addr register. Once a frame
has been processed, the AT76C101 writes the address of
the last compressed data into the Mem_End_Addr register.
The microcontroller uses this information to keep track of
the memory locations having valid images, and to specify
the starting memory address of the next image

Initialization Sequence

The active high RESET signal resets all the AT76C101
resources including the register file. Once the AT76C101
has been reset, the microcontroller can program the chip to
the desired mode of operation. The microcontroller will also
have to load the internal Huffman and Quantization Tables.
Once the internal registers and tables have been initialized,
the microcontroller can initiate a compression/decompres-
sion operation by asserting the Start_Reg register. The
AT76C101 de-asserts this signal after the final image block
is processed. When the AT76C101 completes the process-
ing of an image, it asserts the FRAMEND signal, writes the
a d d r e s s o f t h e l a s t c o m p r e s s e d d a t a i n t o t h e
Mem_End_Addr register and waits for a new Start_Reg
request.

During decompression, the microcontroller has to do some
additional processing of the JPEG data stream. The micro-
controller extracts and process the JPEG header informa-
tion from the compressed data stream. Based on this
header information, the microcontroller then initializes the
internal registers of the AT76C101 and writes the address
of the memory location containing the first compressed
image data (not the start of the JPEG header) into the
Mem_Start_Addr register. It then follows the above men-
tioned initialization sequence.

Quantization Table Loading

The on-chip quantization tables must be loaded with the
required values before the normal operation of the chip.
The AT76C101's quantization table is a 256x16 RAM, and
can store up to four 64-word quantization tables. The upper
half of the RAM area is used to store the compression
quantization tables and the lower half to store the decom-
pression tables. The organization of the quantization RAM
is shown in Figure 4. The Quantization Tables can be
loaded only after the Quant_Table_Load_Enable register
has been set. Once loaded, the quantization tables remain
valid until the power is switched off or until they are repro-
g r a m m e d ( t h e y a r e u n a f f e c t e d b y R E S E T ) . T h e
Quant_Table_Load_Enable register has to be reset after
the tables are loaded and before normal operation of the
chip can begin.

Figure 4. Internal Memory Organization (Quantization and MaxMin Tables)

ENCODING

0000h

0002h

0080h

0100h

0180h

DECODING

QUANTIZATION TABLE

3000h

3008h

3080h

3100h

3180h

MAXMIN TABLE

DC-Y

DC-UV

AC-Y

AC-UV

MIN_CODE (BITS 7-0)

MIN_CODE (BITS 15-8)

MAX_CODE (BITS 7-0)

MAX_CODE (BITS 15-8)

VAL_PTR

NOT USED

3000h

3001h

3002h

3003h

3004h

3005h

3006h

3007h

QUANTIZATION VALUE (BITS 7-0)

QUANTIZATION VALUE (BITS 15-8)

0000h

0001h

QUANTIZATION VALUE

16 BITS

40 BITS

VAL_PTR

MAX_CODE

MIN_CODE

8 BITS

16 BITS

Part Number AT76C101