AT28C16-T
16K (2K x 8)
PCMCIA
Nonvolatile
Attribute
Memory
TSOP
Top View
Pin Name
Function
A0 - A10
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
RDY/BSY
Ready/Busy Output
NC
No Connect
Pin Configurations
Features
·
Ideal Rewriteable Attribute Memory
·
Simple Write Operation
Self-Timed Byte Writes
On-chip Address and Data Latch for SRAM-like Write Operation
Fast Write Cycle Time - 1 ms
5-Volt-Only Nonvolatile Writes
·
End of Write Detection
RDY/BUSY Output
DATA Polling
·
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: 10 Years Minimum
·
Single 5-Volt Supply for Read and Write
·
Very Low Power
30 mA Active Current
100
µ
A Standby Current
Description
The AT28C16-T is the ideal nonvolatile attribute memory: it is a low power, 5-volt-only
byte writeable nonvolatile memory (E
2
PROM). Standby current is typically less than
100
µ
. The AT28C16-T is written like a Static RAM, eliminating complex program-
ming algorithms. The fast write cycle times of 1 ms, allow quick card reconfiguration
in-system. Data retention is specified as 10 years minimum, precluding the necessity
for batteries. Three access times have been specified to allow for varying layers of
buffering between the memory and the PCMCIA interface.
The AT28C16-T is accessed like a Static RAM for read and write operations. During
a byte write, the address and data are latched internally. Following the initiation of a
write cycle, the device will go to a busy state and automatically write the latched data
using an internal control timer. The device provides two methods for detecting the end
of a write cycle; the RDY/BUSY output and DATA POLLING of I/O
7
.
0285C
AT28C16-T
2-175
Block Diagram
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +125°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
2-176
AT28C16-T
Device Operation
READ:The AT28C16-T is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location detemined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual-line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C16-T is similar
to writing into a Static RAM. A low pulse on WE or CE input
with OE high and CE or WE low (respectively) initiates a
byte write. The address is latched on the falling edge of
WE or CE (whichever occurs last) and the data is latched
on the rising edge of WE or CE (whichever occurs first).
Once a byte write is started it will automatically time itself
to completion. For the AT28C16-T the write cycle time is 1
ms maximum. Once a programming operation has been
initiated and for the duration of t
WC
, a read operation will
effectively be a polling operation.
READY/BUSY: Pin 1 is an open drain READY/BUSY out-
put that indicates the current status of the self-timed inter-
nal write cycle. READY/BUSY is actively pulled low during
the write cycle and is released at the completion of the
write. The open drain output allows OR-tying of several
devices to a common interrupt input.
DATA POLLING: The AT28C16-T also provides DATA
polling to signal the completion of a write cycle. During a
write cycle, an attempted read of the the data being written
results in the complement of that data for I/O
7
(the other
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all ouputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) V
CC
sense-- if V
CC
is below 3.8V (typical) the write function is
inhibited; (b) V
CC
power on delay-- once V
CC
h a s
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a byte write; (c) Write Inhibit--
holding any one of OE low, CE high or WE high inhibits
byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C16-T may be set to the high state by the Chip Clear
operation. By setting CE low and OE to 12V, the chip is
cleared when a 10ms low pulse is applied to WE.
DEVICE IDENTIFICATION: A n e x t r a 3 2 - b y t e s o f
E
2
PROM memory are available to the user for device
identifcation. By raising A
9
to 12V (
±
0.5V) and using ad-
dress locations 7E0H to 7FFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
AT28C16-T
2-177
AT28C16-15T
Operating
Temperature (Case)
Com.
0°C - 70°C
Ind.
-40°C - 85°C
V
CC
Power Supply
5V
±
10%
DC and AC Operating Range
Mode
CE
OE
WE
I/O
Read
V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
High Z
Write Inhibit
X
X
V
IH
Write Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Chip Erase
V
IL
V
H
(3)
V
IL
High
Z
3. V
H
= 12.0V
±
0.5V.
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
Operating Modes
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
+ 1V
10
µ
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
µ
A
I
SB1
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
+ 1.0V
100
µ
A
I
SB2
V
CC
Standby Current TTL
CE = 2.0V to V
CC
+ 1.0V
Com.
2
mA
Ind.
3
mA
I
CC
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA
Com.
30
mA
Ind.
45
mA
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
.4
V
V
OH
Output High Voltage
I
OH
= -400
µ
A
2.4
V
DC Characteristics
2-178
AT28C16-T
PCMCIA
Symbol
Atmel
Symbol
Parameter
AT28C16-15T
Min
Max
Units
t
C
(R)
t
RC
Read Cycle Time
150
ns
t
A
(A)
t
ACC
Address Access Time
150
ns
t
A
(CE)
t
CE
(1)
CE Access Time
150
ns
t
A
(OE)
t
OE
(2)
OE Access Time
0
75
ns
t
EN
(CE)
t
Lz
(4)
Output Enable Time From CE
0
ns
t
EN
(OE)
t
OLZ
(4)
Output Enable Time From OE
0
ns
t
V
(A)
t
OH
Output Hold Time
0
ns
t
DIS
(CE)
t
DF
(3, 4)
Output Disable Time From CE
0
50
ns
t
DIS
(OE)
t
DF
(3, 4)
Output Disable Time From OE
0
50
ns
AC Read Characteristics
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
t
R
, t
F
< 5 ns
Input Test Waveforms and
Measurement Level
Output Test Load
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Pin Capacitance (f = 1 MHz, T = 25°C)
(1)
Note:
1. This parameter is characterized and is not 100% tested.
AT28C16-T
2-179
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