1
1661BSEEPR04/04
Features
·
Low-voltage and Standard-voltage Operation, V
CC
= 2.7V to 5.5V
·
Internally Organized 16,384 x 8 and 32,768 x 8
·
2-wire Serial Interface
·
Schmitt Trigger, Filtered Inputs for Noise Suppression
·
Bi-directional Data Transfer Protocol
·
1 MHz (5V) and 400 kHz (2.7V) Compatibility
·
64-byte Page Write Mode (Partial Page Writes Allowed)
·
Self-timed Write Cycle (5 ms Typical)
·
High Reliability
Endurance: 1 Million Write Cycles
Data Retention: 40 Years
ESD Protection: > 4000V
Description
The AT24C128SC/256SC provides 131,072/262,144 bits of serial electrically erasable
and programmable read only memory (EEPROM) organized as 16,384/32,768 words
of 8 bits each. The devices are optimized for use in smart card applications where low-
power and low-voltage operation may be essential. The devices are available in sev-
eral standard ISO 7816 smart card modules (see Ordering Information). All devices
are functionally equivalent to Atmel Serial EEPROM products offered in standard IC
packages (PDIP, SOIC, TSSOP, dBGA), with the exception of the slave address and
Write Protect functions which are not required for smart card applications.
Table 1. Pin Configurations
Figure 1. Card Module Contact
Pad Name
Description
ISO Module Contact
VCC
Power Supply Voltage
C1
GND
Ground
C5
SCL
Serial Clock Input
C3
SDA
Serial Data Input/Output
C7
NC
No Connect
C2, C4, C6, C8
VCC
NC
Two-wire Serial
EEPROM Smart
Card Modules
128K (16,384 x 8)
256 (32,768 x 8)
AT24C128SC
AT24C256SC
2
AT24C128SC/AT24C256SC
1661BSEEPR04/04
Figure 2. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
Memory Organization
AT24C128SC/256SC, 128K/256K SERIAL EEPROM: The 128K/256K is internally
organized as 256/512 pages of 64-bytes each. Random word addressing requires a
14/15-bit data word address.
Absolute Maximum Ratings*
Operating Temperature
......................................-
55
°
C to +125
°
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only;
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature
.........................................-
65
°
C to +150
°
C
Voltage on Any Pin
with Respect to Ground
........................................ -
1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C128SC/AT24C256SC
1661BSEEPR04/04
Pin Capacitance
Note:
This parameter is characterized and is not 100% tested.
DC Characteristics
Note:
1. Applicable over recommended operating range from: T
AC
= 0
°
C to +70
°
C, V
CC
= +2.7V to +5.5V (unless otherwise noted).
2. V
IL
min and V
IH
max are reference only and are not tested.
Table 2. Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
°
C, f = 1.0 MHz, V
CC
= +2.7V.
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (SCL)
6
pF
V
IN
= 0V
Table 3. DC Characteristics
(1)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC
Supply Voltage
2.7
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V
Read at 400 kHz
1.0
2.0
mA
I
CC2
Supply Current
V
CC
= 5.0V
Write at 400 kHz
2.0
3.0
mA
I
SB
Standby Current)
V
CC
= 2.7V
V
IN
= V
CC
or GND
2.0
µA
V
CC
= 5.5V
6.0
I
LI
Input Leakage Current
V
IN
= V
CC
or
GND
0.10
3.0
µA
I
LO
Output Leakage
Current
V
OUT
= V
CC
or
GND
0.05
3.0
µA
V
IL
Input Low Level
(2)
-
0.6
V
CC
x 0.3
V
V
IH
Input High Level
(2)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL
Output Low Level
V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
4
AT24C128SC/AT24C256SC
1661BSEEPR04/04
AC Characteristics
Notes:
1. Applicable over recommended operating range from T
A
= 0
°
C to +70
°
C, V
CC
= +2.7V to +5.5V, CL = 100 pF (unless other-
wise noted). Test conditions are listed in Note 3.
2. This parameter is characterized and is not 100% tested.
3. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 k
(2.7V, 5V),
Input pulse voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
50ns
Input and output timing reference voltages: 0.5V
CC
Table 4. AC Characteristics
(1)
Symbol
Parameter
2.7-volt
5.0-volt
Units
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
400
1000
kHz
t
LOW
Clock Pulse Width Low
1.3
0.4
µs
t
HIGH
Clock Pulse Width High
0.6
0.4
µs
t
AA
Clock Low to Data Out Valid
0.05
0.9
0.05
0.55
µs
t
BUF
Time the bus must be free before a new
transmission can start
(2)
1.3
0.5
µs
t
HD.STA
Start Hold Time
0.6
0.25
µs
t
SU.STA
Start Set-up Time
0.6
0.25
µs
t
HD.DAT
Data In Hold Time
0
0
µs
t
SU.DAT
Data In Set-up Time
100
100
ns
t
R
Inputs Rise Time
(2)
0.3
0.3
µ
s
t
F
Inputs Fall Time
(2)
300
100
ns
t
SU.STO
Stop Set-up Time
0.6
0.25
µs
t
DH
Data Out Hold Time
50
50
ns
t
WR
Write Cycle Time
5
5
ms
Endurance
(2)
25°C, Page Mode
1M
1M
Write Cycles
5
AT24C128SC/AT24C256SC
1661BSEEPR04/04
Device Operation
CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C128SC/256SC features a low power standby mode
which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1.
Clock up to 9 cycles.
2.
Look for SDA high in each cycle while SCL is high.
3.
Create a start condition as SDA is high.
PDF 
ZIP