ARM DDI 0274B

VFP11 Vector Floating-point Coprocessor

Technical Reference Manual

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Change history

Date

Issue

Change

19 December, 2002

First release

10 February, 2003

First release for VFP11 r0p1 coprocessor

ARM DDI 0274B

iii

Contents
VFP11 Vector Floating-point Coprocessor
Technical Reference Manual

Preface

About this document ...................................................................................... x
Feedback ..................................................................................................... xiii

Chapter 1

Introduction

1.1

About the VFP11 coprocessor ................................................................... 1-2

1.2

Applications ................................................................................................. 1-3

1.3

Coprocessor interface ................................................................................. 1-4

1.4

VFP11 coprocessor pipelines ..................................................................... 1-5

1.5

Modes of operation ................................................................................... 1-13

1.6

Short vector instructions ........................................................................... 1-16

1.7

Parallel execution of instructions ............................................................... 1-17

1.8

VFP11 treatment of branch instructions .................................................... 1-18

1.9

Writing optimal VFP11 code ...................................................................... 1-19

1.10

Silicon revision information ....................................................................... 1-20

Chapter 2

Register File

2.1

About the register file .................................................................................. 2-2

2.2

2.3

Decoding the register file ............................................................................ 2-5

Contents

ARM DDI 0274B

2.4

Loading operands from ARM11 registers ................................................... 2-6

2.5

Maintaining consistency in register precision ............................................. 2-8

2.6

Data transfer between memory and VFP11 registers ................................ 2-9

2.7

Access to register banks in CDP operations ............................................ 2-11

Chapter 3

Programmer's Model

3.1

About the programmer's model .................................................................. 3-2

3.2

Compliance with the IEEE 754 standard .................................................... 3-3

3.3

ARMv5TE coprocessor extensions .......................................................... 3-10

3.4

VFP11 system registers ........................................................................... 3-19

Chapter 4

Instruction Execution

4.1

About instruction execution ........................................................................ 4-2

4.2

Serializing instructions ................................................................................ 4-3

4.3

Interrupting the VFP11 coprocessor ........................................................... 4-4

4.4

Forwarding .................................................................................................. 4-5

4.5

Hazards ...................................................................................................... 4-7

4.6

Operation of the scoreboard ....................................................................... 4-8

4.7

Parallel execution ..................................................................................... 4-17

4.8

Execution timing ....................................................................................... 4-19

Chapter 5

Exception Handling

5.1

About exception processing ....................................................................... 5-2

5.2

Bounced instructions .................................................................................. 5-3

5.3

Support code .............................................................................................. 5-5

5.4

Exception processing ................................................................................. 5-8

5.5

Input Subnormal exception ....................................................................... 5-13

5.6

Invalid Operation exception ...................................................................... 5-14

5.7

Division by Zero exception ....................................................................... 5-17

5.8

Overflow exception ................................................................................... 5-18

5.9

Underflow exception ................................................................................. 5-20

5.10

Inexact exception ...................................................................................... 5-22

5.11

Input exceptions ....................................................................................... 5-23

5.12

Arithmetic exceptions ............................................................................... 5-24

Glossary

ARM DDI 0274B

List of Tables
VFP11 Vector Floating-point Coprocessor
Technical Reference Manual

Change history .............................................................................................................. ii

Table 2-1

VFP11 MCR instructions ........................................................................................... 2-6

Table 2-2

VFP11 MRC instructions ........................................................................................... 2-6

Table 2-3

VFP11 MCRR instructions ........................................................................................ 2-7

Table 2-4

VFP11 MRRC instructions ........................................................................................ 2-7

Table 2-5

Single-precision data memory images and byte addresses ...................................... 2-9

Table 2-6

Double-precision data memory images and byte addresses .................................. 2-10

Table 2-7

Single-precision three-operand register usage ....................................................... 2-15

Table 2-8

Single-precision two-operand register usage .......................................................... 2-15

Table 2-9

Double-precision three-operand register usage ...................................................... 2-15

Table 2-10

Double-precision two-operand register usage ........................................................ 2-16

Table 3-1

Default NaN values ................................................................................................... 3-5

Table 3-2

QNaN and SNaN handling ........................................................................................ 3-6

Table 3-3

VFP11 register summary ........................................................................................ 3-19

Table 3-4

Access to VFP11 system registers ......................................................................... 3-20

Table 3-5

FPSID bit fields ....................................................................................................... 3-21

Table 3-6

Encoding of the Floating-Point Status and Control Register ................................... 3-22

Table 3-7

Vector length and stride combinations .................................................................... 3-24

Table 3-8

Encoding of the Floating-Point Exception Register ................................................. 3-26

Table 4-1

Pipeline stages for Example 4-4 ............................................................................... 4-9

Table 4-2

Pipeline stages for Example 4-5 ............................................................................. 4-10

Part Number VFP11

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