ARM DDI 0178B

VFP10TM Vector Floating-point Coprocessor

Technical Reference Manual

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Change history

Date

Issue

Change

22 May, 2001

First release

24 May, 2001

Second release, addition of FPINST and FPINST2 <reg> field addresses

ARM DDI 0178B

iii

Contents
VFP10 Vector Floating-point Coprocessor
Technical Reference Manual

Preface

About this document ...................................................................................... x
Further reading ............................................................................................. xii
Feedback ..................................................................................................... xiii

Chapter 1

Introduction

1.1

About the VFP10 coprocessor .................................................................... 1-2

1.2

Coprocessor interface ................................................................................. 1-4

1.3

The VFP10 coprocessor pipeline ................................................................ 1-5

1.4

Modes of operation ................................................................................... 1-12

1.5

Short vector instructions ........................................................................... 1-15

1.6

Parallel execution of instructions ............................................................... 1-16

1.7

VFP10 coprocessor treatment of branch instructions ............................... 1-17

1.8

Writing optimal VFP10 coprocessor code ................................................. 1-18

1.9

Clocking .................................................................................................... 1-19

1.10

Testing ...................................................................................................... 1-20

1.11

Modifications from VFP10 coprocessor (Rev 0) ........................................ 1-21

Chapter 2

VFP10 Register File

2.1

About the register file .................................................................................. 2-2

Contents

ARM DDI 0178B

2.2

2.3

Decoding the register file ............................................................................ 2-5

2.4

Loading operands from ARM registers ....................................................... 2-7

2.5

Maintaining consistency in register precisions ........................................... 2-9

2.6

Data transfer between memory and VFP10 coprocessor registers .......... 2-10

2.7

Access to register banks in CDP operations ............................................ 2-12

Chapter 3

VFP10 Programmer's Model

3.1

About the programmer's model .................................................................. 3-2

3.2

Compliance with IEEE-754 ......................................................................... 3-4

3.3

ARM v5TE coprocessor extensions ......................................................... 3-11

3.4

Summary of VFP coprocessor system control registers ........................... 3-17

3.5

FPSCR register ........................................................................................ 3-23

Chapter 4

Instruction Execution in the VFP10 Coprocessor

4.1

About instruction execution in the VFP10 coprocessor .............................. 4-2

4.2

Serializing instructions ................................................................................ 4-4

4.3

Interrupting VFP10 coprocessor instructions .............................................. 4-5

4.4

Forwarding .................................................................................................. 4-6

4.5

Hazard and resource stall conditions ....................................................... 4-11

4.6

Parallel execution of operations ............................................................... 4-21

4.7

Execution timing ....................................................................................... 4-23

Chapter 5

Exception Handling

5.1

About exception processing ....................................................................... 5-2

5.2

Support code .............................................................................................. 5-3

5.3

Illegal instructions ....................................................................................... 5-6

5.4

Determination of the trigger instruction ....................................................... 5-7

5.5

Input subnormal ........................................................................................ 5-12

5.6

Invalid operation ....................................................................................... 5-13

5.7

Division by zero ........................................................................................ 5-16

5.8

Overflow ................................................................................................... 5-17

5.9

Underflow ................................................................................................. 5-19

5.10

Inexact result ............................................................................................ 5-21

5.11

Input exceptions ....................................................................................... 5-22

5.12

Arithmetic exceptions ............................................................................... 5-23

Chapter 6

Design for Test

6.1

About DFT .................................................................................................. 6-2

6.2

VFP10 DFT ................................................................................................. 6-3

6.3

VFP10 Core ................................................................................................ 6-4

6.4

VFP10 test wrapper .................................................................................... 6-6

6.5

VFP10 clocking ......................................................................................... 6-10

6.6

Test Pins ................................................................................................... 6-11

Glossary

ARM DDI 0178B

List of Tables
VFP10 Vector Floating-point Coprocessor
Technical Reference Manual

Change history .............................................................................................................. ii

Table 2-1

MCR transfers ........................................................................................................... 2-7

Table 2-2

MRC transfers ........................................................................................................... 2-7

Table 2-3

MCRR transfers ........................................................................................................ 2-8

Table 2-4

MRRC transfers ........................................................................................................ 2-8

Table 2-5

Single-precision data memory images and byte addresses .................................... 2-10

Table 2-6

Double-precision data memory images and byte addresses .................................. 2-11

Table 2-7

Table 2-8

Single-precision three-operand register usage ....................................................... 2-15

Table 2-9

Single-precision two-operand register usage .......................................................... 2-16

Table 2-10

Double-precision three-operand register usage ...................................................... 2-16

Table 2-11

Double-precision two-operand register usage ........................................................ 2-16

Table 3-1

Default NaN values ................................................................................................... 3-6

Table 3-2

Access to control registers ...................................................................................... 3-17

Table 3-3

FPEXC bit field descriptions .................................................................................... 3-19

Table 3-4

Vector iteration count bit values .............................................................................. 3-20

Table 3-5

FPSID bit fields ....................................................................................................... 3-21

Table 3-6

Vector length/stride combinations ........................................................................... 3-25

Table 3-7

Exception status and control bits ............................................................................ 3-26

Table 4-1

Single-precision source register locking and clearing in non-RunFast mode .......... 4-12

Table 4-2

Double-precision source register locking and clearing in non-RunFast mode ........ 4-12

Part Number VFP10

Document Outline