Document Outline

• Contents
• List of Tables
• List of Figures
• Preface
  • About this document
    • Intended audience
    • Using this manual
    • Typographical conventions
    • Timing diagram conventions
    • Further reading
  • Feedback
    • Feedback on the ARM9E-S core (Rev 2)
    • Feedback on the ARM9ES (Rev 2) Technical Reference Manual
• Introduction
  • 1.1 About the ARM9ES core
    • 1.1.1 The instruction pipelines
    • 1.1.2 Memory access
    • 1.1.3 Forwarding, interlocking, and data dependencies
  • 1.2 ARM9ES architecture
    • 1.2.1 Instruction compression
    • 1.2.2 The Thumb instruction set
  • 1.3 ARM9E-S block, core, and interface diagrams
  • 1.4 ARM9E-S instruction set summary
    • 1.4.1 Extended ARM instruction set summary
    • 1.4.2 Thumb instruction set summary
  • 1.5 ARM9E-S Rev 1 and Rev 2 changes
• Programmers Model
  • 2.1 About the programmers model
  • 2.2 Processor operating states
    • 2.2.1 Switching state
    • 2.2.2 Interworking ARM and Thumb state
  • 2.3 Memory formats
    • 2.3.1 Big-endian format
    • 2.3.2 Little-endian format
  • 2.4 Instruction length
  • 2.5 Data types
  • 2.6 Operating modes
  • 2.7 Registers
    • 2.7.1 The ARM state register set
    • 2.7.2 The Thumb state register set
    • 2.7.3 ARM state and Thumb state registers relationship
    • 2.7.4 Accessing high registers in Thumb state
  • 2.8 The program status registers
    • 2.8.1 The condition code flags
    • 2.8.2 The Q flag
    • 2.8.3 The control bits
    • 2.8.4 Reserved bits
  • 2.9 Exceptions
    • 2.9.1 Exception entry and exit summary
    • 2.9.2 Entering an ARM exception
    • 2.9.3 Leaving an ARM exception
    • 2.9.4 Reset
    • 2.9.5 Fast interrupt request
    • 2.9.6 Interrupt request
    • 2.9.7 Aborts
    • 2.9.8 Software interrupt instruction
    • 2.9.9 Undefined instruction
    • 2.9.10 Breakpoint instruction (BKPT)
    • 2.9.11 Exception vectors
    • 2.9.12 Exception priorities
• Memory Interface
  • 3.1 About the memory interface
  • 3.2 Instruction interface
    • 3.2.1 Instruction interface signals
  • 3.3 Instruction interface addressing signals
    • 3.3.1 IA[31:1]
    • 3.3.2 ITBIT
    • 3.3.3 InTRANS
    • 3.3.4 InM[4:0]
  • 3.4 Instruction interface data timed signals
    • 3.4.1 INSTR[31:0]
    • 3.4.2 IABORT
  • 3.5 Endian effects for instruction fetches
  • 3.6 Instruction interface cycle types
    • 3.6.1 Instruction interface, nonsequential cycles
    • 3.6.2 Instruction interface, sequential cycles
    • 3.6.3 Instruction interface, internal cycles
    • 3.6.4 Canceled memory cycles
  • 3.7 Data interface
    • 3.7.1 Data interface signals
  • 3.8 Data interface addressing signals
    • 3.8.1 DA[31:0]
    • 3.8.2 DLOCK
    • 3.8.3 DMAS[1:0]
    • 3.8.4 DnM[4:0]
    • 3.8.5 DnRW
    • 3.8.6 DnSPEC
    • 3.8.7 DnTRANS
  • 3.9 Data interface data timed signals
    • 3.9.1 DABORT
    • 3.9.2 RDATA[31:0]
    • 3.9.3 WDATA[31:0]
    • 3.9.4 Byte and halfword accesses
  • 3.10 Data interface cycle types
    • 3.10.1 Data interface, nonsequential cycles
    • 3.10.2 Data interface, sequential cycles
    • 3.10.3 DBURST[3:0]
    • 3.10.4 Data interface, internal cycles
    • 3.10.5 Data interface, coprocessor register transfer cycles
    • 3.10.6 Canceled memory accesses
  • 3.11 Endian effects for data transfers
    • 3.11.1 Writes
    • 3.11.2 Reads
  • 3.12 Use of CLKEN to control bus cycles
    • 3.12.1 Withdrawal of memory requests in waited cycles
• Interrupts
  • 4.1 About interrupts
  • 4.2 Hardware interface
    • 4.2.1 Generating an interrupt
    • 4.2.2 Synchronization
    • 4.2.3 Re-enabling interrupts after an interrupt exception
    • 4.2.4 Interrupt registers
  • 4.3 Maximum interrupt latency
  • 4.4 Minimum interrupt latency
• Coprocessor Interface
  • 5.1 About the coprocessor interface
    • 5.1.1 Coprocessor pipeline operates in step with the ARM9E-S core
    • 5.1.2 Coprocessor pipeline one cycle behind the ARM9E-S core
  • 5.2 LDC/STC
    • 5.2.1 Coprocessor handshake encoding
  • 5.3 MCR/MRC
  • 5.4 MCRR/MRRC
  • 5.5 Interlocked MCR
  • 5.6 Interlocked MCRR
  • 5.7 CDP
  • 5.8 Privileged instructions
  • 5.9 Busy-waiting and interrupts
  • 5.10 Coprocessor 15 MCRs
  • 5.11 Connecting coprocessors
    • 5.11.1 Connecting a single coprocessor
    • 5.11.2 Connecting multiple coprocessors
    • 5.11.3 No external coprocessor
    • 5.11.4 Undefined instructions
• Device Reset
  • 6.1 About device reset
  • 6.2 Reset modes
    • 6.2.1 Full system reset
    • 6.2.2 Core reset
    • 6.2.3 EmbeddedICE-RT reset
    • 6.2.4 Normal operation
  • 6.3 ARM9E-S core behavior on exit from reset
• Instruction Cycle Times
  • 7.1 Instruction cycle count summary
  • 7.2 Introduction to detailed instruction cycle timings
  • 7.3 Branch and ARM branch with link
  • 7.4 Thumb branch with link
  • 7.5 Branch and exchange
  • 7.6 Thumb Branch, Link, and Exchange
  • 7.7 Data operations
  • 7.8 MRS operations
  • 7.9 MSR operations
  • 7.10 Multiply and multiply accumulate
    • 7.10.1 Interlocks
  • 7.11 QADD, QDADD, QSUB, and QDSUB
    • 7.11.1 Interlocks
  • 7.12 Load register
    • 7.12.1 Interlocks
  • 7.13 Store register
  • 7.14 Load multiple registers
    • 7.14.1 Interlocks
  • 7.15 Store multiple registers
  • 7.16 Load double register
  • 7.17 Store double register
  • 7.18 Data swap
    • 7.18.1 Interlocks
  • 7.19 PLD
  • 7.20 Software interrupt, undefined instruction, and exception entry
  • 7.21 Coprocessor data processing operation
  • 7.22 Load coprocessor register, from memory
  • 7.23 Store coprocessor register, to memory
  • 7.24 Coprocessor register transfer, to ARM
  • 7.25 Coprocessor register transfer, from ARM register
  • 7.26 Double coprocessor register transfer, to ARM register
  • 7.27 Double coprocessor register transfer, from ARM register
  • 7.28 Coprocessor absent
  • 7.29 Unexecuted instructions
• Debug Interface and EmbeddedICE-RT
  • 8.1 About the debug interface
    • 8.1.1 Halt mode
    • 8.1.2 Monitor mode
  • 8.2 Debug systems
    • 8.2.1 The debug host
    • 8.2.2 The protocol converter
    • 8.2.3 The ARM9ES core
  • 8.3 About EmbeddedICE-RT
  • 8.4 Disabling EmbeddedICE-RT
  • 8.5 Debug interface signals
    • 8.5.1 Entry into debug state on breakpoint
    • 8.5.2 Breakpoints and exceptions
    • 8.5.3 Watchpoints
    • 8.5.4 Watchpoints and exceptions
    • 8.5.5 Debug request
    • 8.5.6 Actions of the ARM9ES core in debug state
  • 8.6 ARM9ES core clock domains
    • 8.6.1 Clocks and synchronization
  • 8.7 Determining the core and system state
  • 8.8 The debug communications channel
    • 8.8.1 Debug comms channel registers
    • 8.8.2 Debug comms channel control register
    • 8.8.3 Comms channel monitor mode debug status register
    • 8.8.4 Communications using the comms channel
    • 8.8.5 Comms channel reset
  • 8.9 Monitor mode debug
  • 8.10 Using watchpoints and breakpoints
    • 8.10.1 Watchpoints
    • 8.10.2 Breakpoints
    • 8.10.3 Monitor mode
• AC Parameters
  • 9.1 Timing diagrams
  • 9.2 AC timing parameter definitions
• Signal Descriptions
  • A.1 Clock interface signals
  • A.2 Instruction memory interface signals
  • A.3 Data memory interface signals
  • A.4 Miscellaneous signals
  • A.5 Coprocessor interface signals
  • A.6 Debug signals
• Debug in depth
  • B.1 Scan chains and JTAG interface
    • B.1.1 Debug scan chains
    • B.1.2 TAP state machine
  • B.2 Resetting the TAP controller
  • B.3 Instruction register
  • B.4 Public instructions
    • B.4.1 EXTEST (b0000)
    • B.4.2 SAMPLE/PRELOAD (b0011)
    • B.4.3 SCAN_N (b0010)
    • B.4.4 INTEST (b1100)
    • B.4.5 IDCODE (b1110)
    • B.4.6 BYPASS (b1111)
    • B.4.7 RESTART (b0100)
  • B.5 Test data registers
    • B.5.1 Bypass register
    • B.5.2 ARM9E-S core device identification (ID) code register
    • B.5.3 Instruction register
    • B.5.4 Scan path select register
    • B.5.5 Scan chains 1 and 2
  • B.6 ARM9E-S core clock domains
  • B.7 Determining the core and system state
    • B.7.1 Determining the core state
    • B.7.2 Determining the system state
    • B.7.3 Exit from debug state
  • B.8 Behavior of the program counter during debug
    • B.8.1 ARM and Thumb state breakpoints
    • B.8.2 ARM and Thumb state watchpoints
    • B.8.3 Watchpoint with another exception
    • B.8.4 Watchpoint and breakpoint
    • B.8.5 Debug request
    • B.8.6 System speed access
    • B.8.7 Summary of return address calculations
  • B.9 Priorities and exceptions
    • B.9.1 Breakpoint with Prefetch Abort
    • B.9.2 Interrupts
    • B.9.3 Data Aborts
  • B.10 EmbeddedICE-RT logic
    • B.10.1 Register map
    • B.10.2 Programming and reading EmbeddedICE-RT logic registers
    • B.10.3 Using the mask registers
    • B.10.4 Watchpoint control registers
    • B.10.5 Debug control register
    • B.10.6 Debug status register
    • B.10.7 Vector catch register
  • B.11 Vector catching
  • B.12 Coupling breakpoints and watchpoints
    • B.12.1 Breakpoint and watchpoint coupling example
    • B.12.2 DBGRNG signal
  • B.13 Disabling EmbeddedICE-RT
  • B.14 EmbeddedICE-RT timing
  • Index
    • A
    • B
    • C
    • D
    • E
    • F
    • H
    • I
    • J
    • L
    • M
    • N
    • O
    • P
    • Q
    • R
    • S
    • T
    • U
    • V
    • W
    • Z