Product Overview

ARM926EJ-S

System-on-Chip

JavaTM and DSP enhanced processor

Target Applications

Java enabled Mobile, Smart
phones and PDAs

Applications requiring a
platform OS:
- EPOC, Linux, PalmOS, and
WindowsCE

Wireless internet applications

Networking applications

Digital set top boxes

Automotive:
- Hands-free interfaces
- Infotainment

MPEG4 Video encoding and
decoding

Audio decoding:
- Dolby AC3 digital
- High-end MP3 players
-AAC

Speech codes

Benefits

Integrated single chip
microcontroller, DSP, and
Java solution

Very efficient Java byte
code execution

Reduced power
consumption and chip
complexity over a Java
coprocessor solution

Flexibility with tightly coupled
memory system and variable
size caches

Rapid ASIC or ASSP
integration with a short time-
to-market

Interface to ETM9 for real
time trace support

The ARM926EJ-STM

The ARM926EJ-S macrocell is a fully synthesizable 32-bit RISC processor
comprising an ARM9EJ-STM Java enhanced processor core, instruction and
data caches, Tightly-coupled Memory (TCM) interfaces, Memory
Management Unit (MMU), and separate instruction and data AMBATM
(Advanced Microprocessor Bus Architecture) Advanced High-performance
Bus (AHB) Bus Interfaces. The sizes of both caches and TCM memories can
all be specified independently. The TCM interface is flexible providing the
capability to attach nonzero wait state memory and to support DMA accesses,
while retaining support for single cycle memory accesses using zero-wait
state RAM using the same interface. This flexibility allows the Macrocell to be
tailored to the specific application needs.The MMU supports virtual memory
based platform operating systems such as EPOC, Linux, WindowsCE, and
PalmOS. New power management features allow:

system-level RAM power down

architectural clock stopping

logic-level clock gating.

The ARM926EJ-S provides a complete high-performance single processor
solution, offering considerable savings in chip complexity and area, system
design, power consumption, and time-to-market. It provides higher
performance, lower system cost and lower power consumption than
coprocessors and dual-processor solutions.

Java enhancements (JazelleTM)

The ARM926EJ-S processor has ARM's embedded Jazelle Java acceleration
hardware, within the ARM9EJ-S core. In the rapidly developing market for
internet-enabled applications, Java offers advantages of rapid application
development to software engineers, and the ARM926EJ-S is an ideal
mechanism for implementing those applications.

The ARM9EJ-S processor core executes an extended ARMv5TE instruction
set, which includes support for Java byte code execution (ARMv5TEJ). An
ARM optimized Java Virtual Machine (JVM) software layer has been written to
work with the Jazelle hardware. The Java byte code acceleration is achieved
by the hardware directly executing 80% of simple Java byte codes directly and
the remaining 20% of less frequently byte codes by software emulation within
the ARM optimized JVM.

ARM926EJ-S

DSP enhancements

The ARM926EJ-S processor core
offers the full advantage of the
enhanced DSP capability of the
ARM9EJ-S processor core. Multiply
instructions are processed using a
single-cycle 32x16 implementation.
There are 32x32, 32x16, and 16x16

multiply instructions or Multiply
Accumulate (MAC), and the pipeline
allows one multiply to start each
cycle. Saturating arithmetic improves
efficiency by automatically selecting
saturating behavior during execution
and is used to set limits on signal
processing calculations to minimize
the effect of noise or signal errors. All

of these instructions are beneficial for
algorithms that implement:

GSM protocols

FFT

state space servo control.

AHB interface and

write buffer

Instruction

cache

DTCM

interface

Instruction

TLB

ITCM

interface

Data TLB

Data cache

Trace port

interface

External

coprocessor

interface

CP15 system

configuration

coprocessor

read

data

write data

instr.

fetches

instr

address

data

address

MMU

Instruction tightly

coupled memory

Data tightly

coupled memory

AMBA AHB

External

coprocessors

ETM9

data address

instr address

ARM9EJ-S

processor

core

ARM926EJ-S

Memory Management Unit

The MMU supports a demand page
virtual memory system required by
platform operating systems such as
Linux, EPOC, or WindowsCE. The
MMU provides the access protection
mechanism for all memory accesses.
The address translation, protection
and region type information is stored
in a series of page tables in main
memory. The MMU contains
hardware for automatically reading
and processing these tables, and
storing the resultant translation and
protection information in a translation
lookaside buffer (TLB).

Page sizes of 1MB, 64KB, 4KB &
1KB

Hardware page table walks

Separate TLB for instruction and
data

Domains allow protection
attributes to be changed without
TLB flushes

Fast context switch enables
virtual address remapping in
a 0-32MB region

TLB entries for critical code and
data can be locked down

TLB entries can be removed from
the TLB selectivity

Access permissions for large
pages and small pages can be
specified separately for each
quarter of the page (these
quarters are called subpages).

Caches

The ARM926EJ-S uses separate
caches for instructions and data,
allowing both an instruction fetch, and
a load/store access to take place
simultaneously. The cache is
constructed using standard compiled
SRAM blocks, allowing a wide range

of processes and libraries to be
targeted The size of the each cache
can be selected from the following
range:

4KB

8KB

16KB

32KB

64KB

128KB

The caches are virtually addressed,
with each cache line containing eight
words. Cache lines are allocated on a
read-miss basis. Victim replacement
can be configured to be either round-
robin or pseudo random.
A cacheable memory region can be
defined as either being writeback
(copy-back) or write-through. This is
controlled by the memory region
attributes contained in the page table
entry for the region.

TCM interfaces

The ARM926EJ-S provides a
separate TCM interface for
instructions and data. The interface is
designed to allow single cycle access
for data and instructions. The
interface allows TCM accesses to be
extended by virtue of a wait signal.
Extending memory accesses allows
nonzero wait state memory to be
used, and for DMA type access to
occur. To optimize use of memories
which have a different access latency
for non-sequential and sequential
accesses, the type of access to the
TCM address space is indicated.
There is no restriction on the type of
memory or memory system attached
to the TCM interface other than that it
must not contain read-sensitive
locations.

The TCM uses physical addresses.
Write accesses are controlled using
the protection information stored in
the MMU.

The TCMs are typically used to store
critical code and data for which
deterministic access times are
required, which is not always the case
for a code or data which resides in a
cacheable region of memory.

Bus Interface Unit (BIU)

The ARM926EJ-S contains a
separate AMBA BIU for instructions
and data. Each interface is a full AHB
bus master, allowing all the
advantages of the multilayer AHB
system to be realized.

Unless a memory region is specified
as being nonbuffered all writes are
made using the 16-entry write-buffer,
which avoids stalling the processor
core when writes to main memory are
performed.

Coprocessor interface

The ARM926EJ-S supports the
connection of on-chip coprocessors
through an external coprocessor
interface.

The ARM v5TEJ Architecture

Registers

The ARM9EJ-S processor core
consists of a 32-bit datapath and
associated control logic. The
datapath contains 31 general-
purpose registers, coupled to a full
shifter, Arithmetic Logic Unit, and
multiplier. At any one time 16
registers are visible to the user. The
remainder are banked registers used
to speed up exception processing.
Register 15 is the Program Counter
(PC) and can be used by the majority
of instructions to reference data
relative to the current instruction.
R14 holds the return address after a
subroutine call. R13 is used (by
software convention) as a stack
pointer.

Modes and exception
handling

All privileged modes and exception
handling modes have banked
registers for R14 and R13. After an
exception, R14 holds the return
address for exception processing.
This address is used both to return
after the exception is processed and
in some cases used to address the
instruction that caused the exception.
R13 is banked across exception
modes to provide each exception
handler with a private stack pointer.
The fast interrupt mode also banks
registers eight to 12 so that interrupt
processing can begin without the
need to save or restore these
registers. A seventh processing
mode, System mode, does not have
any banked registers. It uses the
User mode registers. System mode
runs tasks that require a privileged
processor mode and allows them to
invoke all classes of exceptions.

Status registers

The processor state is held in status
registers. The current operating
processor status is in the Current
Program Status Register (CPSR).
The CPSR holds:

Q flag (used in saturating
arithmetic instructions)

four ALU flags (Negative, Zero,
Carry, and Overflow)

two interrupt disable bits (one for
each type of interrupt)

state bits to indicate ARM,
Thumb, or Java state

five bits to encode the current
processor mode.

All five exception modes also have a
Saved Program Status Register
(SPSR) which holds the CPSR of the
task immediately before the
exception occurred.

Exception types

ARM9EJ-S supports five types of
exception, and a privileged
processing mode for each type. The
types of exceptions are:

fast interrupt (FIQ)

normal interrupt (IRQ)

memory aborts

undefined instruction

software interrupt (SWI).

Conditional execution

The majority of ARM instructions are
conditionally executed. Instructions
optionally update the four condition
code flags (Negative, Zero, Carry,
and Overflow) according to their
result. Subsequent instructions are
conditionally executed according to
the status of flags. Fifteen conditions
are implemented.

Four classes of
instructions

The ARM and Thumb instruction sets
can be divided into four broad
classes of instruction:

data processing instructions

load and store instructions

branch instructions

coprocessor instructions.

Data processing

The data processing instructions
operate on data held in general
purpose registers. Of the two source
operands, one is always a register.
The other has two basic forms:

an immediate value

a register value optionally
shifted.

If the operand is a shifted register the
shift amount might have an
immediate value or the value of
another register. Four types of shift
can be specified. Most data
processing instructions can perform
a shift followed by a logical or
arithmetic operation. Multiply
instructions come in two classes:

normal 32-bit result

long 32-bit result variants.

Both types of multiply instruction can
optionally perform an accumulate
operation.

Load and store

The second class of instruction is
load and store instructions. These
instructions come in two main types:

load or store the value of a single
register

load and store multiple register
values.

The ARM v5TEJ Architecture

Load and store single register
instructions can transfer a 32-bit
word, a 16-bit halfword and an
eight-bit byte between memory and a
register. Byte and halfword loads can
be automatically zero extended or
sign extended as they are loaded.
Swap instructions perform an atomic
load and store as a synchronization
primitive.

Addressing modes

Load and store instructions have
three primary addressing modes:

offset

pre-indexed

post-indexed.

They are formed by adding or
subtracting an immediate or register-
based offset to or from a base
register. Register-based offsets can
also be scaled with shift operations.
Pre-indexed and post-indexed
addressing modes update the base
register with the base plus offset
calculation. As the PC is a general
purpose register, a 32-bit value can
be loaded directly into the PC to
perform a jump to any address in the
4GB memory space.

Block transfers

Load and store multiple instructions
perform a block transfer of any
number of the general purpose
registers to or from memory. Four
addressing modes are provided:

pre-increment addressing

post-increment addressing

pre-decrement addressing

post-decrement addressing.

The base address is specified by a
register value (which can be
optionally updated after the transfer).
As the subroutine return address and
the PC values are in general purpose

registers, very efficient subroutine
calls can be constructed.

Branch

As well as allowing any data
processing or load instruction to
change control flow (by writing the
PC) a standard branch instruction is
provided with 24-bit signed offset,
allowing forward and backward
branches of up to 32MB.

Branch with link

There is a Branch with Link (BL)
instruction which allows efficient
subroutine calls by automatically
preserving the return address.

Branch with exchange

There are three types of branches:

BX switches between ARM state
and Thumb state

BLX switches between ARM
state and Thumb state
preserving the return address

BXJ switches between ARM
state and Java state.

Coprocessor

There are three types of coprocessor
instructions:

coprocessor data processing
instructions are used to invoke a
coprocessor specific internal
operation

coprocessor register transfer
instructions allow a coprocessor
value to be transferred to or from
an ARM register

coprocessor data transfer
instructions transfer coprocessor
data to or from memory, where
the ARM calculates the address
of the transfer.

ARM926EJ-S

The V5TEJ ARM Instruction Set including DSP extensions

Mnemonic Operation

MOV

Move

MVN

Move Not

QADD

Saturated add

QDADD

Saturated add with double

QSUB

Saturated subtract

QDSUB

Saturated subtract with double

RSB

Reverse subtract

RSC

Reverse Subtract with Carry

CMP

Compare

CMN

Compare Negated

TST

Test TEQ

Test

Equivalence

ADD

Add

ADC

Add with Carry

SUB

Subtract

SBC

Subtract with Carry

AND

Logical AND

BIC

Bit Clear

EOR

Logical exclusive OR

ORR

Logical (inclusive) OR

MUL

Multiply

MLA

Multiply Accumulate

SMUL

Signed Multiply

SMULW

Signed Word Multiply-Accumulate

SMULL

Sign long multiply

SMLA

Signed Multiply-Accumulate

SMLAW

Signed Word Multiply-Accumulate SMLAL

Signed Long Multiply-Accumulate

UMULL

Unsigned long multiply

UMLAL

Unsigned Long Multiply Accumulate

CLZ

Count Leading Zeroes

BKPT

Breakpoint

MRS

Move From Status Register

MSR

Move to Status Register

Branch

BXJ

Branch to Java

Branch and Link

BLX

Branch and Link and Exchange

Branch and Exchange

SWI

Software Interrupt

LDR

Load Word

STR

Store Word

LDRH

Load Halfword

STRH

Store Halfword

LDRB

Load Byte

STRB

Store Byte

LDRD

Load double

STRD

Store double

LDM

Load Multiple

STM

Store Multiple

LDRSH

Load Signed Halfword

LDRSB

Load Signed Byte

LDRT

Load Register with Translation

STRT

Store Register with Translation

LDRBT

Load Register Byte with TranslationSTRBT

Store Register Byte with Translation

SWP

Swap Word

SWPB

Swap Byte

PLD

No operation

CDP

Coprocessor Data Processing

MRC

Move From Coprocessor

MCR

Move to Coprocessor

MRCC

Move double from coprocessor

MCRR

Move double to coprocessor

LDC

Load To Coprocessor

STC

Store From Coprocessor

The ARM v5TEJ Architecture

The Thumb instruction set

Mnemonic Operation

MOV

Move

MVN

Move Not

ADD

Add

ADC

Add with Carry

SUB

Subtract

SBC

Subtract with Carry

CMP

Compare

CMN

Compare Negated

TST

Test NEG

Negate

AND

Logical AND

BIC

Bit Clear

EOR

Logical Exclusive OR

ORR

Logical (inclusive) OR

LSL

Logical Shift Left

LSR

Logical Shift Right

ASR

Arithmetic Shift Right

ROR

Rotate Right

MUL

Multiply

BKPT

Breakpoint

Unconditional Branch

Bcc

Conditional Branch

Branch and Link

BLX

Branch and Link and Exchange

Branch and Exchange

SWI

Software Interrupt

LDR

Load Word

STR

Store Word

LDRH

Load Halfword

STRH

Store Halfword

LDRB

Load Byte

STRB

Store Byte

LDRSH

Load Signed Halfword

LDRSB

Load Signed Byte

LDMIA

Load Multiple

STMIA

Store Multiple

PUSH

Push Registers to stack

POP

Pop Registers from stack

The ARM v5TEJ Architecture

Modes and registers

User and

System mode

Supervisor

mode

Abort mode

Undefined

mode

Interrupt mode

Fast Interrupt

mode

R8_FIQ

R9_FIQ

R10

R10_FIQ

R11

R11_FIQ

R12

R12_FIQ

R13

R13_SVC

R13_ABORT

R13_UNDEF

R13_IRQ

R13_FIQ

R14

R14_SVC

R14_ABORT

R14_UNDEF

R14_IRQ

R14_FIQ

CPSR

SPSR_SVC

SPSR_ABORT

SPSR_UNDEF

SPSR_IRQ

SPSR_FIQ

Mode-specific banked registers

The ARM v5TEJ Architecture

ARM9EJ-S
processor core

The ARM9EJ-S processor core is an
implementation of the ARM
Instruction Set Architecture (ISA)
ARMv5TEJ, extended with enhanced
Java and DSP performance.
ARMv5TEJ is a superset of the
ARMv4 ISA implemented by the
StrongARMTM processors and the
ARMv4T ISA implemented by the
ARM7TM Thumb and ARM9TM Thumb
Family processors.

Performance and code
density

The ARM9EJ-S executes three
instruction sets:

32-bit ARM instruction set

16-bit Thumb instruction set

8 bit Java instruction set.

The ARM instruction set allows a
program to achieve maximum
performance with the minimum
number of instructions.

The majority of ARM9EJ-S
instructions are executed in a single
cycle. These are shown in the
ARM9EJ-S instruction execution
timing table on page 10. The table
shows for each instruction class:

Issue Cycles:
Number of cycles in execute
stage.

Result Delay:
Number of cycles after execute
until data available.

The simpler Thumb instruction set
offers much increased code density
for code that does not require
maximum performance. Code can
switch between the ARM and Thumb
instruction sets on any procedure
call.

Java state

In Java state the ARM9EJ-S
processor core executes a majority
of Java Bytecodes natively.
Bytecodes are decoded in two
stages (compared to a single decode
stage when in ARM/Thumb state).

ARM9EJ-S integer
pipeline stages

The integer pipeline consists of five
stages to maximize instruction
throughput on ARM9EJ-S:

F: Instruction Fetch

D: Instruction Decode and Register
Read

E: Execute Shift and ALU, or
Address Calculate, or
Multiply

M: Memory Access and Multiply

W: Register Write

Pipelining

By overlapping the various stages of
execution, ARM9EJ-S maximizes the
clock rate achievable to execute
each instruction. It delivers a
throughput approaching one
instruction per cycle.

32-bit data buses

ARM9EJ-S provides 32-bit data
buses between the processor core
and the instruction and data caches,
and between coprocessors and the
processor core. This allows
ARM9EJ-S to achieve very high
performance on many code
sequences, especially those that
require data movement in parallel
with data processing.

Debug features

The ARM9EJ-S processor core also
incorporates a sophisticated debug
unit to allow both software tasks and

external debug hardware to perform
hardware and software breakpoint,
single stepping, register and memory
access. This functionality is made
available from hardware using the
JTAG port. Full-speed, real-time
execution of the processor is
maintained until a breakpoint is hit. At
this point control is passed either to a
software handler or to JTAG control.

The ARM v5TEJ Architecture

Table 1: ARM9EJ-S instruction execution timing

Instruction class Issue Cycles Result delay

Branch

3 (4 for BXJ)

Condition failed

ALU instruction

with register specified shift

MOV PC, Rx

ALU instruction dest = PC

3(4 for shift instructions)

MUL (flags modified)

4 to 5

MUL (flags unmodified)

1 to 3

MSR (flags only)

MSR (mode change)

MRS

LDR (loaded value)

1(2 for shift instructions)

STR

1(2 for shift instructions)

LDM

Number of words

0 (Not last register in list)

LDM

Number of words

1 (Last register in list)

STM

Number of words

SWP

CDP

MRC

MCR

LDC

Number of words

LDC dest = PC

LDC dest = PC, scaled offset

STC

Number of words

LDRD

0 (Not last register in list)

LDRD

1 (Last register in list)

STRD

PLD

MRRC

0 (Not last register in list)

MRRC

1 (Last register in list)

MCRR

System Design and Third Party Support

Embedded Trace
Macrocell

The Embedded Trace Macrocell
(ETM) monitors the ARM926EJ-S
processor core address, data, and
status signals and generates a
compressed trace data stream of
processor activity. The ETM
provides non-intrusive real-time
instruction trace by broadcasting
compressed instruction addresses
at branches. Data tracing is
supported by broadcasting load and
store operations. The unique
triggering and data capabilities of
the ETM means that complex
events can be easily traced.

AMBA bus architecture

The ARM926EJ-S processor is
designed for use with the AMBA
multi-master on-chip bus
architecture. AMBA includes an
AHB connecting processors and
high-bandwidth peripherals and
memory interfaces, and a low-
power peripheral bus allowing a
large number of low-bandwidth
peripherals.

The ARM926EJ-S supports
multilayer AHB, providing 32-bit
address and 32-bit data buses for
instructions and data for
high-bandwidth data transfers
made possible by on-chip memory
and modern SDRAM and RAMBUS
memories.

Compatibility

The ARM926EJ-S is backwards
compatible from the ARM7, ARM9,
ARM9E Thumb and StrongARM
processor families, giving designers
software-compatible processors
with a wide range of price and
performance points.

Everything you need

ARM provides a wide range of
products and services to support its
processor families, including
software development tools,
development boards, models,
applications software, training, and
consulting services.

The ARM Architecture today enjoys
broad third party support. The
ARM9 Thumb family of processors
has strong software compatibility
with existing ARM families ensuring
that its users benefit immediately
from existing support. ARM is
working with its software, EDA, and
semiconductor partners to extend
this support to use new ARM9
Family features.

Current support

Support for the ARM architecture
today includes:

Software toolkits available from
ARM: ARM Developer Suite
(ADS), Cygnus/GNU, Microtec,
Greenhills, JavaSoft,
MetaWare, and Windriver
allowing software development
in C, C++, Java, FORTRAN,
Pascal, Ada, and assembler.
ARM Developer Suite (ADS)
includes:

- Integrated development

environment

- C, C++, assembler, simulators

and windowing source-level
debugger

- Available on Windows95,

WindowsNT, and Unix.

- ARM Multi-ICETM JTAG

interface

- Allows EmbeddedICE

software debug of ARM
processor systems

- ARMulator instruction-

accurate software simulator.

ARM and third party
Development boards.

Application software
components: DSP, speech and
image compression, software
modems, Chinese character
input, network protocols, for
example.

Design Sign-off Models provide
quality ASIC simulation.

Major OS including Microsoft
WindowsCE, EPOC, and
LINUX.

40+ Real-time Operating
Systems including Windriver
VxWorks, pSOS,
Sun Microsystems, Microtec
VRTX, JMI, Embedded
SystemProducts RTXC.

Hardware and software
cosimulation tools from leading
EDA Vendors.

For more information, see

www.arm.com

Contacting ARM

Words and logos marked with

or TM are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice.

Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except
with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document
are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose,
are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any
information in this document, or any error or omission in such information, or any incorrect use of the product.

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Part Number ARM926EJ-S

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