Copyright © 2001 ARM Limited. All rights reserved.
ARM DDI 0229A
ARM720T
(Rev 4)
Technical Reference Manual
ii
Copyright © 2001 ARM Limited. All rights reserved.
ARM DDI 0229A
ARM720T
Technical Reference Manual
Copyright © 2001 ARM Limited. All rights reserved.
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Change history
Date
Issue
Change
22 November 2001
A
ARM720T (Rev 4) first release
ARM DDI 0229A
Copyright © 2001 ARM Limited. All rights reserved.
iii
Contents
ARM720T Technical Reference Manual
Preface
About this document .................................................................................... xiv
Feedback ................................................................................................... xviii
Chapter 1
Introduction
1.1
About the ARM720T (Rev 4) macrocell ...................................................... 1-2
1.2
Coprocessors .............................................................................................. 1-7
1.3
About the instruction set ............................................................................. 1-8
Chapter 2
Programmer's Model
2.1
Processor operating states ......................................................................... 2-2
2.2
Memory formats .......................................................................................... 2-3
2.3
Instruction length ......................................................................................... 2-5
2.4
Data types ................................................................................................... 2-6
2.5
Operating modes ........................................................................................ 2-7
2.6
Registers ..................................................................................................... 2-8
2.7
Program status registers ........................................................................... 2-13
2.8
Exceptions ................................................................................................ 2-16
2.9
Relocation of low virtual addresses by the FCSE PID .............................. 2-23
2.10
Reset ......................................................................................................... 2-24
2.11
Implementation-defined behavior of instructions ....................................... 2-25
Contents
iv
Copyright © 2001 ARM Limited. All rights reserved.
ARM DDI 0229A
Chapter 3
Configuration
3.1
About configuration ..................................................................................... 3-2
3.2
Internal coprocessor instructions ................................................................ 3-3
3.3
Registers .................................................................................................... 3-4
Chapter 4
Instruction and Data Cache
4.1
About the instruction and data cache ......................................................... 4-2
4.2
IDC validity ................................................................................................. 4-4
4.3
IDC enable, disable, and reset ................................................................... 4-5
Chapter 5
Write Buffer
5.1
About the write buffer ................................................................................. 5-2
5.2
Write buffer operation ................................................................................. 5-3
Chapter 6
The Bus Interface
6.1
About the bus interface ............................................................................... 6-2
6.2
Bus interface signals .................................................................................. 6-4
6.3
Transfer types ............................................................................................. 6-6
6.4
Address and control signals ....................................................................... 6-9
6.5
Slave transfer response signals ............................................................... 6-12
6.6
Data buses ............................................................................................... 6-14
6.7
Arbitration ................................................................................................. 6-17
6.8
Bus clocking ............................................................................................. 6-18
6.9
Reset ........................................................................................................ 6-19
Chapter 7
Memory Management Unit
7.1
About the MMU ........................................................................................... 7-2
7.2
MMU program-accessible registers ............................................................ 7-4
7.3
Address translation ..................................................................................... 7-5
7.4
MMU faults and CPU aborts ..................................................................... 7-20
7.5
Fault address and fault status registers .................................................... 7-21
7.6
Domain access control ............................................................................. 7-22
7.7
Fault checking sequence .......................................................................... 7-24
7.8
External aborts ......................................................................................... 7-27
7.9
Interaction of the MMU and cache ............................................................ 7-28
Chapter 8
Coprocessor Interface
8.1
About coprocessors .................................................................................... 8-2
8.2
Coprocessor interface signals .................................................................... 8-4
8.3
Pipeline-following signals ........................................................................... 8-5
8.4
Coprocessor interface handshaking ........................................................... 8-6
8.5
Connecting coprocessors ......................................................................... 8-11
8.6
Not using an external coprocessor ........................................................... 8-13
8.7
STC operations ......................................................................................... 8-14
8.8
Undefined instructions .............................................................................. 8-15
8.9
Privileged instructions ............................................................................... 8-16
Contents
ARM DDI 0229A
Copyright © 2001 ARM Limited. All rights reserved.
v
Chapter 9
Debugging Your System
9.1
About debugging your system .................................................................... 9-3
9.2
Controlling debugging ................................................................................. 9-5
9.3
Entry into debug state ................................................................................. 9-7
9.4
Debug interface ......................................................................................... 9-12
9.5
ARM720T core clock domains .................................................................. 9-13
9.6
The EmbeddedICE-RT macrocell ............................................................. 9-14
9.7
Disabling EmbeddedICE-RT ..................................................................... 9-16
9.8
EmbeddedICE-RT register map ................................................................ 9-17
9.9
Monitor mode debugging .......................................................................... 9-18
9.10
The debug communications channel ........................................................ 9-20
9.11
Scan chains and the JTAG interface ........................................................ 9-24
9.12
The TAP controller .................................................................................... 9-27
9.13
Public JTAG instructions ........................................................................... 9-29
9.14
Test data registers .................................................................................... 9-32
9.15
Scan timing ............................................................................................... 9-37
9.16
Examining the core and the system in debug state .................................. 9-40
9.17
Exit from debug state ................................................................................ 9-44
9.18
The program counter during debug .......................................................... 9-46
9.19
Priorities and exceptions ........................................................................... 9-50
9.20
Watchpoint unit registers .......................................................................... 9-51
9.21
Programming breakpoints ......................................................................... 9-56
9.22
Programming watchpoints ......................................................................... 9-59
9.23
Abort status register .................................................................................. 9-61
9.24
Debug control register ............................................................................... 9-62
9.25
Debug status register ................................................................................ 9-65
9.26
Coupling breakpoints and watchpoints ..................................................... 9-67
9.27
EmbeddedICE-RT timing .......................................................................... 9-70
Chapter 10
ETM Interface
10.1
About the ETM interface ........................................................................... 10-2
10.2
Enabling and disabling the ETM7 interface ............................................... 10-3
10.3
Connections between the ETM7 macrocell and the ARM720T (Rev 4)
processor .................................................................................................. 10-4
10.4
Clocks and resets ..................................................................................... 10-6
10.5
Debug request wiring ................................................................................ 10-7
10.6
TAP interface wiring .................................................................................. 10-8
Chapter 11
Test Support
11.1
About the ARM720T (Rev 4) test registers ............................................... 11-2
11.2
Automatic Test Pattern Generation (ATPG) .............................................. 11-3
11.3
Test state register ..................................................................................... 11-4
11.4
Cache test registers and operations ......................................................... 11-5
11.5
MMU test registers and operations ......................................................... 11-12
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