A42L2604 Series

Preliminary

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

PRELIMINARY (November, 2001, Version 0.2)

AMIC Technology, Inc.

Features

Organization: 4,194,304 words X 4 bits

Part Identification

- A42L2604

(2K Ref.)

- A42L2604-L

(2K Ref. with self-refresh)

Single 3.3V power supply/built-in VBB generator

Low power consumption

- Operating: 80mA (-45 max)

Standby: 1mA (TTL), 1mA (CMOS),

350

A (Self-refresh current)

High speed

- 45/50 ns RAS access time
- 20/22 ns column address access time

12/13 ns CAS access time

18/20 ns EDO Page Mode Cycle Time

Industrial operating temperature range: -40

C to +85

for -U

Fast Page Mode with Extended Data Out

2K Refresh Cycle in 32ms

Read-modify-write, RAS -only, CAS -before- RAS ,

Hidden refresh capability

TTL-compatible, three-state I/O

JEDEC standard packages

300mil, 24/26-pin SOJ

300mil, 24/26-pin TSOP type II package

General Description

The A42L2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by
4-bit configuration. This product can execute Write and
Read operation via CAS pin.
The A42L2604 offers an accelerated Fast Page Mode

Pin Configuration

SOJ

TSOP

VCC

I/O

CAS

I/O

VSS

A42L2604S

RAS

A10

VCC

VSS

VCC

I/O

CAS

I/O

VSS

A42L2604V

RAS

A10

VCC

VSS

cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 2048(2K Ref.) words
within a row at a 56/50 MHz EDO cycle, making the
A42L2604 ideally suited for graphics, digital signal
processing and high performance computing systems.

Pin Descriptions

Symbol

Description

A0 A10

Address Inputs (2K product)

I/O

- I/O

Data Input/Output

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

Output Enable

VCC

3.3V Power Supply

VSS

Ground

No Connection

A42L2604 Series

PRELIMINARY

(November, 2001, Version 0.2)

AMIC Technology, Inc.

Selection Guide

Symbol

Description

-45

-50

Unit

RAC

Maximum RAS Access Time

Maximum Column Address Access Time

CAC

Maximum CAS Access Time

OEA

Maximum Output Enable ( OE ) Access Time

Minimum Read or Write Cycle Time

Minimum EDO Cycle Time

Functional Description

The A42L2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.

RAS and CAS are used to strobe the row address and the

column address, respectively.

A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or

CAS , whichever occurs later. The data inputs and outputs

are routed through 4 common I/O pins, with RAS , CAS ,

WE and OE controlling the in direction.

EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by

CAS . While holding RAS low, CAS can be toggled to

strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (t

). Since data can be output after CAS goes high,

the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain

valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.

A memory cycle is terminated by returning both RAS and

CAS high. Memory cell data will retain its correct state by

maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.

Power-On

The initial application of the VCC supply requires a 200 ľs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid V

during Power-On to avoid current

surges.

A42L2604 Series

PRELIMINARY

(November, 2001, Version 0.2)

AMIC Technology, Inc.

Block Diagram

Recommended Operating Conditions

(Ta = 0

C to +70

C or -40

C to +85

Symbol

Description

Min.

Typ.

Max.

Unit

VCC

Power Supply

3.0

3.3

3.6

VSS

Input High Voltage

2.0

VCC + 0.3

Input Low Voltage

-1.0

0.8

Control

Clocks

VBB Generator

Refresh Timer

Refresh control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Memory Array
4,194,304 X 4

Cells

Sense Amps & I/O

Data in

Buffer

Data out

Buffer

Vcc
Vss

RAS

CAS

A0~A10

I/O

A42L2604 Series

PRELIMINARY

(November, 2001, Version 0.2)

AMIC Technology, Inc.

Truth Table

Function

RAS

CAS

Address

I/Os

Standby

High-Z

Read: Word

Row/Col.

Data Out

Read

Row/Col.

Data Out

Write: Word (Early)

Row/Col.

Data In

Write (Early)

Row/Col.

Data In

Read-Write

Row/Col.

Data Out

Data In

EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles

L
L

H
H

Row/Col.

Col.

Data Out
Data Out

EDO-Page-Mode Write (Early)
-First cycle
-Subsequent Cycles

L
L

X
X

Row/Col.

Col.

Data In
Data In

EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles

L
L

Row/Col.

Col.

Data Out

Data In

Data Out

Data In

Hidden Refresh Read

Row/Col.

Data Out

Hidden Refresh Write

Row/Col.

Data In

High-Z

RAS -Only Refresh

Row

High-Z

CBR Refresh

High-Z

Self Refresh (L-ver only)

High-Z

Part Number A42L2604