PRELIMINARY

This document contains information on a product under development at FASL LLC. The information is intended to
help you evaluate this product. FASL LLC reserves the right to change or discontinue work on this proposed product
without notice.

Publication Am29LV800D_00 Rev. A Amend. 4

Issue Date: January 21, 2005

Am29LV800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory

Distinctive Characteristics

Single power supply operation
-- 2.7 to 3.6 volt read and write operations

for battery-powered applications

Manufactured on 0.23 µm process

technology
-- Compatible with 0.32 µm Am29LV800

device

High performance
-- Access times as fast as 70 ns

Ultra low power consumption (typical

values at 5 MHz)

-- 200 nA Automatic Sleep mode current
-- 200 nA standby mode current
-- 7 mA read current

-- 15 mA program/erase current

Flexible sector architecture

-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

-- One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

-- Supports full chip erase
-- Sector Protection features:

A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors

Unlock Bypass Program Command
-- Reduces overall programming time when

issuing multiple program command

sequences

Top or bottom boot block configurations
available

Embedded Algorithms

-- Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

-- Embedded Program algorithm

automatically writes and verifies data at

specified addresses

Minimum 1 million write cycle guarantee

per sector

20-year data retention at 125°C

-- Reliable operation for the life of the system

Package option

-- 48-ball FBGA
-- 48-pin TSOP

-- 44-pin SO

Compatibility with JEDEC standards

-- Pinout and software compatible with single-

power supply Flash

-- Superior inadvertent write protection

Data# Polling and toggle bits
-- Provides a software method of detecting

program or erase operation completion

Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting

program or erase cycle completion

Erase Suspend/Erase Resume

-- Suspends an erase operation to read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

Hardware reset pin (RESET#)
-- Hardware method to reset the device to

reading array data

For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration

path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.

Am29LV800D

Am29LV800D_00_A4_E January 21, 2005

P R E L I M I N A R Y

General Description

The Am29LV800D is an 8 Mbit, 3.0 volt-only

Flash memory organized as 1,048,576 bytes or

524,288 words. The device is offered in 48-ball

FBGA, 44-pin SO, and 48-pin TSOP packages.

For more information, refer to publication

number 21536. The word-wide data (x16)

appears on DQ15DQ0; the byte-wide (x8) data

appears on DQ7DQ0. This device requires only

a single, 3.0 volt V

supply to perform read,

program, and erase operations. A standard

EPROM programmer can also be used to program

and erase the device.

This device is manufactured using AMD's 0.23

µm process technology, and offers all the fea-

tures and benefits of the Am29LV800B, which

was manufactured using 0.32 µm process tech-

nology.
The standard device offers access times of 70,

90, and 120 ns, allowing high speed micropro-

cessors to operate without wait states. To elim-

inate bus contention the device has separate

chip enable (CE#), write enable (WE#) and

output enable (OE#) controls.

The device requires only a single 3.0 volt

power supply for both read and write func-

tions. Internally generated and regulated volt-

ages are provided for the program and erase

operations.
The device is entirely command set compatible

with the JEDEC single-power-supply Flash

standard. Commands are written to the

command register using standard micropro-

cessor write timings. Register contents serve as

input to an internal state-machine that controls

the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase opera-

tions. Reading data out of the device is similar

to reading from other Flash or EPROM devices.

Device programming occurs by executing the

program command sequence. This initiates the

Embedded Program algorithm--an internal

algorithm that automatically times the program

pulse widths and verifies proper cell margin. The

Unlock Bypass mode facilitates faster pro-

gramming times by requiring only two write

cycles to program data instead of four.
Device erasure occurs by executing the erase

c o m m a n d s e q u e n c e . T h i s i n i t i a t e s t h e

Embedded Erase algorithm--an internal algo-

rithm that automatically preprograms the array

(if it is not already programmed) before exe-

cuting the erase operation. During erase, the

device automatically times the erase pulse

widths and verifies proper cell margin.

The host system can detect whether a program

or erase operation is complete by observing the

RY/BY# pin, or by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a

program or erase cycle has been completed, the

device is ready to read array data or accept

another command.
The sector erase architecture allows memory

sectors to be erased and reprogrammed without

affecting the data contents of other sectors. The

device is fully erased when shipped from the

factory.

Hardware data protection measures include

a low V

detector that automatically inhibits

write operations during power transitions. The

hardware sector protection feature disables

both program and erase operations in any com-

bination of the sectors of memory. This can be

achieved in-system or via programming equip-

ment.
The Erase Suspend feature enables the user to

put erase on hold for any period of time to read

data from, or program data to, any sector that

is not selected for erasure. True background

erase can thus be achieved.

The hardware RESET# pin terminates any

operation in progress and resets the internal

state machine to reading array data. The

RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

device, enabling the system microprocessor to

read the boot-up firmware from the Flash

memory.
The device offers two power-saving features.

When addresses have been stable for a specified

amount of time, the device enters the auto-

matic sleep mode. The system can also place

the device into the standby mode. Power con-

sumption is greatly reduced in both these

modes.

AMD's Flash technology combines years of Flash

memory manufacturing experience to produce

the highest levels of quality, reliability and cost

effectiveness. The device electrically erases

all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is pro-

grammed using hot electron injection.

January 21, 2005 Am29LV800D_00_A4_E

Am29LV800D

P R E L I M I N A R Y

Table Of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Package ..............7

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Standard Products ......................................................................8

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29LV800D Device Bus Operations .10

Word/Byte Configuration ...................................................... 10
Requirements for Reading Array Data ............................... 10
Writing Commands/Command Sequences .........................11
Program and Erase Operation Status ...................................11
Standby Mode ..............................................................................11
Automatic Sleep Mode ..............................................................11
RESET#: Hardware Reset Pin .................................................11
Output Disable Mode ...............................................................12

Table 2. Am29LV800DT Top Boot Block
Sector Addresses ........................................12
Table 3. Am29LV800DB Bottom Boot Block
Sector Addresses ........................................13

Autoselect Mode ........................................................................13

Table 4. Am29LV800D Autoselect Codes
(High Voltage Method) ................................14

Sector Protection/Unprotection .......................................... 14
Temporary Sector Unprotect ............................................... 14

Figure 1. Temporary Sector Unprotect
Operation .................................................. 15
Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms ........................ 16

Hardware Data Protection .....................................................17

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 17

Reading Array Data ...................................................................17
Reset Command .........................................................................17
Autoselect Command Sequence .......................................... 18
Word/Byte Program Command Sequence ....................... 18

Figure 1. Program Operation ........................ 19

Chip Erase Command Sequence .......................................... 19
Sector Erase Command Sequence ...................................... 19
Erase Suspend/Erase Resume Commands ....................... 20

Figure 1. Erase Operation ............................ 21
Table 5. Am29LV800D Command Definitions ..21

Write Operation Status . . . . . . . . . . . . . . . . . . . . 22

DQ7: Data# Polling ..................................................................22

Figure 1. Data# Polling Algorithm ................. 23

RY/BY#: Ready/Busy# .............................................................23
DQ6: Toggle Bit I ......................................................................24
DQ2: Toggle Bit II .....................................................................24
Reading Toggle Bits DQ6/DQ2 ............................................24
DQ5: Exceeded Timing Limits ..............................................25
DQ3: Sector Erase Timer .......................................................25

Figure 1. Toggle Bit Algorithm ...................... 25
Table 6. Write Operation Status ....................26

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 27
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .28

CMOS Compatible .................................................................. 28

Figure 1. I

CC1

Current vs. Time (Showing Active

and Automatic Sleep Currents) .................... 29
Figure 1. Typical I

CC1

vs. Frequency ............. 29

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 1. Test Setup................................... 30

Table 7. Test Specifications ........................................30

Key to Switching Waveforms. . . . . . . . . . . . . . . . 30

Figure 1. Input Waveforms and
Measurement Levels................................... 30

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31

Read Operations ........................................................................31

Figure 1. Read Operations Timings ............... 31

Hardware Reset (RESET#) ....................................................32

Figure 1. RESET# Timings........................... 32

Word/Byte Configuration (BYTE#) ..................................33

Figure 1. BYTE# Timings for Read
Operations................................................ 34
Figure 1. BYTE# Timings for Write
Operations................................................ 34

Erase/Program Operations ....................................................35

Figure 1. Program Operation Timings............ 36
Figure 1. Chip/Sector Erase Operation
Timings .................................................... 37
Figure 1. Data# Polling Timings (During
Embedded Algorithms) ............................... 38
Figure 1. Toggle Bit Timings (During
Embedded Algorithms) ............................... 38
Figure 1. DQ2 vs. DQ6 ............................... 39

Temporary Sector Unprotect ...............................................39

Figure 1. Temporary Sector Unprotect

Timing Diagram ......................................... 39
Figure 1. Sector Protect/Unprotect

Timing Diagram ......................................... 40

Alternate CE# Controlled

Erase/Program Operations .................................................... 41

Figure 1. Alternate CE# Controlled Write
Operation Timings...................................... 42

Erase and Programming Performance . . . . . . . . . 43
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 43
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 43
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . . .44

TS 048--48-Pin Standard TSOP ........................................ 44
TSR048--48-Pin Reverse TSOP .........................................45
FBB 048--48-Ball Fine-Pitch Ball Grid Array
(FBGA) 6 x 9 mm ................................................................... 46

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 47

VBK 048 - 48 Ball Fine-Pitch Ball Grid Array
(FBGA) 6.15 x 8.15 mm .............................................................47
SO 044--44-Pin Small Outline Package .......................... 48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .49

Part Number AM29LV800DT-90

Document Outline