PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Publication# 21415

Rev: C Amendment/+2

Issue Date: March 1998

Am29LV017B

16 Megabit (2 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

Single power supply operation

-- Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

-- Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with
high performance 3.3 volt microprocessors

Manufactured on 0.35 µm process technology

High performance

-- Full voltage range: access times as fast as 90 ns

-- Regulated voltage range: access times as fast

as 80 ns

Ultra low power consumption (typical values at
5 MHz)

-- 200 nA Automatic Sleep mode current

-- 200 nA standby mode current

-- 9 mA read current

-- 15 mA program/erase current

Flexible sector architecture

-- Thirty-two 64 Kbyte sectors

-- Supports full chip erase

-- Sector Protection features:

A hardware method of locking a sector to
prevent any program or erase operations within
that sector

Sectors can be locked in-system or via
programming equipment

Temporary Sector Unprotect feature allows code
changes in previously locked sectors

Unlock Bypass Program Command

-- Reduces overall programming time when

issuing multiple program command sequences

Embedded Algorithms

-- Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

-- Embedded Program algorithm automatically

writes and verifies data at specified addresses

Minimum 1,000,000 write cycle guarantee per
sector

Package option

-- 48-ball FBGA

-- 40-pin TSOP

CFI (Common Flash Interface) compliant

-- Provides device-specific information to the

system, allowing host software to easily
reconfigure for different Flash devices

Compatibility with JEDEC standards

-- Pinout and software compatible with single-

power supply Flash

-- Superior inadvertent write protection

Data# Polling and toggle bits

-- Provides a software method of detecting

program or erase operation completion

Ready/Busy# pin (RY/BY#)

-- Provides a hardware method of detecting

program or erase cycle completion

Erase Suspend/Erase Resume

-- Suspends an erase operation to read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

Hardware reset pin (RESET#)

-- Hardware method to reset the device to reading

array data

Am29LV017B

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29LV017B is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in 48-ball FBGA and 40-pin TSOP packages.
The byte-wide (x8) data appears on DQ7DQ0. All
read, program, and erase operations are accomplished
using only a single power supply. The device can also
be programmed in standard EPROM programmers.

The standard device offers access times of 80, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.

The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.

Am29LV017B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

3
4
5
6
7
8

17
18

19
20

9
10
11
12
13
14
15

38
37
36
35
34
33
32
31
30
29
28
27
26

24
23
22
21

A16

A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6

A4
A3
A2
A1

A17

DQ0

A20
A19
A10

DQ7
DQ6
DQ5

OE#

CE#

DQ4

DQ3
DQ2
DQ1

2
3
4
5
6
7
8

17
18
19
20

9
10
11
12
13
14
15

39
38
37
36
35
34
33
32
31
30
29
28
27
26

24
23
22
21

A16

A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

RY/BY#

A18

A7
A6

A4
A3
A2
A1

A17

DQ0

A20
A19
A10
DQ7
DQ6
DQ5

OE#

CE#
A0

DQ4
V

NC
DQ3
DQ2
DQ1

CE#

OE#

A18

DQ0

DQ1

RY/BY#

DQ2

DQ3

WE#

RESET#

DQ5

DQ4

A11

A12

A19

A10

DQ6

DQ7

A14

A13

A15

A16

A17

A20

21415C-2

40-Pin Reverse TSOP

40-Pin Standard TSOP

48-Ball FBGA (Bottom View)

Am29LV017B

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION
Am29LV017B
16 Megabit (2 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase

-80R

Am29LV017B

OPTIONAL PROCESSING
Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)

I = Industrial (40°C to +85°C)

E = Extended (55°C to +125°C)

PACKAGE TYPE
E

40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)

40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)

WC =

48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 9 mm package

SPEED OPTION
See Product Selector Guide and Valid Combinations

Valid Combinations

Am29LV017B-80R

EC, FC, WCC

Am29LV017B-90

EC, EI, EE,

FC, FI, FE,

WCC, WCI, WCE

Am29LV017B-120

Am29LV017B

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the

register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.

Table 1.

Am29LV017B Device Bus Operations

Legend:
L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5 V, X = Don't Care, A

= Address In, D

= Data In, D

OUT

= Data Out

Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector
Protection/Unprotection" section.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.

See "Reading Array Data" for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I

CC1

the DC Characteristics table represents the active cur-
rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

, and OE# to V

The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The "Byte
Program Command Sequence" section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. A "sector address"
consists of the address bits required to uniquely select
a sector. The "Command Definitions" section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.

After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in this

Operation

CE#

OE#

WE#

RESET#

Addresses

DQ0DQ7

Read

OUT

Write

Standby

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Protect (See Note)

Sector Addresses,

A6 = L, A1 = H, A0 = L

, D

OUT

Sector Unprotect (See Note)

Sector Addresses

A6 = H, A1 = H, A0 = L

, D

OUT

Temporary Sector Unprotect

Am29LV017B

P R E L I M I N A R Y

mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

CC2

in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7DQ0. Standard read cycle timings and I

read specifications apply. Refer to "Write Operation
Status" for more information, and to "AC Characteris-
tics" for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V

0.3 V.

(Note that this is a more restricted voltage range than
V

.) If CE# and RESET# are held at V

, but not within

0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires
standard access time (t

) for read access when the

device is in either of these standby modes, before it is
ready to read data.

The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, "RE-
SET#: Hardware Reset Pin".

If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.

CC3

in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t

A C C

+ 3 0 n s . T h e a u t o m a t i c s l e e p m o d e i s

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. I

CC4

in the DC Characteristics table

r e p r e s e n ts th e a u to m a t i c sle e p m o d e c u r r e n t
specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t

, the

device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

±0.3 V, the device

draws CMOS standby current (I

CC4

). If RESET# is held

at V

but not within V

±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.

If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a "0" (busy) until the in-
ternal reset operation is complete, which requires a
time of t

READY

(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is "1"), the reset operation is completed
within a time of t

READY

(not during Embedded Algo-

rithms). The system can read data t

after the RE-

SET# pin returns to V

Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at V

, output from the device is

disabled. The output pins are placed in the high imped-
ance state.

Am29LV017B

P R E L I M I N A R Y

Table 2.

Am29LV017B Sector Address Table

Sector

A20

A19

A18

A17

A16

Address Range

(in hexadecimal)

SA0

00000000FFFF

SA1

01000001FFFF

SA2

02000002FFFF

SA3

03000003FFFF

SA4

04000004FFFF

SA5

05000005FFFF

SA6

06000006FFFF

SA7

07000007FFFF

SA8

08000008FFFF

SA9

09000009FFFF

SA10

0A00000AFFFF

SA11

0B00000BFFFF

SA12

0C00000CFFFF

SA13

0D00000DFFFF

SA14

0E00000EFFFF

SA15

0F00000FFFFF

SA16

10000010FFFF

SA17

11000011FFFF

SA18

12000012FFFF

SA19

13000013FFFF

SA20

14000014FFFF

SA21

15000015FFFF

SA22

16000016FFFF

SA23

17000017FFFF

SA24

18000018FFFF

SA25

19000019FFFF

SA26

1A00001AFFFF

SA27

1B00001BFFFF

SA28

1C00001CFFFF

SA29

1D00001DFFFF

SA30

1E00001EFFFF

SA31

1F00001FFFFF

Am29LV017B

P R E L I M I N A R Y

Autoselect Mode

The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 3 shows
the remaining address bits that are don't care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 8. This method
does not require V

. See "Command Definitions" for

details on using the autoselect mode.

Table 3.

Am29LV017B Autoselect Codes (High Voltage Method)

L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don't care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.

The primary method requires V

on the RESET# pin

only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 21 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle.

The alternate method intended only for programming
equipment requires V

on address pin A9 and OE#.

This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. Pub-
lication number 21587 contains further details; contact
an AMD representative to request a copy.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD's ExpressFlashTM Service. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See "Autoselect Mode" for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to V

. During this mode, formerly protected

sectors can be programmed or erased by selecting the
sector addresses. Once V

is removed from the RE-

SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the timing diagrams, for this feature.

Description

CE#

OE#

WE#

A20

A16

A15

A10

DQ7

DQ0

Manufacturer ID: AMD

01h

Device ID: Am29LV017B

C8h

Sector Protection Verification

01h

(protected)

00h

(unprotected)

Am29LV017B

P R E L I M I N A R Y

Figure 1.

In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = V

Wait 1

First Write

Cycle = 60h?

Data = 01h?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = V

Wait 1

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

21415C-4

Am29LV017B

P R E L I M I N A R Y

Figure 2.

Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection

against inadvertent writes (refer to Table 8 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V

power-up

and power-down transitions, or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V

is greater than V

LKO

. The system must provide the

proper signals to the control pins to prevent uninten-
tional writes when V

is greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#
= V

, CE# = V

or WE# = V

. To initiate a write cy-

cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power

up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
a u t o m a t i c a l l y r e s e t t o r e a d i n g a r ray d a t a o n
power-up.

START

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

21415C-5

Am29LV017B

P R E L I M I N A R Y

COMMON FLASH MEMORY INTERFACE
(CFI)

The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.

This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array

data. The system can read CFI information at the
addresses given in Tables 47. To terminate reading
CFI data, the system must write the reset command.

The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 47. The
system must write the reset command to return the
device to the autoselect mode.

For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represent-
ative for copies of these documents.

Table 4.

CFI Query Identification String

Addresses

Data

Description

10h
11h
12h

51h
52h
59h

Query Unique ASCII string "QRY"

13h
14h

02h
00h

Primary OEM Command Set

15h
16h

40h
00h

Address for Primary Extended Table

17h
18h

00h
00h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

00h
00h

Address for Alternate OEM Extended Table (00h = none exists)

Table 5.

System Interface String

Addresses

Data

Description

1Bh

27h

Min. (write/erase)

D7D4: volt, D3D0: 100 millivolt

1Ch

36h

Max. (write/erase)

D7D4: volt, D3D0: 100 millivolt

1Dh

00h

Min. voltage (00h = no V

pin present)

1Eh

00h

Max. voltage (00h = no V

pin present)

1Fh

04h

Typical timeout per single byte/word write 2

µs

20h

00h

Typical timeout for Min. size buffer write 2

µs (00h = not supported)

21h

0Ah

Typical timeout per individual block erase 2

22h

00h

Typical timeout for full chip erase 2

ms (00h = not supported)

23h

05h

Max. timeout for byte/word write 2

times typical

24h

00h

Max. timeout for buffer write 2

times typical

25h

04h

Max. timeout per individual block erase 2

times typical

26h

00h

Max. timeout for full chip erase 2

times typical (00h = not supported)

Am29LV017B

P R E L I M I N A R Y

Table 6.

Device Geometry Definition

Addresses

Data

Description

27h

15h

Device Size = 2

byte

28h
29h

00h
00h

Flash Device Interface description (refer to CFI publication 100)

2Ah
2Bh

00h
00h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch

01h

Number of Erase Block Regions within device

2Dh
2Eh

2Fh
30h

1Fh
00h
00h
01h

Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)

31h
32h
33h
34h

00h
00h
00h
00h

Erase Block Region 2 Information

35h
36h
37h
38h

00h
00h
80h
00h

Erase Block Region 3 Information

39h

3Ah
3Bh
3Ch

00h
00h
00h
00h

Erase Block Region 4 Information

Table 7.

Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h
41h
42h

50h
52h
49h

Query-unique ASCII string "PRI"

43h

31h

Major version number, ASCII

44h

30h

Minor version number, ASCII

45h

01h

Address Sensitive Unlock
0 = Required, 1 = Not Required

46h

02h

Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h

01h

Sector Protect
0 = Not Supported, X = Number of sectors in per group

48h

01h

Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported

49h

04h

Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode

4Ah

00h

Simultaneous Operation: 00 = Not Supported, 01 = Supported

4Bh

00h

Burst Mode Type: 00 = Not Supported, 01 = Supported

4Ch

00h

Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page

Am29LV017B

P R E L I M I N A R Y

COMMAND DEFINITIONS

Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 8 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
"AC Characteristics" section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See "Erase Sus-
pend/Erase Resume Commands" for more information
on this mode.

The system must issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the "Reset Com-
mand" section, next.

See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.

The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.

The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command

must

be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 8 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires V

on address bit A9.

The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Table 2 for
valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

The device programs one byte of data for each pro-
gram operation. The command sequence requires four
bus cycles, and is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is

not required to provide further controls or tim-

ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
8 shows the address and data requirements for the
byte program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See "Write Operation Status"
for information on these status bits.

Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-

Am29LV017B

P R E L I M I N A R Y

quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a "0" back to a "1". Attempting to do so may halt
the operation and set DQ5 to "1," or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0"
to a "1".

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the standard
program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program ad-
dress and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming
time. Table 8 shows the requirements for the command
sequence.

During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don't cares for both cycles. The device then returns to
reading array data.

Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in "AC
Characteristics" for parameters, and to Figure 15 for
timing diagrams

Note: See Table 8 for program command sequence.

Figure 3.

Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does

not require the system to

preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 8 shows
the address and data requirements for the chip erase
command sequence.

Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21415C-6

Am29LV017B

P R E L I M I N A R Y

The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
"Write Operation Status" for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.

Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 16 for
timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. Table 8 shows the address and data re-
quirements for the sector erase command sequence.

The device does

not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer" section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to "Write Operation Status" for informa-
tion on these status bits.)

Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the "AC Characteristics" section for parameters, and to
Figure 16 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are "don't-cares" when writing the Erase Sus-
pend command.

When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device "erase
suspends" all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See "Write Operation Status" for information on these
status bits.

After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See "Write Operation Status" for more information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to

Am29LV017B

P R E L I M I N A R Y

Table 8.

Am29LV017B Command Definitions

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or CE#
pulse.

PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.

SA = Address of the sector to be erased or verified. Address
bits A20A16 uniquely select any sector.

Notes:
1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

4. Address bits are don't care for unlock and command

cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in

read mode.

6. The Reset command is required to return to the read

mode when the device is in the autoselect mode or if DQ5
goes high.

7. The fourth cycle of the autoselect command sequence is

a read cycle.

8. The data is 00h for an unprotected sector and 01h for a

protected sector.

9. The Unlock Bypass command is required prior to the

Unlock Bypass Program command.

10. The Unlock Bypass Reset command is required to return

to reading array data when the device is in the Unlock
Bypass mode.

11. The system may read and program functions in non-

erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.

12. The Erase Resume command is valid only during the

Erase Suspend mode.

Command Sequence

(Note 1)

Bus Cycles (Notes 24)

First Second

Third

Fourth

Fifth Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 5)

Reset (Note 6)

XXX

Auto-
select
(Note 7)

Manufacturer ID

XXX

X00

Device ID

XXX

X01

Sector Protect
Verify (Note 8)

XXX

X02

XXX

Byte Program

XXX

Unlock Bypass

XXX

Unlock Bypass Program
(Note 9)

XXX

Unlock Bypass Reset
(Note 10)

XXX

Chip Erase

XXX

Sector Erase

XXX

Erase Suspend (Note 11)

XXX

Erase Resume (Note 12)

XXX

l
es

Am29LV017B

P R E L I M I N A R Y

WRITE OPERATION STATUS

The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 9 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.

During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n t h e
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.

During the Embedded Erase algorithm, Data# Polling
produces a "0" on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to "1";
prior to this, the device outputs the "complement," or
"0." The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0DQ6 while
Output Enable (OE#) is asserted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
"AC Characteristics" section illustrates this.

Table 9 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7DQ0

Addr = VA

Read DQ7DQ0

Addr = VA

DQ7 = Data?

START

Notes:
1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = "1" because

DQ7 may change simultaneously with DQ5.

21415C-8

Figure 5.

Data# Polling Algorithm

Am29LV017B

P R E L I M I N A R Y

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

. (The RY/BY# pin is not availa-

ble on the 44-pin SO package.)

If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 9 shows the outputs for RY/BY#. Figures 14, 15
and 16 shows RY/BY# for reset, program, and erase
operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or CE#
to control the read cycles). When the operation is com-
plete, DQ6 stops toggling.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.

The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.

Table 9 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm in flowchart form,
and the section "Reading Toggle Bits DQ6/DQ2" ex-
plains the algorithm. Figure 18 in the "AC Characteris-
tics" section shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The "Toggle Bit II" on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses
within those sectors that have been selected for eras-
ure. (The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 9 to compare outputs for
DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchart
form, and the section "Reading Toggle Bits DQ6/DQ2"
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 18 shows the toggle bit timing dia-
gram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7DQ0 on the following read cy-
cle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system

Am29LV017B

P R E L I M I N A R Y

must write the reset command to return to reading
array data.

The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).

Table 9 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 18 in the
"AC Characteristics" section shows the toggle bit timing
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write
Reset Command

Program/Erase

Operation Complete

Read DQ7DQ0

Toggle Bit

= Toggle?

Read DQ7DQ0

Twice

Read DQ7DQ0

Notes:
1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to "1". See text.

21415C-9

Figure 6.

Toggle Bit Algorithm

(Note 1)

(Notes
1, 2)

Am29LV017B

P R E L I M I N A R Y

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a "1." This is a failure
condition that indicates the program or erase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a "1" to a location that is previously
programmed to "0." Only an erase operation can
change a "0" back to a "1." Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a "1."

Under both these conditions, the system must issue
the reset command to return the device to reading
array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from "0" to "1." If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the "Sector Erase Command Sequence" sec-
tion.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is "1", the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 9 shows the outputs for DQ3.

Table 9.

Write Operation Status

Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See "DQ5: Exceeded Timing Limits" for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/BY#

Standard
Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase
Suspend
Mode

Reading within Erase
Suspended Sector

No toggle

N/A

Toggle

Reading within Non-Erase
Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

Am29LV017B

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65

C to +150

Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 65

C to +125

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . . 0.5 V to +4.0 V

A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . . 0.5 V to +12.5 V

All other pins (Note 1) . . . . . . 0.5 V to V

+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During

voltage transitions, input or I/O pins may undershoot V

to 2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on input or I/O pins is

+0.5 V.

During voltage transitions, input or I/O pins may overshoot
to V

+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is 0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V

to 2.0 V for periods of up

to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

Figure 7.

Maximum Negative Overshoot Waveform

Figure 8.

Maximum Positive Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T

) . . . . . . . . . 40°C to +85°C

Extended (E) Devices

Ambient Temperature (T

) . . . . . . . . 55°C to +125°C

Supply Voltages

for regulated voltage range . . . . . . +3.0 V to 3.6 V

for full voltage range . . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the func-
tionality of the device is guaranteed.

20 ns

+0.8 V

0.5 V

20 ns

2.0 V

21415C-10

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

21415C-11

Am29LV017B

P R E L I M I N A R Y

DC CHARACTERISTICS

CMOS Compatible

Notes:
1. The I

current listed is typically is less than 2 mA/MHz, with OE# at V

. Typical specifications are for V

= 3.0 V.

2. I

active while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns. Typical sleep mode

current is 200 nA.

4. Not 100% tested.

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Input Load Current

= V

to V

= V

max

1.0

µA

LIT

A9 Input Load Current

= V

CC max

; A9 = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

= V

CC max

1.0

µA

CC1

Active Read Current

(Note 1)

= V

CC max

;

CE# = V

IL,

OE#

5 MHz

1 MHz

CC2

Active Write Current

(Notes 2 and 4)

= V

CC max

;

CE# = V

IL,

OE#

CC3

Standby Current

= V

CC max

;

CE#, RESET# = V

0.3 V

0.2

µA

CC4

Reset Current

= V

CC max

;

RESET# = V

0.3 V

0.2

µA

CC5

Automatic Sleep Mode (Note 3)

= V

CC max

; V

= V

± 0.3 V;

= V

0.3 V

0.2

µA

Input Low Voltage

0.5

0.8

Input High Voltage

0.7 x V

+ 0.3

Voltage for Autoselect and
Temporary Sector Unprotect

= 3.3 V

11.5

12.5

Output Low Voltage

= 4.0 mA, V

= V

CC min

0.45

OH1

Output High Voltage

= 2.0 mA, V

= V

CC min

0.85 V

OH2

= 100 µA, V

= V

CC min

0.4

LKO

Low V

Lock-Out Voltage

(Note 4)

2.3

2.5

Am29LV017B

P R E L I M I N A R Y

AC CHARACTERISTICS
Read Operations

Notes:
1. Not 100% tested.

2. See Figure 11 and Table 10 for test specifications.

Parameter

Description

Speed Option

JEDEC

Std

Test Setup

-80R

-90

-120

Unit

AVAV

Read Cycle Time (Note 1)

Min

120

AVQV

ACC

Address to Output Delay

CE# = V

OE# = V

Max

120

ELQV

Chip Enable to Output Delay

OE# = V

Max

120

GLQV

Output Enable to Output Delay

Max

EHQZ

Chip Enable to Output High Z (Note 1)

Max

GHQZ

Output Enable to Output High Z (Note 1)

Max

OEH

Output Enable
Hold Time (Note 1)

Read

Min

Toggle and
Data# Polling

Min

AXQX

Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)

Min

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

ACC

OEH

0 V

RY/BY#

RESET#

21415C-16

Figure 13.

Read Operations Timings

Am29LV017B

P R E L I M I N A R Y

AC CHARACTERISTICS
Erase/Program Operations

Notes:
1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

Parameter

-80R

-90

-120

JEDEC

Std.

Description

Unit

AVAV

Write Cycle Time (Note 1)

Min

120

AVWL

Address Setup Time

Min

WLAX

Address Hold Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

OES

Output Enable Setup Time (Note 1)

Min

GHWL

Read Recovery Time Before Write
(OE# High to WE# Low)

Min

ELWL

CE# Setup Time

Min

WHEH

CE# Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse Width High

Min

WHWH1

Programming Operation (Note 2)

Typ

µs

WHWH2

Sector Erase Operation (Note 2)

Typ

0.7

sec

VCS

Setup Time (Note 1)

Min

µs

Recovery Time from RY/BY#

Min

BUSY

Program/Erase Valid to RY/BY# Delay

Min

Am29LV017B

P R E L I M I N A R Y

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

DQ7

DQ0DQ6

RY/BY#

BUSY

Complement

True

Addresses

OEH

Status Data

Complement

Status Data

True

Valid Data

ACC

Note: VA = Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

21415C-20

Figure 17.

Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses

OEH

ACC

Valid Data

Valid Status

(first read)

(second read)

(stops toggling)

Valid Status

Note: VA = Valid address; not required for DQ6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.

21415C-21

Figure 18.

Toggle Bit Timings (During Embedded Algorithms)

Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended
sector.

21415C-22

Figure 19.

DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Am29LV017B

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Notes:
1. Typical program and erase times assume the following conditions: 25

C, 3.0 V V

, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See

Table 8 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except V

. Test conditions: V

= 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:
1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.7

Excludes 00h programming
prior to erasure (Note 4)

Chip Erase Time

22.5

Byte Programming Time

300

µs

Excludes system level
overhead (Note 5)

Chip Programming Time (Note 4)

Description

Min

Max

Input voltage with respect to V

on all pins except I/O pins

(including A9, OE#, and RESET#)

1.0 V

12.5 V

Input voltage with respect to V

on all I/O pins

1.0 V

+ 1.0 V

Current

100 mA

+100 mA

Parameter

Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

= 0

7.5

OUT

Output Capacitance

OUT

= 0

8.5

IN2

Control Pin Capacitance

= 0

7.5

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

Years

125

Years

Am29LV017B

P R E L I M I N A R Y

REVISION SUMMARY

Global

Deleted SO package from data sheet.

Revision C

Alternate CE# Controlled Erase/Program
Operations

Changed t

from 45 to 35 ns on 80R and 90 speed

options.

Revision C+1

Global

Changed data sheet status to Preliminary.

Reset Command

Deleted the last paragraph in this section.

Revision C+2

Figure 1, In-System Sector Protect/Unprotect
Algorithms

In the sector protect algorithm, added a "Reset
PLSCNT=1" box in the path from "Protect another sec-
tor?" back to setting up the next sector address.

AC Characteristics

Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations: Corrected the notes refer-
ence for t

WHWH1

and t

WHWH2

. These parameters are

100% tested. Corrected the note reference for t

VCS

This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for t

VIDR

. This parameter is not

100% tested.

Figure 21, Sector Protect/Unprotect Timing
Diagram

A valid address is not required for the first write cycle;
only the data 60h.

Erase and Programming Performance

In Note 2, the worst case endurance is now 1 million cy-
cles.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Part Number Am29LV017B

Document Outline