PRELIMINARY

Publication# 21503

Rev: C Amendment/+1

Issue Date: April 1998

Am29F080B

8 Megabit (1 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

5.0 V

10%, single power supply operation

-- Minimizes system level power requirements

Manufactured on 0.35

µm process technology

-- Compatible with 0.5 µm Am29F080 device

High performance

-- Access times as fast as 70 ns

Low power consumption

-- 25 mA typical active read current

-- 30 mA typical program/erase current

-- 1 µA typical standby current (standard access

time to active mode)

Flexible sector architecture

-- 16 uniform sectors of 64 Kbytes each

-- Any combination of sectors can be erased.

-- Supports full chip erase

-- Group sector protection:

A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group

Temporary Sector Group Unprotect allows code
changes in previously locked sectors

Embedded Algorithms

-- Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

-- Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

Minimum 1,000,000 program/erase cycles per
sector guaranteed

Package options

-- 40-pin TSOP

-- 44-pin SO

Compatible with JEDEC standards

-- Pinout and software compatible with

single-power-supply Flash standard

-- Superior inadvertent write protection

Data# Polling and toggle bits

-- Provides a software method of detecting

program or erase cycle completion

Ready/Busy# output (RY/BY#)

-- Provides a hardware method for detecting

program or erase cycle completion

Erase Suspend/Erase Resume

-- Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector,
then resumes the erase operation

Hardware reset pin (RESET#)

-- Resets internal state machine to the read mode

Am29F080B

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29F080B is an 8 Mbit, 5.0 volt-only Flash mem-
ory organized as 1,048,576 bytes. The 8 bits of data
appear on DQ0DQ7. The Am29F080B is offered in
40-pin TSOP and 44-pin SO packages. This device is
designed to be programmed in-system with the stan-
dard system 5.0 volt V

supply. A 12.0 volt V

is not

required for program or erase operations. The device
can also be programmed in standard EPROM pro-
grammers.

This device is manufactured using AMD's 0.35 µm
process technology, and offers all the features and ben-
efits of the Am29F080, which was manufactured using
0.5 µm process technology.

The standard device offers access times of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to op-
erate without wait states. To eliminate bus contention,
the device has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.

The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically
preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.

The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.

AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t
effectiveness. The device electrically erases all
b i t s w i t h i n a s e c t o r s i m u l t a n e o u s l y v i a
F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s
programmed using hot electron injection.

Am29F080B

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be support-
ed in volume for this device. Consult the local AMD sales of-
fice to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION
Am29F080B
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase

Am29F080B

-75

OPTIONAL PROCESSING
Blank = Standard Processing

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE
C = Commercial (0

C to +70

I = Industrial (40

C to +85

PACKAGE TYPE
E

40-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 040)

40-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR040)

44-Pin Small Outline Package (SO 044)

SPEED OPTION
See Product Selector Guide and Valid Combinations

Valid Combinations

Am29F080B-75

EC, EI, FC, FI, SC, SI

Am29F080B-90

EC, EI, EE,
FC, FI, FE,
SC, SI, SE

Am29F080B-120

Am29F080B-150

Am29F080B

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.

Table 1.

Am29F080B Device Bus Operations

Legend:

L = Logic Low = V

, H = Logic High = V

, D

OUT

= Data Out, D

= Data In, A

= Address In, X = Don't Care. See DC Charac-

teristics for voltage levels.

Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V

The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.

See "Reading Array Data" for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I

CC1

in the DC Characteristics

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

, and OE# to V

An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
"sector address" consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

CC2

in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
tables and timing diagrams for write operations.

Operation

CE#

OE#

WE#

RESET#

A0A19

DQ0

DQ7

Read

OUT

Write

TTL Standby

HIGH Z

CMOS Standby

0.3 V

HIGH Z

Output Disable

HIGH Z

Hardware Reset

HIGH Z

Temporary Sector Group Unprotect (See Note)

Am29F080B

P R E L I M I N A R Y

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7DQ0. Standard read cycle timings and I

read specifications apply. Refer to "Write Operation
Status" for more information, and to each AC Charac-
teristics section in the appropriate data sheet for timing
diagrams.

Standby Mode

When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V

0.5 V. (Note

that this is a more restricted voltage range than V

The device enters the TTL standby mode when CE#
and RESET# pins are both held at V

. The device re-

quires standard access time (t

) for read access when

the device is in either of these standby modes, before it
is ready to read data.

The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, "RE-
SET#: Hardware Reset Pin".

If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.

In the DC Characteristics tables, I

CC3

represents the

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system

drives the RESET# pin low for at least a period of t

the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.

The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.

If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a "0" (busy) until the in-
ternal reset operation is complete, which requires a
time of t

READY

(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is "1"), the reset operation is completed
within a time of t

READY

(not during Embedded Algo-

rithms). The system can read data t

after the RE-

SET# pin returns to V

Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.

Output Disable Mode

When the OE# input is at V

, output from the device is

disabled. The output pins are placed in the high imped-
ance state.

Am29F080B

P R E L I M I N A R Y

Table 2.

Am29F080B Sector Address Table

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don't care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require V

. See

"Command Definitions" for details on using the autose-
lect mode.

Sector

A19

A18

A17

A16

Address Range

SA0

000000h00FFFFh

SA1

010000h01FFFFh

SA2

020000h02FFFFh

SA3

030000h03FFFFh

SA4

040000h04FFFFh

SA5

050000h05FFFFh

SA6

060000h06FFFFh

SA7

070000h07FFFFh

SA8

080000h08FFFFh

SA9

090000h09FFFFh

SA10

0A0000h0AFFFFh

SA11

0B0000h0BFFFFh

SA12

0C0000h0CFFFFh

SA13

0D0000h0DFFFFh

SA14

0E0000h0EFFFFh

SA15

0F0000h0FFFFFh

Am29F080B

P R E L I M I N A R Y

Table 3.

Am29F080B Autoselect Codes (High Voltage Method)

Legend: L = Logic Low = V

, H = Logic High = V

, SGA = Sector Group Address, X = Don't care.

Note: The system may also autoselect information in-system via the command register. See Table 5.

Sector Group Protection/Unprotection

The hardware group sector protection feature dis-
ables both program and erase operations in any sec-
tor group. Each sector group consists of two adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group con-
tains. The hardware sector group unprotection fea-
ture re-enables both program and erase operations in
previously protected sector groups.

Sector group protection/unprotection must be imple-
mented using programming equipment. The procedure
requires a high voltage (V

) on address pin A9 and the

control pins. Details on this method are provided in a
supplement, listed in publication number 19945. Con-
tact an AMD representative to obtain a copy of the ap-
propriate document.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sector groups at its factory prior to shipping the device
through AMD's ExpressFlashTM Service. Contact an
AMD representative for details.

It is possible to determine whether a sector group is
protected or unprotected. See "Autoselect Mode" for
details.

Table 4.

Sector Group Addresses

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to V

. During this mode,

formerly protected sector groups can be programmed
or erased by selecting the sector group addresses.
Once V

is removed from the RESET# pin, all the

p r e v i o u s l y p r o t e c t e d s e c t o r g r o u p s a r e
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram
shows the timing waveforms, for this feature.

Figure 1.

Temporary Sector Group Unprotect

Operation

Description

CE#

OE#

WE#

A19

A12

A11

A10

DQ7

DQ0

Manufacturer ID: AMD

01h

Device ID: Am29F080B

D5h

Sector Group
Protection Verification

SGA

01h (protected)

00h

(unprotected)

Sector

Group

A19

A18

A17

Sectors

SGA0

SA0

SA1

SGA1

SA2

SA3

SGA2

SA4

SA5

SGA3

SA6

SA7

SGA4

SA8

SA9

SGA5

SA10

SA11

SGA6

SA12

SA13

SGA7

SA14

SA15

START

Perform Erase or

Program Operations

RESET# = V

Temporary Sector Group

Unprotect

Completed (Note 2)

RESET# = V

(Note 1)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected

once again.

21503C-6

Am29F080B

P R E L I M I N A R Y

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V

power-up and

power-down transitions, or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V

is greater than V

LKO

. The system must provide the

proper signals to the control pins to prevent uninten-
tional writes when V

is greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =
V

, CE# = V

or WE# = V

. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power up, the

device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.

Am29F080B

P R E L I M I N A R Y

COMMAND DEFINITIONS

Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
"AC Characteristics" section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See "Erase Suspend/
Erase Resume Commands" for more information on
this mode.

The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the "Reset Com-
mand" section, next.

See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.

Reset Command

Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.

The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.

The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command

must

be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires V

on address bit A9.

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is

not required to provide further

controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See "Write Operation Status" for in-
formation on these status bits.

Am29F080B

P R E L I M I N A R Y

Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a "0" back to a "1". Attempting to do so may halt
the operation and set DQ5 to "1", or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0"
to a "1".

Note: See the appropriate Command Definitions table for
program command sequence.

Figure 2.

Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase
algorithm. The device does

not require the system to

preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.

Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.

The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
"Write Operation Status" for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.

Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.

The device does

not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.

After the command sequence is written, a sector erase
time-out of 50

s begins. During the time-out period,

additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50

otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50

s, the

system need not monitor DQ3. Any command other

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21503C-7

Am29F080B

P R E L I M I N A R Y

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer" section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to "Write Operation Status" for informa-
tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the "AC Characteristics" section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50

s time-out period

during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are "don't-cares" when writing the Erase Sus-
pend command.

When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20

s to suspend the erase operation. However,

when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device "erase
suspends" all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See "Write Operation Status" for information on these
status bits.

After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See "Write Operation Status" for more informa-
tion.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See "Autoselect Command Sequence"
for more information.

The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.

Am29F080B

P R E L I M I N A R Y

Table 5.

Am29F080B Command Definitions

Legend:
RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse.

SA = Address of the sector to be erased. Address bits A19A16 uniquely select any sector.

SGA = Address of the sector group to be verified.

Notes:
1. All values are in hexadecimal.

2. See Table 1 for descriptions of bus operations.

3. No unlock or command cycles required when device is in read mode.

4. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high.

5. The data is 00h for an unprotected sector group and 01h for a protected sector group. The complete bus address in the fourth

cycle is composed of the sector group address (A19A17), A1 = 1, and A0 = 0.

6. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command

is valid only during a sector erase operation.

7. The Erase Resume command is valid only during the Erase Suspend mode.

8. Unless otherwise noted, address bits A19A11 are don't care.

Command

Sequence

(Note 1)

Bus Cycles (Notes 25)

First

Second Third Fourth Fifth Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 3)

Reset (Note 4)

XXX

Autoselect
Manufacturer ID

555

2AA

555

X00

Autoselect
Device ID

555

2AA

555

X01

Autoselect
Sector Group
Protect Verify
(Note 5)

555

2AA

555

SGA

X02

Byte Program

555

2AA

555

Chip Erase

555

2AA

555

2AA

555

Sector Erase

555

2AA

555

2AA

Erase Suspend
(Note 6)

XXX

Erase Resume
(Note 7)

XXX

l
es

Am29F080B

P R E L I M I N A R Y

WRITE OPERATION STATUS

The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host
sys tem w he th er a n E m be dd e d Alg or ith m is i n
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.

During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n t h e
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2

s, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling
produces a "0" on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to "1";
prior to this, the device outputs the "complement," or
"0." The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100

s, then the de-

vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the "AC Characteristics" section illustrates this.

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7DQ0

Addr = VA

Read DQ7DQ0

Addr = VA

DQ7 = Data?

START

Notes:
1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = "1" because

DQ7 may change simultaneously with DQ5.

21503C-9

Figure 4.

Data# Polling Algorithm

Am29F080B

P R E L I M I N A R Y

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia-
grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100

s, then returns to reading

array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector,
DQ6 toggles for approximately 2

s after the program

command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
"AC Characteristics" section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The "Toggle Bit II" on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.

Figure 5 shows the toggle bit algorithm in flowchart
form, and the section "DQ2: Toggle Bit II" explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7DQ0 on the following
read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.

Am29F080B

P R E L I M I N A R Y

The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a "1." This is a failure
condition that indicates the program or erase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a "1" to a location that is previously pro-
grammed to "0." Only an erase operation can change
a "0" back to a "1." Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a "1."

Under both these conditions, the system must issue the
reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from "0" to "1." The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50

s. See also the "Sector Erase Command Se-

quence" section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is "1", the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status

check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write
Reset Command

Program/Erase

Operation Complete

Read DQ7DQ0

Toggle Bit

= Toggle?

Read DQ7DQ0

Twice

Read DQ7DQ0

Notes:
1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to "1". See text.

21503C-10

Figure 5.

Toggle Bit Algorithm

(Notes
1, 2)

Note 1

Am29F080B

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65

C to +125

Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 55

C to +125

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . 2.0 V to +7.0 V

A9, OE#, RESET# (Note 2) . . . . 2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . . 2.0 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is 0.5 V. During

voltage transitions, inputs may overshoot V

to 2.0 V

for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on output and I/O pins is V

+ 0.5 V. During

voltage transitions, outputs may overshoot to V

+ 2.0 V

for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9, OE#, RESET# pins is

0.5V. During voltage transitions, A9, OE#, RESET# pins
may overshoot V

to 2.0 V for periods of up to 20 ns.

See Figure 6. Maximum DC input voltage on A9, OE#,
and RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.

3. No more than one output shorted at a time. Duration of

the short circuit should not be greater than one second.

Stresses greater than those listed in this section may cause
permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure of the device to absolute
maximum rating conditions for extended periods may affect de-
vice reliability.

21503-11

Figure 6.

Maximum Negative Overshoot

Waveform

21503-12

Figure 7.

Maximum Negative Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Case Temperature (T

) . . . . . . . . . . . . . 0

C to +70

Industrial (I) Devices

Case Temperature (T

) . . . . . . . . . . . 40

C to +85

Supply Voltages

for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V

for± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

20 ns

+0.8 V

0.5 V

20 ns

2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

Am29F080B

P R E L I M I N A R Y

DC CHARACTERISTICS

TTL/NMOS Compatible

CMOS Compatible

Notes for DC Characteristics (both tables):

1. The I

current listed includes is typically less than 1 mA/MHz, with OE# at V

2. I

active while Embedded Program or Embedded Erase algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol

Parameter Description

Test Description

Min

Typ

Max

Unit

Input Load Current

= V

to V

, V

= V

Max

1.0

µA

LIT

A9 Input Load Current

= V

Max, A9 = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

, V

= V

Max

1.0

µA

CC1

Read Current (Note 1)

CE# = V

IL,

OE# = V

CC2

Write Current (Notes 2, 3)

CE#

IL,

OE#

CC3

Standby Current

(CE# Controlled)

= V

Max, CE# = V

RESET#

0.4

1.0

CC4

Standby Current

(RESET# Controlled)

= V

Max, RESET# = V

0.4

1.0

Input Low Level

0.5

0.8

Input High Level

2.0

+ 0.5

Voltage for Autoselect and Sector
Protect

= 5.0 V

11.5

12.5

Output Low Voltage

= 12 mA, V

= V

Min

0.45

Output High Level

= 2.5 mA V

= V

Min

2.4

LKO

Low V

Lock-out Voltage

3.2

4.2

Parameter

Symbol

Parameter Description

Test Description

Min

Typ

Max

Unit

Input Load Current

= V

to V

, V

= V

Max

1.0

µA

LIT

A9 Input Load Current

= V

Max, A9 = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

, V

= V

Max

1.0

µA

CC1

Read Current (Note 1)

CE# = V

IL,

OE# = V

CC2

Write Current (Notes 2, 3)

CE#

= V

IL,

OE#

= V

CC3

Standby Current

(CE# Controlled)

Max,

CE#

0.3 V,

RESET#

0.3 V

µA

CC4

Standby Current

(RESET# Controlled)

= V

Max,

RESET# = V

0.3 V

µA

Input Low Level

0.5

0.8

Input High Level

0.7x V

+ 0.3

Voltage for Autoselect
and Sector Protect

= 5.0 V

11.5

12.5

Output Low Voltage

= 12 mA, V

= V

Min

0.45

OH1

Output High Voltage

= 2.5 mA, V

= V

Min

0.85 V

OH2

= 100 µA, V

= V

Min

0.4

LKO

Low V

Lock-out Voltage

3.2

4.2

Am29F080B

P R E L I M I N A R Y

AC CHARACTERISTICS

Read-only Operations

Notes:
1. Not 100% tested.

2. Refer to Figure 8 and Table 7 for test specifications.

Parameter Symbol

Parameter Description

Test

Setup

Speed Options

Unit

JEDEC Standard

-75

-90

-120

-150

AVAV

Read Cycle Time (Note 1)

Min

120

150

AVQV

ACC

Address to Output Delay

CE# = V

OE# = V

Max

120

150

ELQV

Chip Enable to Output Delay

OE# = V

Max

120

150

GLQV

Output Enable to Output Delay

Max

OEH

Output Enable Hold
Time (Note 1)

Read

Min

Toggle and
Data# Polling

Min

EHQZ

Chip Enable to Output High Z

Max

GHQZ

Output Enable to Output High Z

Max

AXQX

Output Hold Time From Addresses CE#

OE# Whichever Occurs First

Min

Ready

RESET# Pin Low to Read Mode
(Note 1)

Max

µs

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

ACC

OEH

0 V

RY/BY#

RESET#

21503C-14

Figure 9.

Read Operation Timings

Am29F080B

P R E L I M I N A R Y

AC CHARACTERISTICS

Erase and Program Operations

Notes:
1. Not 100% tested.

2. See the "Erase And Programming Performance" section for more information.

Parameter

Parameter Description

Speed Options

Unit

JEDEC Std.

-75

-90

-120

-150

AVAV

Write Cycle Time (Note 1)

Min

120

150

AVWL

Address Setup Time

Min

WLAX

Address Hold Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

OES

Output Enable Setup Time

Min

GHWL

Read Recover Time Before Write
(OE# high to WE# low)

Min

ELWL

CE# Setup Time

Min

WHEH

CE# Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse Width High

Min

WHWH1

Byte Programming Operation (Note 2)

Typ

µs

WHWH2

Sector Erase Operation (Note 2)

Typ

sec

VCS

Set Up Time (Note 1)

Min

µs

BUSY

WE# to RY/BY# Valid

Min

Am29F080B

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Notes:
1. Typical program and erase times assume the following conditions: 25

C, 5.0 V V

, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V (4.75 for -75), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further

information on command definitions.

6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 1,000,000 cycles are guaranteed.

LATCHUP CHARACTERISTIC

Includes all pins except V

. Test conditions: V

= 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:
1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

sec

Excludes 00h programming prior to
erasure (Note 4)

Chip Erase Time

128

sec

Byte Programming Time

300

µs

Excludes system-level overhead
(Note 5)

Chip Programming Time (Note 3)

7.2

21.6

sec

Min

Max

Input Voltage with respect to V

on I/O pins

1.0 V

+ 1.0 V

Current

100 mA

+100 mA

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Input Capacitance

= 0

7.5

OUT

Output Capacitance

OUT

= 0

8.5

IN2

Control Pin Capacitance

= 0

7.5

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

Years

125

Years

Am29F080B

P R E L I M I N A R Y

REVISION SUMMARY FOR AM29F080B

Revision B

Global

Formatted for consistency with other 5.0 volt-only data
sheets.

Figure 9, Read Operation Timings

Corrected RESET# waveform so that it is high for the
duration of the read cycle.

Figure 11, Chip/Sector Erase Operation Timings

Corrected data unlock cycle in diagram to 55h.

Figure 17, Alternate CE# Controlled Program
Operation Timings

Corrected command for sector erase to 30h, chip erase
to 10h.

Revision C

Standby Mode

Removed sentence in first paragraph referring to RE-
SET# pulse.

Sector Group Protection/Unprotection, Temporary
Sector Group Unprotect

Changed references from "sector" to "sector group".
Corrected text to indicate sector groups are composed
of two adjacent sectors.

Revision C+1

Distinctive Characteristics

Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.

AC Characteristics

Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for t

WHWH1

and t

WHWH2

. These param-

eters are 100% tested. Corrected the note reference for
t

VCS

. This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for t

VIDR

. This parameter is not

100% tested.

Command Definitions

Corrected the shift in the table header.

Erase and Programming Performance

Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Part Number Am29F080B

Document Outline