Altera Corporation

a8259

Programmable

Interrupt Controller

July 1997, ver. 1

Data Sheet

A-DS-A8259-01

Features

Optimized for FLEX

and MAX

architectures

Offers eight levels of individually maskable interrupts

Expandable to 64 interrupts

Offers a flexible priority resolution scheme

Provides programmable interrupt modes and vectors

Uses approximately 399 logic elements (LEs) in FLEX devices

Functionally based on the Intel 8259 device, except as noted in the

"Variations & Clarifications" section on page 79

General
Description

The Altera

a8259

MegaCore

function is a programmable interrupt

controller. The

a8259

can be initialized by the microprocessor through

eight data bus lines (

din[7..0]

and

dout[7..0]

), and the

ncs

nrd

nwr

int

, and

ninta

control signals.

Figure 1

shows the symbol for the

a8259

Figure 1. a8259 Symbol

A8259

nEN

DOUT[7..0]

CASOUT[2..0]

CAS_EN

INT

nMRST

CLK

nCS

nWR

nRD

CASIN[2..0]

nSP

nINTA

IR[7..0]
DIN[7..0]

Altera Corporation

a8259 Programmable Interrupt Controller Data Sheet

Table 1

describes the input and output ports of the

a8259

Note:

(1)

The interrupt request signals can be set as active high or positive-edge-triggered via bit 3 of Initialization Command
Word (ICW) 1 (see

"ICW 1" on page 62

for more information).

Table 1. a8259 Ports

Name

Type

Polarity

Description

nmrst

Input

Low

Master reset. When

nmrst

is asserted, all internal registers assume their

default state. The

a8259

is idle, awaiting initialization.

clk

Input

Clock. All registers are clocked on the positive edge of the clock.

ncs

Input

Low

Chip select. When low, this signal enables the

nwr

and

nrd

signals and

a8259

nwr

Input

Low

Write control. When this signal is low (and

ncs

signal is also low), it enables

write transactions to the

a8259

nrd

Input

Low

Read control. When this signal is low (and

ncs

signal is also low), it enables

read transactions from the

a8259

Input

High

Address. This signal serves as a register selector when writing to and
reading from internal

a8259

registers.

ninta

Input

Low

Interrupt acknowledge. This signal serves as the primary handshake
between the

a8259

and microprocessor during an interrupt service cycle.

nsp

Input

Low

Slave processor. This signal indicates that the

a8259

should be configured

as a slave. However, this signal is ignored when the

a8259

is configured

as a single device. This signal should also be ignored in buffered mode.

casin[2..0]

Input

High

Cascade data bus. These bus signals act as a cascade mode control to a
slave

a8259

. If the

a8259

is configured as a master, the bus should be

driven low.

ir[7..0]

Inputs

High

(1)

Interrupt request. These are eight maskable, prioritized interrupt service
request signals.

din[7..0]

Input

Data bus. This bus inputs data when writing to internal

a8259

registers.

int

Output

High

Interrupt. This signal indicates that the

a8259

has made an unmasked

service request.

casout[2..0]

Output

High

Cascade data bus. These bus signals act as cascade mode control, and
should be connected to the

casin[2..0]

bus of a slave

a8259

. When

the

a8259

is configured as a master, the

casout[2..0]

bus is ignored.

cas_en

Output

High

Cascade directional bus enable. This signal is intended as a tri-state enable
signal to external bidirectional I/O buffers on the cascade control bus.

dout[7..0]

Output

Data bus. The output data when reading from internal

a8259

registers.

nen

Output

Low

Data enable. This signal indicates that a read cycle is being performed on
an internal

a8259

external bidirectional I/O buffers.

Altera Corporation

a8259 Programmable Interrupt Controller Data Sheet

Functional
Description

Figure 2

shows the

a8259

block diagram.

Figure 2. a8259 Block Diagram

The

int

and

ninta

signals provide the handshaking mechanism for the

a8259

to signal the microprocessor. The

a8259

requests service via the

int

signal and receives an acknowledgment of acceptance from the

microprocessor via the

ninta

signal. The

int

signal is applied directly to

the microprocessor's interrupt input. Whenever the

a8259

receives a

valid interrupt request on an

pin (

ir1

through

ir7

), the

int

signal

goes high.

The

ninta

input is connected to the microprocessor's interrupt

acknowledgment signal. The microprocessor pulses the

ninta

signal

twice during the interrupt acknowledgment cycle, which tells the

a8259

that the interrupt request has been acknowledged. Then, the

a8259

sends

the highest priority active interrupt type number onto the

din[7..0]

bus for the microprocessor to acknowledge.

The

inputs are used by external devices to request service, and they can

be configured for level-sensitive or edge-sensitive operation.

Interrupt
Request
Register

Interrupt

Control

Logic

Read/Write

Control Logic

& Initialization/

Command

Registers

Priority

Resolution

In-Service

Interrupt Vector

ir[7..0]

ninta

nsp

casin[2..0]

clk

nmrst

nrd

nwr

ncs

din[7..0]

int

nen

cas_en

cas_out[2..0]

dout[7..0]

60 Altera Corporation

a8259 Programmable Interrupt Controller Data Sheet

The

casin[2..0]

and

casout[2..0]

buses, and

nsp

and

cas_en

pins

are used to implement the cascade interface. These pins are used when
more than one

a8259

functions are interconnected in a master/slave

configuration, expanding the number of interrupts from 8 up to 64.

Programming
& Initialization

The

a8259

operation depends on initial programming. Two types of

command words are used for programming the

a8259

: initialization

command words (ICWs) and operation command words (OCWs). ICWs
are used to load the

a8259

internal control registers, while the OCWs

permit the microprocessor to initiate variations in the basic operating
modes defined by the ICW registers.

Table 2

summarizes how to access

the ICW and OCW registers for programming and initialization (for more
information on ICW and OCW registers, see

"Register Descriptions" on

page 62

Note:
(1) "Don't Care" indicates that the bit has no address significance for this register access method. However, the bit will

usually have data significance.

To begin an initialization sequence, the

pin must be low, and bit 4 of

the

din[7..0]

bus must be high during a valid write cycle.

Figure 3

shows the

a8259

initialization sequence flow diagram.

Table 2. ICW & OCW Register Access for Programming & Initialization

Note (1)

Register Mnemonics Description Access Method

A0 D4 D3

ICW 1 0 1 Don't Care A write with A0 low and D4 high is

interpreted as the beginning of an
initialization sequence.

Sequential access
which starts with ICW 1
and timed by the pulsing

nwr

signal.

ICW 2 1 Don't Care Don't Care This register always follows ICW 1.

ICW 3 1 Don't Care Don't Care The use of this register depends on

the value of SINGLE (see

Figure 3

page 61

ICW 4 1 Don't Care Don't Care The use of this register depends on

the value of IC4 (see

Figure 3

page 61

OCW 1 1 Don't Care Don't Care These registers can be accessed

randomly (see

"Operation Command

Word Registers" on page 65

for

more details).

Random access

OCW 2 0 0 0

OCW 3 0 0 1

Altera Corporation

a8259 Programmable Interrupt Controller Data Sheet

Figure 3. a8259 Initialization Sequence Flow Diagram

Figures 4

and

show typical write and read cycles, respectively. The

ncs

nwr

, and

nrd

signals enable data to be written to and read from the

a8259

. This data is clocked by the rising edge of

clk

. The

ncs

and

nwr

signals must be held low for an entire clock cycle in order to read or write
valid data.

Figure 4. Typical Write Cycle

X indicates "don't care." DV indicates "data valid."

ICW 1

ICW 2

ICW 3

ICW 4

Ready to

interrupts

Is SINGLE

low?

Note (1)

IC4

high?

Note (1)

Yes

Note:

(1) For more information on SINGLE and IC4, see Table 3 on page 62.

clk

nwr

ncs

din[7..0]

Part Number A8259

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