®
Altera Corporation
45
a8255
Programmable Peripheral
Interface Adapter
September 1996, ver. 1
A-DS-A8255-01
Features
s
a8255
MegaCore function implementing a programmable
peripheral interface adapter
s
Optimized for FLEX
®
and MAX
®
architectures
s
24 programmable inputs/outputs
s
Static read/write or handshaking modes
s
Direct bit set/reset capability
s
Synchronous design
s
Uses approximately 194 FLEX logic elements (LEs)
s
Functionally based on the Intel 8255A and Harris 82C55A devices,
except as noted in the
"Variations & Clarifications" section on
page 56
General
Description
The
a8255
MegaCore function implements a programmable peripheral
interface adapter (see
Figure 1
). The
a8255
has 24 I/O signals that can be
programmed in two groups of 12. This MegaCore function operates in the
following three modes:
s
Mode 0: Basic Input/Output
--Port A, port B, and port C (upper and
lower) can be independently configured as inputs or outputs to read
or hold static data. Outputs are registered; inputs are not registered.
s
Mode 1: Strobed Input/Output
--Port A and port B can be
independently configured as strobed input or output buses. Signals
from port C are dedicated as control signals for data handshaking.
s
Mode 2: Bidirectional Bus
--Port A can be configured as a bidirectional
bus with the majority of port C providing the control signals. In this
configuration, port B can still implement mode 0 or mode 1.
Figure 1. a8255 Symbol
PAEN
PBEN
DOUT[7..0]
PAOUT[7..0]
PBOUT[7..0]
PCEN[7..0]
PCOUT[7..0]
A8255
CLK
nCS
nRD
nWR
RESET
A[1..0]
DIN[7..0]
PAin[7..0]
PBin[7..0]
PCin[7..0]
46
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table 1
describes the input and output ports of the
a8255
.
Table 1. a8255 Ports
Name
Type
Polarity
Description
clk
Input
Clock.
ncs
Input
Low
Chip select. When
ncs
is asserted, the
a8255
is selected and read
and write transactions to internal registers are possible.
nrd
Input
Low
Read control. When
nrd
is asserted and the
a8255
is selected, read
transactions from internal registers are possible.
nwr
Input
Low
Write control. When
nwr
is asserted and the
a8255
is selected, write
transactions to internal registers are possible.
reset
Input
High
Reset. Initializes the control and port C output registers, and sets the
port A, B, and C registers to input mode.
a[1..0]
Input
High
Register address bus. This bus selects one of the internal registers.
din[7..0]
Input
High
Data input bus. The CPU writes data to the internal control, port A,
port B, or port C register via the
din[7..0]
bus.
pain[7..0]
Input
High
Port A input data bus.
pbin[7..0]
Input
High
Port B input data bus.
pcin[7..0]
Input
High
Port C input data bus.
paen
Output
High
Port A data enable. Output enable for the port A output data bus.
pben
Output
High
Port B data enable. Output enable for the port B output data bus.
dout[7..0]
Output
High
Data output bus. The CPU reads data from the internal control,
port A, port B, or port C register via the
dout[7..0]
bus.
paout[7..0]
Output
High
Port A output data bus.
pbout[7..0]
Output
High
Port B output data bus.
pcen[7..0]
Output
High
Port C data enable bus. Output enable for each bit of the port C
output data bus.
pcout[7..0]
Output
High
Port C output data bus.
Altera Corporation
47
a8255 Programmable Peripheral Interface Adapter Data Sheet
Functional
Description
Figure 2
shows a block diagram of the
a8255
.
Figure 2. a8255 Block Diagram
Data Output Select
Control Register Data
Port A
Output Register
Control Register
& Logic
reset
ncs
nrd
nwr
a[1..0]
din[7..0]
Data Output
Multiplexer
paen
pben
pcen[7..0]
dout[7..0]
Port A
Input Register
Port C
Output Register
& Control
Port B
Input Register
Port B
Output Register
Port Control Bus
paout[7..0]
pain[7..0]
pbout[7..0]
pbin[7..0]
pcout[7..0]
pcin[7..0]
Port C Status
48
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Register Address Map
Table 2
shows the register address map for the
a8255
.
Registers
This section describes the following
a8255
registers:
s
Control
s
Port A, B & C
Control Register
The control register sets the mode and signal direction for the three 8-bit
I/O ports. Control of the I/O ports is split into two groups. Group A
consists of port A and the upper four bits of port C; group B consists of
port B and the lower four bits of port C. Group A can be set to mode 0,
mode 1, or mode 2, but group B can be set to only mode 0 or mode 1.
Writing to the control register address with bit 7 set is the mode definition
format, which allows control of the mode and direction of the three I/O
ports (see
Table 3
). Writing to the control register address with bit 7 reset
is the port C bit set/reset format, which allows single-bit control of port C
(see
Table 4
). The CPU reads the control register using the mode
definition format.
Table 2. Register Address Map
a1
a0
Register
0
0
Port A data (all modes)
0
1
Port B data (all modes)
1
0
Port C data (mode 0) and status (modes 1 and 2)
1
1
Control register mode definition and port C bit set/reset
Altera Corporation
49
a8255 Programmable Peripheral Interface Adapter Data Sheet
Note:
(1)
The X indicates "don't care."
Notes:
(1)
For example, to reset bit 3 of port C, bit 7 is reset to indicate that the write is in the
port C bit set/reset format. Bits 6 through 4 are "don't care." Bits 3 through 1 are
011 to address bit 3, and bit 0 is 0 to indicate a reset operation. The complete data
word is 0XXX0110.
(2)
The X indicates "don't care."
Table 3. Control Register Mode Definition Format
Bit
Description
0
Port C (lower) I/O direction:
1 = input
0 = output
1
Port B I/O direction:
1 = input
0 = output
2
Group B mode select:
1 = mode 1
0 = mode 0
3
Port C (upper) I/O direction:
1 = input
0 = output
4
Port A I/O direction:
1 = input
0 = output
6..5
Group A mode select:
00 = mode 0
01 = mode 1
1X = mode 2,
Note (1)
7
1 when writing = mode definition format
Always 1 when reading the control register
Table 4. Port C Bit Set/Reset Format
Note (1)
Bit
Description
0
Bit set/reset:
1 = set
0 = reset
3..1
Bit select address
6..4
XXX,
Note (2)
7
0 when writing = port C bit set/reset format
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