August
2004
ASM4SSTVF32852
rev 2.0
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
DDR 24-Bit to 48-Bit Registered Buffer
Features
Differential clock signals.
Supports SSTL_2 class II specifications on
inputs and outputs.
Low voltage operation.
V
DD
= 2.3V to 2.7V.
Available in 114 ball BGA package.
Industrial temperature range also available.
Product Description
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal
bus driver designed for 2.3V to 2.7V V
DD
operation and
SSTL_2 I/O levels except for the LVCMOS RESETB
input.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow,
and CLKB is used to maintain sufficient noise margins,
whereas the RESETB, an LVCMOS asynchronous
signal is intended for use at the time of power-up only.
The ASM4SSTVF32852 supports a low power standby
mode of operation. A logic
"Low" level at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic "Low" state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Please note that RESETB must always be
supported with a LVCMOS levels at a valid logic state
since VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state
before a stable clock has been supplied, RESETB must
be held at a logic "Low" level during power-up.
In the DDR DIMM application, RESETB is specified to
be asynchronous with respect to CLK/CLKB. Therefore,
no timing relationship can be guaranteed between the
two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be
driven to a logic "Low" level quickly relative to the time
to disable the differential input receivers. This ensures
there are no "glitches" on any output. However, when
coming out of low power standby state, the register will
become active quickly relative to the time taken to
enable the differential input receivers. When the data
inputs are at a logic level "Low" and the clock is stable
during the "Low-to-High" transition of RESETB until the
input receivers are fully enabled, the design ensures
that the outputs will remain at a logic "Low" level.
Applications
DDR Memory Modules.
Provides complete DDR DIMM logic solution
with ASM5CVF857, ASM4SSTVF16857 and
ASM4SSTVF16859.
SSTL_2 compatible data registers.
August
2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
2 of 13
Block Diagram
Pin Configurations
114-Pin Ball BGA
Q1B
Q1A
CLK
CLK
RESETB
D1
VREF
R
CLKB
D1
To 23 Other Channels
B
C
D
E
F
G
H
J
K
R
T
U
P
N
M
A
L
V
W
1
2
3
4
5
6
August
2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
3 of 13
Pin Description
Pin #
Pin Name
Type
Description
R1, P1, N1, N2, M1, L2, L1, K1, K2, J2, J1, H1,
G1, G2, F1, F2, E1, D1, D2, C1, C2, B1, A1, A2
Q (24:1)A
O
Data output.
R6, P6, N6,N5,M6, L5, L6, K6, K5, J5, J6, H6, G6,
G5, F6, F5, E6, D6, D5, C6, C5, B6, A6, A5
Q (24:1)B
O
Data output.
E2, B3, D3, G3, J3, L3, M3, P3, B4, D4, G4, J4,
L4, M4, P4, E5
GND
P
Ground.
B2, M2, P2, C3, E3, F3, H3, K3, N3, C4, E4, F4,
H4, K4, N4, B5, M5, P5
VDDQ
P
Output supply voltage, 2,5V nominal.
W4, V4, U4, W5, W6, V5, T4, V6, U6, U5, T6, T5,
W3, V3, U3, W2, W1, V2, T3, V1, U1, U2, T1, T2
D(24:1)
I
Data input.
A3
CLK
I
Positive master clock input.
A4
CLKB
I
Negative master clock input.
H2, H5, R2, R5
VDD
P
Core supply voltage, 2.5V nominal.
R3
RESETB
I
Reset (Active Low).
R4
VREF
I
Input reference, 1.25V nominal.
August
2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
4 of 13
Pin Configuration Assignments
1
2
3
4
5
6
A
Q2A
Q1A
CLK
CLKB
Q1B
Q2B
B
Q3A
VDDQ
GND
GND
VDDQ
Q3B
C
Q5A
Q4A
VDDQ
VDDQ
Q4B
Q5B
D
Q7A
Q6A
GND
GND
Q6B
Q7B
E
Q8A
GND
VDDQ
VDDQ
GND
Q8B
F
Q10A
Q9A
VDDQ
VDDQ
Q9B
Q10B
G
Q12A
Q11A
GND
GND
Q11B
Q12B
H
Q13A
VDD
VDDQ
VDDQ
VDD
Q13B
J
Q14A
Q15A
GND
GND
Q15B
Q14B
K
Q17A
Q16A
VDDQ
VDDQ
Q16B
Q17B
L
Q18A
Q19A
GND
GND
Q19B
Q18B
M
Q20A
VDDQ
GND
GND
VDDQ
Q20B
N
Q22A
Q21A
VDDQ
VDDQ
Q21B
Q22B
P
Q23A
VDDQ
GND
GND
VDDQ
Q23B
R
Q24A
VDD
RESETB
VREF
VDD
Q24B
T
D2
D1
D6
D18
D13
D14
U
D4
D3
D10
D22
D15
D16
V
D5
D7
D11
D23
D19
D17
W
D8
D9
D12
D24
D21
D20
August
2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
5 of 13
Truth Table
1
Inputs
Q Outputs
RESET#
CLK
CLK#
D
Q
L
X or floating
X or floating
X or floating
L
H
H
H
H
L
L
H
L or H
L or H
X
Q
0
2
Note: 1. H=High signal level, L=Low signal level,
= transition from low to high,
= transition from high to low, X = don't care 2.
Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Storage Temperature
-65
+150
°C
Supply Voltage
-0.5
3.6
V
Input Voltage
1
-0.5
V
DD
+ 0.5
V
Output Voltage
1,2
-0.5
V
DD
+ 0.5
V
Input Clamp Current
± 50
mA
Output Clamp Current
±50
mA
Continuous Output Current
±50
mA
VDD, VDDQ or GND current/pin
100
mA
Package Thermal Impedance
3
55
°C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
0
> V
DDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged
periods can affect device reliability.
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