Data Sheet

29319.32

3971

DUAL DMOS

FULL-BRIDGE DRIVER

Designed to interface between external PWM control logic and

inductive loads such as relays, solenoids, dc motors, or stepper motors,
each full bridge can operate with output currents to

ą2.5 A and operating

voltages to 50 V.

Low r

DS(on)

DMOS output drivers provide low power dissipation

during PWM operation. Internal charge pump circuitry is used to create
a boosted voltage to fully enhance the high-side DMOS switches.

Three TTL-compatible logic-input terminals per bridge allow flex-

ibility in configuring PWM control.

Internal circuit protection includes thermal shutdown with hysteresis,

and crossover-current protection. Special power -up sequencing is not
required.

The A3971SLB is supplied in a 24-lead plastic SOIC with a copper

batwing tab. The power tab is at ground potential and needs no electri-
cal isolation.

FEATURES

I ą2.5 A Load Current Capability per Bridge
I Parallel Outputs for 5 A Load-Current Capability
I Low r

DS(on)

Outputs

Typically 325 m

source, 175 m sink

I Synchronous Rectification via Control Logic
I Internal Undervoltage Monitor
I Crossover-Current Protection
I Source Connections for External Current Sensing
I Thermal Shutdown Circuitry

ADVANCE INFORMATION

(Subject to change without notice)

May 2, 2000

ABSOLUTE MAXIMUM RATINGS

at TA = +25°C

Load Supply Voltage, V

................ 50 V

Output Current, I

OUT

Transient (<500 ns) ...................

ą5 A

Logic Supply Voltage,

............................................ 7.0 V

Sense Voltage, V

SENSE

...................... 0.5 V

Logic Input Voltage Range,

.................. -0.3 V to V

+ 0.3 V

High-Side Gate Voltage ........... V

+ 8 V

Package Power Dissipation,

............................................. 2.2 W

Operating Temperature Range,

............................. -20

°C to +85°C

Junction Temperature, T

............. +150

°C

Storage Temperature Range,

........................... -55

°C to +150°C

Output duty cycle, ambient temperature, and
heat sinking may limit current rating. Under
any set of conditions, do not exceed the
specified current rating or a junction tempera-
ture of 150

°C.

Always order by complete part number: A3971SLB .

LOGIC

CHARGE PUMP

GROUND

PWM

OUT

LOAD
SUPPLY

SENSE

OUT

CP2

Dwg. PP-069-2

GROUND

CONNECTION

LOGIC

GROUND

OUT

PWM

CP1

SENSE

LOAD

SUPPLY

LOGIC
SUPPLY

BB2

BB1

3971
DUAL DMOS
FULL-BRIDGE DRIVER

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

FUNCTIONAL BLOCK DIAGRAM

BRIDGE 1

CONTROL

LOGIC

VOLTAGE

REFERENCE

UVLO &

THERMAL

SHUTDOWN

OUT

SENSE

GATE

DRIVE

CHARGE PUMP

CP1

CP2

BB2

OUT

0.22

ľF/100 V

DMOS H-BRIDGE

0.22

ľF

50 V

OUT

BB1

OUT

DMOS H-BRIDGE

SENSE

GROUND

PWM

REF

LOW SIDE SUPPLY

BRIDGE 2

CONTROL

LOGIC

LGND

(OPTIONAL)

LOAD

SUPPLY

, C

LOGIC

SUPPLY

Dwg. FP-050

18 19

3971

DUAL DMOS

FULL-BRIDGE DRIVER

www.allegromicro.com

ELECTRICAL CHARACTERISTICS at T

= +25

C, V

= 50 V, V

= 5.0 V (unless otherwise noted).

Limits

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Load Supply Voltage Range

Operating

Logic Supply Voltage Range

Operating

4.5

5.0

5.5

Load Supply Current

Operating, each supply, no load

3.0

Logic Supply Current

Operating

5.0

Output Drivers

Output Leakage Current

DSS

OUT

= V

<1.0

ľA

OUT

= 0 V

<-1.0

-20

Output ON Resistance

DS(on)

High-side switch, I

OUT

= -2.5 A

325

375

Low-side switch, I

OUT

= 2.5 A

175

200

Body Diode Forward Voltage

Source diode, I

= 2.5 A

1.2

Sink diode, I

= 2.5 A

1.0

High-Side Gate Voltage

C = 0.22

ľF, reference V

6.0

6.5

7.0

Control Logic

Logic Input Voltage

IN(0)

0.8

IN(1)

2.0

Logic Input Current

IN(0)

= 0 V

<1.0

-5.0

ľA

IN(1)

= 5.0 V

ľA

Propagation Delay Time

50% to 90%:

PWM change to source off

PWM change to sink off

PWM change to source on

565

PWM change to sink on

665

Disable to source on

150

Disable to sink on

250

Thermal Shutdown Temperature

165

°C

Thermal Shutdown Hysteresis

°C

UVLO Threshold

UVLO

Increasing V

3.9

4.15

4.4

UVLO Hysteresis

UVLO

0.15

NOTES:

1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.

3971
DUAL DMOS
FULL-BRIDGE DRIVER

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

Logic Truth Table

PWM

OUT

Function

Disable

Forward

Reverse

Synchronous

Rectification/

Slow Decay

Chop

Terminal List

Terminal

Name

Description

No (Internal) connection

LGND

Logic ground

Control input, bridge 1

OUT

Output A, bridge 1

BB1

Load supply voltage, bridge 1

6, 7

GND

Ground

SENSE

Sense resistor, bridge 1

OUT

Output B, bridge 1

Control input, bridge 1

PWM

Control input, bridge 1

CP1

Charge-pump capacitor

CP2

Charge-pump capacitor

Reservoir capacitor

Control input, bridge 2

OUT

Output B, bridge 2

SENSE

Sense resistor, bridge 2

18, 19

GND

Ground

BB2

Load supply voltage, bridge 2

OUT

Output A, bridge 2

Control input, bridge 2

PWM

Control input, bridge 2

Logic supply voltage

3971

DUAL DMOS

FULL-BRIDGE DRIVER

www.allegromicro.com

Charge Pump. The DMOS output stage requires a
charge pump to bring the high-side gate-source voltage
approximately 8 V above the V

supply. Two external

components are required, a pumping capacitor connected
between CP1 and CP2 and a reservoir capacitor connected
between V

and V

. Ceramic 0.22

ľF capacitors are

recommended.

Control Logic. Each bridge is controlled by three TTL-
compatible inputs. The inputs are resistively pulled to
ground (via 250 k

). A crossover-delay circuit protects

the outputs from a shoot-thru condition when going from a
forward or reverse on state to synchronous rectification/
slow decay chop (both sink drivers on). If the logic is in
the DISABLE state and changes to an on state the 415 ns
crossover delay does not occur.

Protection Circuitry. In the event of a fault due to
excessive junction temperature, or low voltage on V

, the outputs of the device are disabled until the fault

condition is removed.

Current Sensing. If external current-sensing circuitry
is used, the sense resistor should have an independent
ground return to the ground terminal of the device. Due to
current transients during switching, a 0.1

ľF capacitor

should be connected from the sense terminal to the
batwing tab connection of the package. This capacitor
reduces voltage swings at the terminal due to the fast di/dt,
which in turn ensures that the sink driver gate-source
voltage stays within the safe operating area. Allegro
MicroSystems recommends a value of R

given by:

= 0.5/I

TRIP

max.

Thermal protection. Circuitry turns off all drivers
when the junction temperature reaches 165

°C, typically.

It is intended only to protect the device from failures due
to excessive junction temperatures and should not imply
that output short circuits are permitted. Thermal shut-
down has a hysteresis of approximately 15

°C.

Layout. The printed wiring board should use a heavy
ground plane. For optimum electrical and thermal perfor-
mance, the driver should be soldered directly onto the
board. If external current sensing is used, the ground side
of R

should have an individual path to the ground

terminal(s) of the device. This path should be as short as
is possible physically and should not have any other
components connected to it. The load supply terminal
should be decoupled with an electrolytic capacitor
( >47

ľF is recommended) placed as close to the device as

is possible.

Parallel Operation. For high-power applications, the
two DMOS full bridges in the A3971 may be connected in
parallel as shown below. The current will be shared
equally in each full bridge due to the positive temperature
coefficient of the DMOS

DS(on)

Functional Description

Dwg. EP-069

PWM

CONTROL

+5 V

1550 V

47 ľF

0.22 ľF

47 ľF

1550 V

LOGIC

CHARGE PUMP

BB2

BB1

Part Number 3971