ASAHI KASEI
[AKD5385A]
<KM072400>
2003/07
- 1 -
GENERAL DESCRIPTION
AKD5385A is an evaluation board for the digital audio 24bit 192kHz A/D converter, AK5385A. The
AKD5385A includes the input circuit and also has a digital interface transmitter. Further, the AKD5385A
can achieve the interface with digital audio systems via opt-connector.
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Ordering guide
AKD5385A --- Evaluation board for AK5385A
FUNCTION
·
DIT with optical output
·
BNC connector for an external clock input
AVDD
DVDD
AGND
DGND
LIN
RIN
AK4103
(DIT)
Clock
Generator
DSP Data
10pin Header
AK5385A
Opt
Out
Input
Buffer
+15V
-15V
5V
Regulator
Figure 1. AKD5385A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Evaluation board Rev.A for AK5385A
AKD5385A
ASAHI KASEI
[AKD5385A]
<KM072400>
2003/07
- 2 -
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Operation sequence
1) Set up the power supplies lines.
[AVDD] (red) = 4.75
5.25V : for AVDD of AK5385A (typ. 5.0V)
[DVDD] (red) = 3.0
5.25V : for DVDD of AK5385A (typ. 3.3V)
[+15V] (green) = +15V : for Op-amp
[
-
15V] (blue) =
-
15V : for Op-amp
[VCC] (red) = 5V : for logic
[AGND] (black) = 0V : for analog ground
[DGND] (black) = 0V : for logic ground
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches.
(See the followings.)
3) Power on.
The AK5385A and AK4103 should be reset once bringing SW1 = "L" upon power-up.
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Evaluation mode
(1) Slave Mode
(1-1) A/D evaluation using DIT function of AK4103
PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through
optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the
digital-amplifier which equips DIR input. Nothing should be connected to PORT2 (DSP). In case of using
external clock through a BNC connector (J3), select EXT on JP8 (CLK) and short JP5 (XTE) and open JP10
(EXT).
JP8
CLK
JP3
LRCK
JP4
BICK
JP5
XTE
JP10
EXT
XTL
EXT
(1-2) Feeding all clocks from PORT2 (DSP)
Under the following set-up, all external clocks (MCLK, BICK, LRCK) can be fed through PORT2 (DSP). The
A/D converted data is output from SDTO of PORT2 (DSP). Also, the A/D converted data is output through
optical connector (TOTX176).
JP8
CLK
JP3
LRCK
JP4
BICK
JP5
XTE
JP10
EXT
XTL
EXT
ASAHI KASEI
[AKD5385A]
<KM072400>
2003/07
- 3 -
(2) Master Mode
(2-1) A/D evaluation using DIT function of AK4103
PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through
optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the
digital-amplifier which equips DIR input. Nothing should be connected to PORT2 (DSP). In case of using
external clock through a BNC connector (J3), select EXT on JP8 (CLK) and short JP5 (XTE) and open JP10
(EXT).
JP8
CLK
JP3
LRCK
JP4
BICK
JP5
XTE
JP10
EXT
XTL
EXT
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Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT : Common. (The connector "DGND" can be open.) <Default>
2. JP2 (AVDD) : Select AVDD for AK5385A
AVDD : Supply from AVDD connector <Default>
REG : Supply from regulator. AVDD connector should be supplied +15V.
3. JP6 (BCFS) : Select BICK frequency
256 : In case of MCLK=256fs/512fs <Default>
384 : In case of MCLK=128fs/384fs
4. JP7 (MCLK) : Supply MCLK frequency for 74HC4040
256 : In case of MCLK=128fs/256fs
512 : In case of MCLK=512fs <Default>
384/768 : In case of MCLK=384fs
5. JP9 (LRFS) : Select LRCK frequency
256 : In case of MCLK=256fs/512fs <Default>
384 : In case of MCLK=128fs/384fs
ASAHI KASEI
[AKD5385A]
<KM072400>
2003/07
- 5 -
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DIP Switch set up
[SW2] (MODE): Setting the evaluation mode for AK5385A and AK4103
ON is "H", OFF is "L".
No.
Name
OFF ("L")
ON ("H")
Default
1
CKS0
OFF ("L")
2
CKS1
See Table 3
ON ("H")
3
DIF
MSB justified
I
2
S Compatible
OFF ("L")
4
M/S
Slave mode
Master mode
OFF ("L")
5
DFS0
OFF ("L")
6
DFS1
See Table 4
OFF ("L")
7
HPFE
HPF Disable
HPF Enable
ON ("H")
8
DIT1
ON ("H")
9
DIT0
See Table 5
OFF ("L")
10
-
N/A
N/A
OFF ("L")
Table 2. Mode Setting
CKS1
CKS0
MCLK Frequency
L
L
256fs
L
H
128fs
H
L
512fs
Default
H
H
384fs
Table 3. MCLK Frequency
DFS1
DFS0
LRCK Frequency
L
L
8kHz
fs
54kHz
Default
L
H
54kHz
<
fs
108kHz
H
L
108kHz
<
fs
216kHz
H
H
N/A
Table 4. Sampling Speed
Mode
DIT1
DIT0
MCLK
fs
0
L
L
256fs
108kHz
1
L
H
128fs
216kHz
2
H
L
512fs
54kHz
Default
3
H
H
384fs
54kHz
Table 5. MCLK Frequency Setting of AK4103
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The function of the toggle SW
Upper-side is "H" and lower-side is "L".
[SW1] (PDN): Resets the AK5385A and AK4103. Keep "H" during normal operation.
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