ASAHI KASEI [AK4532]

0178-E-01 1 1999/06

AK4532

Internet/Network/General Purpose Multimedia Audio CODEC

General Description

The AK4532 is a low-cost high-quality 16-Bit CODEC designed specifically for Internet Boxes, Network
PCs, and to interface with audio/video controller ICs for standard PC applications. AKM's AK4532
serial interface mode simplifies the design process on existing and new audio projects. The converters
can have a range of 4 to 50 kHz. For voice mail applications, an internal 26 dB microphone preamp has
been added and because of the internal input mixer, music or other sounds can easily be mixed with voice.

Features

2ch Audio CODEC

2ch stereo including 1ch mono recording mixer with L/R, R/L, L/L and R/R switching

2ch stereo playback mixer

Mic input with 26 dB optional gain

High Jitter Tolerance

Interface compatible with AKM's AK4531

Sampling Rate: 4 kHz to 50 kHz

3-wire Serial Interface for Mixer Control

5 V operation, can connect to 3.3 V Digital Controller.

Low power consumption - 150 mW

Power down mode

Small low profile package - 24 pin VSOP.

Block Diagram

ASAHI KASEI [AK4532]

0178-E-01 3 1999/06

Pin and Function

Pin Name

I/O

Function

AGND

Analog Ground

Analog Power - 5V

MIC/AUXR

Mic or Right Aux Line Level Input

AUXL

Left Aux Line Level Input

LINER

Right Line Level Input

LINEL

Left Line Level Input

Power down and Reset

MCLK

Master Clock for CODEC

LRCK

Left Right Clock for CODEC

SCLK

Serial Clock for CODEC

SDI

Serial Data In

SDO

Serial Data Out

DGND

Digital Ground

Digital Power - 5V

Chip Select

CCLK

Control Port Clock

CDATA

Control Port Data

CMODE

MCLK select (L:256fs, H:384fs)

LOUT

Left Analog Out

ROUT

Right Analog Out

VRAD

A/D Reference
Connect to AGND with 0.1uF and 4.7uF capacitors

AINFL

L channel Antialias Filter Pin
Connect to AGND with 1.0nF capacitor

AINFR

R channel Antialias Filter Pin
Connect to AGND with 1.0nF capacitor

VCOM

Voltage Common Output Pin
Connect to AGND with 0.1uF and 4.7uF capacitors.

Note: 1. No load current may be taken from the VCOM, VRAD pins for the external circuits.
2. All digital input pins should not be left floating.

ASAHI KASEI [AK4532]

0178-E-01 4 1999/06

ABSOLUTE MAXIMUM RATINGS

AGND, DGND = 0 V
Parameter

Symbol

min

max

Units

Power Supplies:

Analog
Digital

VA
VD

-0.3
-0.3

6.0
6.0 or VA+0.3

V
V

Input Current, Any Pin except Supplies

IIN

+/- 10

Analog Input Voltage Range

VINA

-0.3

6.0 or VA+0.3

Digital Input Voltage

VIND

-0.3

6.0 or VA+0.3

Ambient Temperature

-10

Storage Temperature

Tstg

-65

150

Note: 1. All voltages with respect to ground.
2. Max value is higher voltage of 6.0 or VA+0.3V.

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
Operating Specifications are not guarantee at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V, Note 1)
Parameter

Symbol

min

typ

max

units

Power Supplies

Analog
Digital

VA
VD

4.5
4.5

5.0
5.0

5.5
VA

V
V

Note 1: All voltages with respect to ground.

ASAHI KASEI [AK4532]

0178-E-01 5 1999/06

ANALOG CHARACTERISTICS

(Ta=25 ; VA, VD = 5.0V; fs = 44.1kHz; Signal Frequency = 1 kHz; MCLK=256fs; BCLK = 64 fs;
LRCK = fs, Gain, ATT and Mixer switches are defualt setting. Measurement frequency bandwidth is
10Hz to 20kHz, unless otherwise noted.)
Parameter

min

typ

max

units

A/D

measured via LineL and LineR

Resolution

Bits

S/(N+D)

-0.5 dB Input

S/N

A-weighted

Dynamic Range

-60 dB Input,
A-weighted

Interchannel Isolation

(Note 1)

Interchannel Gain Mismatch

0.2

0.5

Gain Drift

100

ppm/

Offset Error

(Note 2)

+/- 1

LSB

Input Voltage

(Note 4)

2.50

2.70

2.90

Vpp

Mixer Input Resistance

100

D/A

measured via LOUT and ROUT

Resolution

Bits

S/(N+D)

S/N

A-weighted

Dynamic Range

-60 dB Input,
A-weighted

Interchannel Isolation

(Note 1)

100

Interchannel Gain Mismatch

0.2

0.7

Gain Drift

100

ppm/

Output Voltage

(Note 4)

2.85

3.05

3.35

Vpp

Load Resistance

Out-of-Band Noise

BW < 100 kHz

-81

MIC Amp

Gain

Input Resistance

For 26dB setting

Mixer Gain Control

32 Steps

Step Size

(Note 3)

Gain Control Range

-50

Master Volume

32 Steps

Step Size

(Note 3)

Attenuation Control Range

-62

Power Supplies

Normal Operation

Power Dissipation

150

225

Power-Down Mode

Power Dissipation

100

200

Note: 1. Crosstalk between channels on the same A/D or D/A.

2. Internal HPF removes offset.

3. Minimum spec applies to -40dB setting.
4. Input and Output voltage scale with VA.

ASAHI KASEI [AK4532]

0178-E-01 6 1999/06

FILTER CHARACTERISTICS

(Ta=25 ; VA, VD = 5.0V±10%; fs = 44.1 kHz)
Parameter

Symbol

min

typ

max

Units

A/D Digital Filter
(Decimation LPF)
Passband (Note 1)

+/- 0.1 dB
-0.5 dB
-1.2 dB
-6.7 dB

0
0
0
0

16.5
19.0
20.0
22.05

kHz
kHz
kHz
kHz

Stopband

26.0

kHz

Passband Ripple

+/- 0.1

Stopband Attenuation

Group Delay Distortion

Delta GD

Group Delay (Note 2)

16.1

1/fs

A/D Digital Filter (HPF)
Frequency Response
(Note 1)

-3 dB
-0.5 dB
-0.1 dB

6.85
19.6
44.9

Hz
Hz
Hz

D/A Digital Filter
Passband (Note 1)

+/- 0.1 dB
-6.0 dB

0
0

18.0
22.05

kHz
kHz

Stopband

26.1

kHz

Passband Ripple

+/- 0.1

Stopband Attenuation

Group Delay (Note 2)

14.4

1/fs

D/A Digital Filter
+ Analog Filter
Frequency Response

0 to 20 kHz

+/- 1.0

Note: 1. The passband and stopband frequencies scale with fs.

2. The calculating delay time which occurred by digital filtering. This time is from the input of
analog signal to setting the 16bit data of both channels to the output register of ADC.
For DAC, this time is from setting 16bit data of both channels on input register to the output of
analog signal.

DIGITAL CHARACTERISTICS

(Ta=25 ; VA, VD = 5.0V±10%)
Parameter

Symbol

min

typ

max

Units

High-Level Input Voltage
Low-Level Input Voltage

VIH
VIL

2.2
-

-
-

-
0.8

V
V

High-Level Output Voltage (Iout=-80uA)
Low-Level Output Voltage (Iout=80uA)

VOH
VOL

VD-0.4
-

-
-

-
0.4

V
V

Input Leakage Current

Iin

+/-10

ASAHI KASEI [AK4532]

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SWITCHING CHARACTERISTICS

(Ta=25 ; VA, VD = 5.0V±10%, Cl = 20pF)
Parameter

Symbol

min

typ

max

Units

Master Clock Timing (CMODE=L)
(CMODE=H)
Pulse Width Low (CMODE=L)
(CMODE=H)
Pulse Width High (CMODE=L)
(CMODE=H)

fCLK
fCLK
fCLKL
fCLKL
fCLKH
fCLKH

1.024
1.536
31.25
23
31.25
23

11.2896
16.9344

12.800
19.2

MHz
MHz
ns
ns
ns
ns

LRCK Frequency (Note 1)
Duty Cycle

4
45

44.1

50
55

kHz
%

Serial Interface Timing
SCLK Period
SCLK Pulse Width Low
SCLK Pulse Width High
LRCK Edge to SCLK "rising edge" (Note 2)
SCLK "rising edge" to LRCK edge (Note 2)
SDI Hold Time
SDI Setup Time
LRCK to SDO(MSB)
SCLK "rising edge" to SDO

tSCK
tSCKL
tSCKH
tLRS
tSLR
tSDH
tSDS
tLRS
tSSD

312.5
100
100
50
50
50
50

70
70

ns
ns
ns
ns
ns
ns
ns
ns
ns

Control Interface Timing
CCLK Period
CCLK Pulse Width Low
CCLK Pulse Width High
CDATA Hold Time
CDATA Setup Time

High Level Time

"falling edge" to CCLK "rising" time

CCLK "rising time" to

"rising" time

tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH

200
80
80
50
50
150
50
50

ns
ns
ns
ns
ns
ns
ns
ns

Reset Timing

Pulse Width

"rising edge" to SDO delay (Note 3)

tPD
tPDS

150

516

ns
1/fs

Note: 1. If the duty of LRCK changes larger than 5% from 50%, the AK4532 is reset by the internal phase
detecting circuit automatically.

2. SCLK rising edge must not occur at the same time as LRCK edge.

3. These cycles are the number of LRCK rising from

rising.

ASAHI KASEI [AK4532]

0178-E-01 8 1999/06

Audio Data Formats

The data format of ADC and DAC are MSB first & MSB justified with 16bit. The SCLK needs 32fs or
more than 32fs in a LRCK cycle.

141312

1514

Don't Care

SCLK

SDI

16Bit

Lch

Rch

141312

1514

Don't Care

SDO

16Bit

SDO,SDI - 15:MSB,0:LSB

LRCK

=64fs

Timing Diagram

VIH
VIL

LRCK

SCLK

MCLK

tCLKL

1/fCLK

CLKH

VIH
VIL

1/fs

VIH
VIL

SCKL

SCK

SCKH

Clock Timing

LRCK

SCLK

SDO

SSD

VIH
VIL

LRS

SLR

SDH

SDS

SDI

VIH
VIL

LRS

Serial Audio Interface Timing

ASAHI KASEI [AK4532]

0178-E-01 10 1999/06

OPERATION OVERVIW

1. CONTROL REGISTER MAP
Addr

Master Volume Lch

MUTE

ATT4

ATT3

ATT2

ATT1

ATT0

Master Volume Rch

MUTE

ATT4

ATT3

ATT2

ATT1

ATT0

Voice Volume Lch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Voice Volume Rch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Line Volume Lch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Line Volume Rch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

AUX Volume Lch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

AUX Volume Rch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Output Mixer SW 1

LineL

LineR

MIC

Output Mixer SW 2

AUXL

AUXR

VoiceL

VoiceR

Lch Input Mixer SW 1

LineL

LineR

Rch Input Mixer SW 1

LineL

LineR

Lch Input Mixer SW 2

AUXL

AUXR

VoiceL

Rch Input Mixer SW 2

AUXL

AUXR

VoiceR

Reset and Power Down

RST

MIC Amp Gain

MGAIN

Note: ATT* is data bits for the attenuation level.
GAI* is data bits for the gain level.

IMPORTANT: There is the compatibility between the AK4531 and AK4532. But the input mixer
functions of those device has some different implication in the application, receptively.
And the other address of control register except those described in the above table and "1A" are
"do not care". Address "1A" for testing shall be strictly prohibited to access.
Be ware that the three MSB address bits(A7, A6, A5) are ignored by AK4532. Writing to address
"20" register will update the address "00" register for instance.

2. WRITE Timing of Control Register

CCLK

A7-A0:

Address

D7-D0:

Control Data

CDATA

3. Control Register Definitions

Addr

Master Volume Lch

MUTE

ATT4

ATT3

ATT2

ATT1

ATT0

Master Volume Rch

MUTE

ATT4

ATT3

ATT2

ATT1

ATT0

MUTE

No MUTE

ATT4:0

32 levels with 2 dB step

00000: 0dB
11111: -62 dB

Initial "0000 0000"(No MUTE & 0dB)

ASAHI KASEI [AK4532]

0178-E-01 11 1999/06

Addr

Voice Volume Lch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Voice Volume Rch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Line Volume Lch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

Line Volume Rch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

AUX Volume Lch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

AUX Volume Rch

MUTE

GAI4

GAI3

GAI2

GAI1

GAI0

MUTE

No MUTE

ATT4:0

32 levels with 2 dB step

00000: 12dB
00110: 0 dB
11111: -50 dB

Initial "0000 0110"(No MUTE & 0dB)

Addr

Output Mixer SW 1

LineL

LineR

MIC

Output Mixer SW 2

AUXL

AUXR

VoiceL

VoiceR

Lch Input Mixer SW 1

LineL

LineR

Rch Input Mixer SW 1

LineL

LineR

Lch Input Mixer SW 2

AUXL

AUXR

VoiceL

Rch Input Mixer SW 2

AUXL

AUXR

VoiceR

ON/OFF of Mixer Switches

OFF

Initial

"000X XX00"

XXX=000: Addr=10,14,15 (All:OFF)
XXX=011: Addr=11(Output Mixer Voice R&L:ON)
XXX=100: Addr=12(Lch Input Mixer Line L :ON)
XXX=010: Addr=13(Rch Input Mixer Line R :ON)

Addr

Reset and Power Down

RST

MIC Amp Gain

MGAIN

RST

initializes the contents of all registers except

and

RST

registers. When

pin goes low,

RST

1: Normal Operation
0: Initialize

pin goes low,

1: Normal Operation
0: Power Down

MGAIN selects the gain of MIC amp. The initial state is "0".

0: Bypass (0dB)
1: 26 dB

Try to avoid pops and clicks when activating or inactivating this function.

ASAHI KASEI [AK4532]

0178-E-01 12 1999/06

4. Explanation of each sequence
4.1. Reset & Power down

INIT1

INITA

Normal

INIT2

Normal PD+INIT2

Normal

Inhibit(1)

Inhibit(2)

Inhibit(2

Power Supply

PD pin

PD(register)

RST(register)

Internal State

Write to register

External clock

MCLK,LRCK,SCLK

The clocks may be stopped.

INITA

INIT1: Initializing all registers. The AK4532 exists in the power down state.

INIT2: Initializing all registers except

RST

registers.

INITA: Initializing the analog section. Initializing period is 516/fs.

PD: Power down state. All analog outputs are floating.

In case of

RST

registers.

Inhibit(1): Inhibits writing to all registers.

Inhibit(2): Inhibits writing to all registers except for

RST

registers.

The AK4532 operates with the external clocks(MCLK, LRCK, SCLK) during initializing the

analog section.

Figure 1. Reset & Power Down Sequence

4.2.

pin operation

"H": Normal operation

"L": Initializing mode 1(INIT1 in Figure 1)

Initializing all registers.

Inhibits writing to all registers.

The initialization of the analog section starts at rising edge of

pin.

SDO pin stays "L" during the initializing periods of 516/fs.

Going into power down state.

4.3.

RST

"1": Normal operation

"0": Initializing mode 2(INIT2 in Figure 1)

Initializing all registers except

RST

registers.

Inhibits writing to all registers except

RST

registers.

RST

pin goes "L".

The analog section is not initialized.

4.4.

"1": Normal operation

"0": Power down

The contents of all registers are held.

resister goes "1" when

pin goes "L"

All analog outputs(LOUT, ROUT) go floating.
The initialization of the analog section starts at the rising edge of

resister.

SDO pin stays "L" during the initializing period of 516/fs.

4.5. SDO output pin operation

ASAHI KASEI [AK4532]

0178-E-01 13 1999/06

SDO output is the 16bit data of ADC and goes "L"(0000H) in the following cases.

pin = "L"

During initializing the analog section(516/fs).

RST

4.6. Analog output pin(LOUT, ROUT) operation

These outputs are floating in the following case.

pin = "L"

5. System Clock

The external clocks which are required to operate the AK4532 are MCLK, LRCK and SCLK. MCLK

should be synchronized with LRCK but the phase is free of care. As the AK4532 includes the phase
detect circuit for LRCK, the AK4532 is reset automatically when the synchronization is out of phase
by changing the clock frequencies. Therefore, the reset is not required except only upon power-up.

All external clocks should always be present whenever the AK4532 is in normal operation mode. If these

clocks are not provided, the AK4532 may draw excessive current and do not possibly operate
properly because the device utilizes the dynamic logic internally. If the external clocks are not
present, the AK4532 should be in the power down mode.

5. Digital High Pass Filter

The ADC of the AK4532 has a digital high pass filter for DC offset cancel. The cut-off frequency of
the HPF is 6.85Hz at fs=44.1kHz and the frequency response at 20Hz is -0.5dB. It also scales with
sampling rate(fs).

ASAHI KASEI [AK4532]

0178-E-01 14 1999/06

System Design

Figure 2 shows the system connection diagram. An evaluation board is available which demonstrates the
optimum layout, power supply arrangements and measurement results.

LRCK

DGND

AGND

Synth.

Controller

+5V

Analog

AK4532

LOUT

0.1u

4.7u

VRAD

SCLK
SDI

Analog

Out

Lch

4.7u

0.1u

ROUT

Analog

Out

Rch

VCOM

CMODE
CDATA
CCLK
CS

MCLK

SDO

4.7u

0.1u

AINFL

MIC/AUXR

AUXL

LineR

LineL

AINFR

Figure 2. Typical Connection Diagram

1. Grounding and power supply decoupling

The AK4532 requires careful attention to power supply and grounding arrangements. VD should be

supplied from analog power supply. Analog ground and digital ground should be connected together
near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should
be as near to the AK4532 as possible, with the small value ceramic capacitor being the nearest.

2. On-chip voltage reference

The on-chip voltage references are output on the VRAD and VCOM pins for decouping .

The VRAD is used as the reference of A/D conversion. The VCOM is a signal ground of this chip. An

electrolytic capacitor less than 10uF in parallel with a 0.1uF ceramic capacitor attached to these pins
eliminates the effects of high frequency noise. Especially, the small value ceramic capacitors should
be as near to the AK4532 as possible. No load current may be drawn from the VRAD and VCOM
pins. All signals, especially clocks, should be kept away from the VRAD and VCOM pins in order to
avoid unwanted coupling into the chip.

ASAHI KASEI [AK4532]

0178-E-01 15 1999/06

3. Analog Inputs

The mixer input and the ADC inputs are single-ended and internally biased to the VCOM voltage with

60k(typ) resistance. The input signal range is typically 2.83Vpp(1Vrms). Figure 3 is an example
for 2Vrms line-level input circuit. The ADC output data format is 2's complement. The AK4532
accepts input voltages from AGND to VA. The output code is 7FFFH for input above a positive full
scale and 8000H for input below a negative full scale. The ideal code is 0000H with no input signal.
The DC offset is canceled by the internal HPF.

LINE/AUX

0.47u

5.1k

AK4532

Analog
Input
2Vrms

5.1k

Figure 3. 2Vrms Line-level Input

The AK4532 samples the analog inputs at 64fs. The digital filter rejects all noise higher than the stop

band. However, the filter will not reject frequencies right around 64fs(and multiples of 64fs). Most
audio signals do not have significant energy at 64fs. As a result, two 1nF capacitors are necessary for
AINFR and AINFL.

4. Analog Outputs

The analog outputs are also single-ended and centered around the VCOM voltage. The output signal

range is typically 2.83Vpp(1Vrms). The DAC input data format is 2's complement. The output
voltage is a positive full scale for 7FFFH and a negative full scale for 8000H. The ideal output is
VCOM voltage for 0000H. The internal switched-capacitor filter and continuous-time filter almost
remove the noise generated by the delta-sigma modulator of DAC beyond the audio passband,
especially low sampling rate. The noise floor level is almost constant and the audible noise level is
-83dB(typ) at 8kHz sampling.

5. Other information

5.1 Clock change

The clock change or LRCK phase shift should be done while muting the DAC output by the master

volume or voice volume to avoid the click noise by out-of-synchronization.

ADC may output digital code at the clock change, or LRCK phase shift may produce incomplete or

destroyed 16bit data. Then some attention is required carefully.

5.2 Offset on mixer inputs

When the mixer gain is set to +12dB, the output has pretty large offset even if the inputs are no signal.

Therefore, large click noise may occur when the gain level is changed quickly.

5.3 Click noise on the analog outputs

The click noise of about -50dB occurs from the analog outputs(LOUT, ROUT) at the power on/off or the

transition of

systems application.

Part Number AK4532