eroflex Circuit T
echnology
Data Bus Modules For The Future © SCDCT2561 REV A 8/16/99
Bus Controller, Remote Terminal and BUS Monitor
Features
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Second Source Compatible to the BUS-65610
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16MHz CT2565 Replacement
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RTU implements all dual redundant mode codes
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Selective mode code illegalization available
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16 bit microprocessor compatibility
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BC checks status word for correct address and set flags
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RTU illegal mode codes externally selectable
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16 bit µProcessor compatibility
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DMA handshaking for subsystem message transfers
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Continuous On-Line and Initiated Built-In-Test
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MIL-PRF-38534 compliant circuits available
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Packaging Hermetic Metal
· 78 Pin, 2.1" x 1.87" x .25" Plug-In type package
· 82 Lead, 2.2" x 1.61" x .18" Flat package
General Description
The CT2561 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller (BC), Remote
Terminal Unit (RTU) and Bus Monitor (MT). Packaged in a hybrid plug-in or flatpack, the CT2561
performs all the functions required to interface a MIL-STD-1553 dual redundant serial data bus such
as ACT4487 and a subsystem parallel three-state data bus.
Using a single Aeroflex custom monolithic ASIC design, the CT2561 features pin-for-pin and
functional CT2565 compatibility, user initiated self-test, and low power consumption.
Compatible with most microprocessors the CT2561 provides a 16bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing, DMA and control lines are provided internally, thereby reducing the subsystem
overhead associated with message transfers.
The CT2561 implements all dual redundant MIL-STD-1553 mode codes. In addition, any mode
code may (Optionally) be legalized through the use of an external PROM. Complete error detection
is provided by the CT2561 for BC and RTU operation. Error detection includes: response time-out,
inter-message gaps, sync, parity, Manchester, word count and bit count.
The CT2561 is fully compliant with MIL-STD-1553, is available screened in accordance with the
requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to
+125°C.
CT2561
FOR MIL-STD-1553B
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CIRCUIT TECHNOLOGY
www.aeroflex.com
Aeroflex Circuit Technology
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
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Aeroflex Circuit Technology
3
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1A Pin Function Table (78 Pin Plug-In)
Pin #
Symbol
I/O
Description
1
RT/BC
I
Mode Select input - logic "1" for RT mode, logic "0" for BC mode.
2
MT
I
Monitor mode enable. When unit is operating as a BC, a logic "0" will select
monitor mode.
3
STATEN
O
Output signal in RT mode that indicates status word is being transferred on the
internal bus.
4
TIMEOUT
O
Indicates No Response Timeout has occurred during BC and RTU (RT to RT
transfer).
5
HSFAIL
O
Output in RT mode indicating the DMA transfer did not occur in time to allow
proper operation on the 1553 bus.
6
DBACCEPT
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Input signal used to set DBACCEPT bit in status register for response to a valid
mode command on the 1553 bus.
7
SSFLAG
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Input which controls the SSFLAG bit in the status register.
8
SVCREQ
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Input which controls the service request bit in the status word.
9
INCMD
O
Output signal indicating the RT is currently in a message transfer sequence.
10
SSER
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Input which controls the subsystem error bit in the status register.
11
TESTOUT
-
Factory test point. Do not connect.
12
WC1
O
WC bit 1 - latched output of command word.
13
WC3
O
WC bit 3 - latched output of command word.
14
TXINH B
O
Transmitter inhibit output for channel B.
15
T/R
O
Output indicating T/R bit of current command word in RT mode.
16
CHA/CHB
O
Output indicating current selected channel (0 = Channel A).
17
CS
O
Chip Select output for subsystem memory control.
18
OE
O
Output Enable output for subsystem memory control.
19
BUSREQ
O
Output signal used to initiate transfer to/from subsystem.
20
+5V
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+5 Volt DC input.
21
DB0(LSB)
I/O
Least significant bit - 16 bit parallel data bus.
22
DB2
I/O
Bit 2 of data bus.
23
DB4
I/O
Bit 4 of data bus.
24
DB6
I/O
Bit 6 of data bus.
25
DB8
I/O
Bit 8 of data bus.
26
DB10
I/O
Bit 10 of data bus.
27
DB12
I/O
Bit 12 of data bus.
28
DB14
I/O
Bit 14 of data bus.
Aeroflex Circuit Technology
4
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
29
LWORD
-
Last word output during BC mode indicates last data word of the current
message transfer has been transferred on the parallel bus.
30
MSGERR
O
Output signal which indicates an error occurred during the current message
sequence.
31
TXDATA A
O
Bipolar serial data output to positive input of bus transceiver.
32
RXDATA A
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Bipolar serial input from negative output of bus transceiver.
33
RTADP
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Parity bit input for RT address.
34
RTAD1
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Bit 1 of RT address input.
35
RTAD3
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Bit 3 of RT address input.
36
RESET
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System reset input - resets all inputs in module.
37
TXDATA B
O
Bipolar serial data output to negative input bus transceiver.
38
RXDATA B
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Bipolar serial data input from positive output of bus transceiver.
39
16MHz
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16MHz TTL clock input.
40
GROUND
-
Signal ground.
41
BCSTART
I
Cycle enable input Logic "0" initiates bus controller message transfer operation.
42
NBGRNT
O
New bus grant output from RT indicates beginning of message transfer
sequence.
43
BITEN
O
Built in Test enable output indicates RT is transferring BlT word on internal 16 bit
bus.
44
WR
O
Write enable output for control of subsystem memory.
45
BUSGRNT
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Bus request input in response to DTREQ. Allows BC/RT to transfer data to
subsystem.
46
LOOPERR
O
Loop error output. Logic "0" indicates failure of loop back transmitted data.
47
SSBUSY
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Subsystem busy input for RT status word.
48
ILLCMD
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Illegal command input to RT, used to block RT response to an illegal command.
49
ADRINC
O
Increment output pulse. Goes LOW at the completion of each word transfer
to/from subsystem. Can increment external address counter.
50
CHASSIS
-
Frame ground electricity isolated from signal ground
51
WC0
O
LSB of current command word count field.
52
WC2
O
Bit 2 of word count field.
53
WC4
O
Bit 4 of word count field.
54
TXINH A
O
Transmitter inhibit output signal for Channel A.
55
LMC
O
Latched Mode Command. Logic "1" indicates current word command is a mode
code word, WC0-WC4.
56
TESTIN
-
Factory test point. Do not connect.
Table 1A Pin Function Table (78 Pin Plug-In) (continued)
Pin #
Symbol
I/O
Description
Aeroflex Circuit Technology
5
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
57
EOM
O
End of message output. Logic "0" occurs when BC/RT message is completed.
58
BUFENA
I
Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem
must read bit or Status words. Enables internal 16 bit bus onto subsystem bus.
59
BUSACK
O
Bus acknowledge output. LOW during DMA Handshake, in response to
BUSGRNT.
60
DB1
I/O
Bit 1 of 16 bit parallel bus.
61
DB3
I/O
Bit 3 of 16 bit parallel bus.
62
DB5
I/O
Bit 5 of 16 bit parallel bus.
63
DB7
I/O
Bit 7 of 16 bit parallel bus.
64
DB9
I/O
Bit 9 of 16 bit parallel bus.
65
DB11
I/O
Bit 11 of 16 bit parallel bus.
66
DB13
I/O
Bit 13 of 16 bit parallel bus.
67
DB15(MSB)
I/O
Bit 15 of 16 bit parallel bus.
68
STATERR
O
BC output indicates one or more bits set or address mismatch in a received
status word.
69
TXDATA A
O
Bipolar serial data output to negative input of bus transceiver.
70
RXDATA A
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Bipolar serial data input from positive output of bus transceiver.
71
NODT
O
No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front
end is active.
72
RTAD0
I
LSB of 5 bit RT address.
73
RTAD2
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Bit 2 of RT address.
74
RTAD4
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Bit 4 of RT address.
75
BCSTRCV
O
Broadcast receive. Logic "0" means the current command was a broadcast
command.
76
TXDATA B
O
Bipolar serial output to positive input of bus transceiver.
77
RXDATA B
I
Bipolar serial input from negative output of bus transceiver.
78
SOM
O
Start of message output indicates beginning of RT/BC message transfer
sequence.
Table 1A Pin Function Table (78 Pin Plug-In) (continued)
Pin #
Symbol
I/O
Description
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