OP467 Data Sheet

PIN CONNECTIONS

14-Lead Ceramic DIP (Y Suffix) and

14-Lead Epoxy DIP (P Suffix)

OUT A

IN A

+IN A

V+

+IN B

IN B

OUT B

OUT D

IN D

+IN D

+IN C

IN C

OUT C

OP467

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Quad Precision, High Speed

Operational Amplifier

OP467

FEATURES
High Slew Rate 170 V/ s
Wide Bandwidth 28 MHz
Fast Settling Time <200 ns to 0.01%
Low Offset Voltage <500 V
Unity-Gain Stable
Low Voltage Operation 5 V to 15 V
Low Supply Current <10 mA
Drives Capacitive Loads

APPLICATIONS
High Speed Image Display Drivers
High Frequency Active Filters
Fast Instrumentation Amplifiers
High Speed Detectors
Integrators
Photo Diode Preamps

GENERAL DESCRIPTION

The OP467 is a quad, high speed, precision operational ampli-
fier. It offers the performance of a high speed op amp combined
with the advantages of a precision operational amplifier all in a
single package. The OP467 is an ideal choice for applications
where, traditionally, more than one op amp was used to achieve
this level of speed and precision.

The OP467's internal compensation ensures stable unity-gain
operation, and it can drive large capacitive loads without oscilla-
tion. With a gain bandwidth product of 28 MHz driving a 30 pF
load, output slew rate in excess of 170 V/

s, and settling time to

0.01% in less than 200 ns, the OP467 provides excellent dy-
namic accuracy in high speed data-acquisition systems. The
channel-to-channel separation is typically 60 dB at 10 MHz.

The dc performance of OP467 includes less than 0.5 mV of
offset, voltage noise density below 6 nV/

Hz and total supply

current under 10 mA. Common-mode rejection and power
supply rejection ratios are typically 85 dB. PSRR is maintained
to better than 40 dB with input frequencies as high as 1 MHz.
The low offset and drift plus high speed and low noise, make the
OP467 usable in applications such as high speed detectors and
instrumentation.

The OP467 is specified for operation from

5 V to

15 V over

the extended industrial temperature range (40

C to +85

C) and

is available in 14-lead plastic and ceramic DIP, plus SOL-16
and 20-lead LCC surface mount packages.

Contact your local sales office for MIL-STD-883 data sheet and
availability.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

16-Lead SOL

(S Suffix)

OUT A

IN A

+IN A

V+

+IN B

IN B

OUT B

OUT D

IN D

+IN D

+IN C

IN C

OUT C

OP467

NC = NO CONNECT

+IN

IN

OUT

V+

Figure 1. Simplified Schematic

20-Position Chip Carrier

(RC Suffix)

+IN D

+IN C

10 11 12 13

(TOP VIEW)

+IN A

V+

+IN B

OUT A

IN A

OUT D

IN D

IN B

OUT B

IN C

OUT C

OP467

NC = NO CONNECT

OP467SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

0.2

0.5

+85

Input Bias Current

= 0 V

150

600

= 0 V, 40

+85

150

700

Input Offset Current

= 0 V

100

= 0 V, 40

+85

150

Common-Mode Rejection

CMR

12 V

CMR

12 V, 40

+85

Large Signal Voltage Gain

= 2 k

, 40

+85

77.5

Offset Voltage Drift

3.5

Bias Current Drift

0.2

pA/

Long Term Offset Voltage Drift

Note 1

750

OUTPUT CHARACTERISTICS

Output Voltage Swing

= 2 k

13.0

13.5

= 2 k

, 40

+85

12.9

13.12

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

4.5 V

18 V

120

+85

115

Supply Current

= 0 V

= 0 V, 40

+85

Supply Voltage Range

4.5

DYNAMIC PERFORMANCE

Gain Bandwidth Product

GBP

= +1, C

= 30 pF

MHz

Slew Rate

= 10 V Step, R

= 2 k

, C

= 30 pF

= +1

125

170

= 1

350

Full-Power Bandwidth

= 10 V Step

2.7

MHz

Settling Time

To 0.01%, V

= 10 V Step

200

Phase Margin

Degrees

Input Capacitance
Common Mode

2.0

Differential

1.0

NOISE PERFORMANCE

Voltage Noise

p-p

f = 0.1 Hz to 10 Hz

0.15

V p-p

Voltage Noise Density

f = 1 kHz

nV/

Current Noise Density

f = 1 kHz

pA/

NOTE

Long Term Offset Voltage Drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at +125

C, with an LTPD of 1.3.

Specifications subject to change without notice.

REV. C

(@ V

= 15.0 V, T

= +25 C unless otherwise noted)

OP467

REV. C

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

0.3

0.5

+85

Input Bias Current

= 0 V

125

600

= 0 V, 40

+85

150

700

Input Offset Current

= 0 V

100

= 0 V, 40

+85

150

Common-Mode Rejection

CMR

2.0 V

CMR

2.0 V, 40

+85

Large Signal Voltage Gain

= 2 k

, 40

+85

Offset Voltage Drift

3 5

Bias Current Drift

0.2

pA/

OUTPUT CHARACTERISTICS

Output Voltage Swing

= 2 k

3.0

3.5

= 2 k

, 40

+85

3.0

3.20

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

4.5 V

5.5 V

107

+85

105

Supply Current

= 0 V

= 0 V, 40

+85

DYNAMIC PERFORMANCE

Gain Bandwidth Product

GBP

= +1

MHz

Slew Rate

= 5 V Step, R

= 2 k

, C

= 39 pF

= +1

= 1

Full-Power Bandwidth

= 5 V Step

2.5

MHz

Settling Time

To 0.01%, V

= 5 V Step

280

Phase Margin

Degrees

NOISE PERFORMANCE

Voltage Noise

p-p

f = 0.1 Hz to 10 Hz

0.15

V p-p

Voltage Noise Density

f = 1 kHz

nV/

Current Noise Density

f = 1 kHz

pA/

Specifications subject to change without notice.

(@ V

= 5.0 V, T

= +25 C unless otherwise noted)

OP467

REV. C

WAFER TEST LIMITS

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

0.5

mV max

Input Bias Current

= 0 V

600

nA max

Input Offset Current

= 0 V

100

nA max

Input Voltage Range

V min/max

Common-Mode Rejection Ratio

CMRR

12 V

dB min

Power Supply Rejection Ratio

PSRR

V =

4.5 V to

18 V

dB min

Large Signal Voltage Gain

= 2 k

dB min

Output Voltage Range

= 2 k

13.0

V min

Supply Current

= 0 V, R

mA max

NOTES

Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard

product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

Guaranteed by CMR test.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 V

Input Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 V

Differential Input Voltage

. . . . . . . . . . . . . . . . . . . . . .

26 V

Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . Limited
Storage Temperature Range

Y, RC Packages . . . . . . . . . . . . . . . . . . . . 65

C to +175

P, S Packages . . . . . . . . . . . . . . . . . . . . . . 65

C to +150

Operating Temperature Range

OP467A . . . . . . . . . . . . . . . . . . . . . . . . . . 55

C to +125

OP467G . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

C to +85

Junction Temperature Range

Y, RC Packages . . . . . . . . . . . . . . . . . . . . 65

C to +175

P, S Packages . . . . . . . . . . . . . . . . . . . . . . 65

C to +150

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

Package Type

Units

14-Lead Cerdip (Y)

C/W

14-Lead Plastic DIP (P)

C/W

16-Lead SOL (S)

C/W

20-Contact LCC (RC)

C/W

NOTES

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

For supply voltages less than

18 V, the absolute maximum input voltage is equal

to the supply voltage.

is specified for the worst case conditions, i.e.,

is specified for device in socket

for cerdip, P-DIP, and LCC packages;

is specified for device soldered in circuit

board for SOIC package.

ORDERING GUIDE

Temperature

Package

Model

Ranges

Descriptions

Options

OP467AY/883

C to +125

C 14-Lead Cerdip

Q-14

OP467ARC/883 55

C to +125

C 20-Contact LCC

E-20A

OP467GP

C to +85

14-Lead Plastic DIP N-14

OP467GS

C to +85

16-Lead SOL

R-16

OP467GBC

+25

DICE

DICE CHARACTERISTICS

OP467 Die Size 0.111 0.100 inch, 11,100 sq. mils Sub-
strate is Connected to V+, Number of Transistors 165.

(

@ V

= 15.0 V, T

= +25 C unless otherwise noted.)

OP467

REV. C

20

10k

100M

10M

100k

10

180

PHASE SHIFT Degrees

OPEN-LOOP GAIN dB

FREQUENCY Hz

GAIN

PHASE

= 15V

= 1M

= 30pF

Figure 2. Open-Loop Gain, Phase vs. Frequency

20

100k

100M

10M

10k

FREQUENCY Hz

CLOSED-LOOP GAIN dB

= 15V

= +25 C

Figure 3. Closed-Loop Gain vs. Frequency

SUPPLY VOLTAGE Volts

OPEN-LOOP GAIN V/mV

= +125 C

= +25 C

= 55 C

Figure 4. Open-Loop Gain vs. Supply Voltage

100

100k

10k

100

FREQUENCY Hz

IMPEDANCE 

= 15V

= +25 C

VCL

= +100

VCL

= +10

VCL

= +1

Figure 5. Closed-Loop Output Impedance vs. Frequency

0.0

100k

10M

0.1

0.2

0.3

0.1

0.2

0.3

GAIN ERROR dB

FREQUENCY Hz

3.4

5.8

= 5

= 15

Figure 6. Gain Linearity vs. Frequency

10k

10M

100k

FREQUENCY Hz

MAXIMUM OUTPUT SWING Volts

VCL

= 1

VCL

= +1

= 15V

= +25 C

= 2k

Figure 7. Max V

OUT

Swing vs. Frequency

Typical Performance Characteristics

OP467

REV. C

10k

10M

100k

FREQUENCY Hz

MAXIMUM OUTPUT SWING Volts

= 5V

= +25 C

= 2k

VCL

= 1

VCL

= +1

Figure 8. Max V

OUT

Swing vs. Frequency

120

10k

10M

100k

100

FREQUENCY Hz

COMMON-MODE REJECTION Volts

= 15V

= +25 C

Figure 9. Common-Mode Rejection vs. Frequency

120

100k

10k

100

FREQUENCY Hz

POWER SUPPLY REJECTION dB

= 15V

= +25 C

Figure 10. Power-Supply Rejection vs. Frequency

1600

200

1400

1000

800

600

1200

400

LOAD CAPACITANCE pF

OVERSHOOT %

= 15V

= 2k

= 100mV p-p

VCL

= +1

VCL

= 1

Figure 11. Small Signal Overshoot vs. Load Capacitance

1600

200

1400

1000

800

600

1200

400

LOAD CAPACITANCE pF

OVERSHOOT %

= 5V

= 2k

= 100mV p-p

VCL

= +1

VCL

= 1

Figure 12. Small Signal Overshoot vs. Load Capacitance

40

10k

100M

10M

100k

30

20

10

GAIN dB

FREQUENCY Hz

= 15V

10000pF

1000pF

500pF

200pF

= NETWORK

ANALYZER

Figure 13. Noninverting Gain vs. Capacitive Loads

OP467

REV. C

50

100

100M

10M

100k

10k

40

30

20

10

90

80

70

60

FREQUENCY Hz

CHANNEL SEPARATION dB

= 15V

100

Figure 14. Channel Separation vs. Frequency

100

FREQUENCY Hz

INPUT CURRENT NOISE DENSITY pA/ Hz

15V

Figure 15. Input Current Noise Density vs. Frequency

100

1.0

0.1

10k

100

FREQUENCY Hz

nV/ Hz

Figure 16. Voltage Noise Density vs. Frequency

500

400

300

200

100

TIME ns

OUT

ERROR mV

= 15V

= 5V

= 50pF

Figure 17. Settling Time, Negative Edge

500

400

300

200

100

TIME ns

OUT

ERROR mV

= 15V

= 5V

= 50pF

Figure 18. Settling Time, Positive Edge

20

10

15

SUPPLY VOLTAGE Volts

INPUT VOLTAGE RANGE Volts

= +25 C

Figure 19. Input Voltage Range vs. Supply Voltage

OP467

REV. C

100k

100M

10M

10k

20

10

GAIN dB

FREQUENCY Hz

= 15V

= 5V

= 10k

= 50pF

= 15V

= 5V

30

40

50

Figure 20. Noninverting Gain vs. Supply Voltage

OUTPUT SWING Volts

100

10k

LOAD RESISTANCE 

POSITIVE

SWING

NEGATIVE
SWING

= 15V

= +25 C

Figure 21. Output Swing vs. Load Resistance

OUTPUT SWING Volts

100

10k

LOAD RESISTANCE 

POSITIVE

SWING

NEGATIVE
SWING

= 5V

= +25 C

Figure 22. Output Swing vs. Load Resistance

500

400

300

100

50

200

100

400

350

300

250

200

150

100

INPUT OFFSET VOLTAGE V

UNITS

= 15V

= +25 C

1252 OP AMPS

Figure 23. Input Offset Voltage Distribution

500

400

300

100

50

200

100

400

350

300

250

200

150

100

INPUT OFFSET VOLTAGE V

UNITS

= 5V

= +25 C

1252 OP AMPS

Figure 24. Input Offset Voltage Distribution

TC V

 V/ C

500

5.0

300

100

0.5

200

400

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

UNITS

= 15V

= +25 C

1252 OP AMPS

Figure 25. TC V

Distribution

OP467

REV. C

TC V

 V/ C

500

5.0

300

100

0.5

200

400

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

UNITS

= 5V

= +25 C

1252 OP AMPS

Figure 26. TC V

Distribution

75

125

50

100

25

29.0

27.0

28.5

27.5

28.0

TEMPERATURE C

PHASE MARGIN Degrees

GAIN BANDWIDTH PRODUCT MHz

GBW

= 15V

= 2k

Figure 27. Phase Margin and Gain Bandwidth vs.
Temperature

400

125

100

50

75

200

150

250

300

350

100

25

TEMPERATURE C

SLEW RATE V/

+SR

SR

= 5V

= 2k

VCL

= 1

Figure 28. Slew Rate vs. Temperature

400

125

100

50

75

200

150

250

300

350

100

25

TEMPERATURE C

SLEW RATE V/

SR

+SR

= 5V

= 2k

VCL

= +1

Figure 29. Slew Rate vs. Temperature

650

250

125

350

300

50

75

450

400

500

550

600

100

25

TEMPERATURE C

SLEW RATE V/

= 15V

= 2k

VCL

= 1

+SR

SR

Figure 30. Slew Rate vs. Temperature

400

125

100

50

75

200

150

250

300

350

100

25

TEMPERATURE C

SLEW RATE V/

= 15V

= 2k

VCL

= +1

+SR

SR

Figure 31. Slew Rate vs. Temperature

OP467

REV. C

APPLICATIONS INFORMATION

OUTPUT SHORT-CIRCUIT PERFORMANCE

To achieve a wide bandwidth and high slew rate, the OP467
output is not short circuit protected. Shorting the output to
ground or to the supplies may destroy the device.

For safe operation, the output load current should be limited so
that the junction temperature does not exceed the absolute
maximum junction temperature.

To calculate the maximum internal power dissipation, the fol-
lowing formula can be used:

max

where T

and T

are junction and ambient temperatures respec-

tively, P

is device internal power dissipation, and

is pack-

aged device thermal resistance given in the data sheet.

UNUSED AMPLIFIERS

It is recommended that any unused amplifiers in a quad package
be connected as a unity gain follower with a 1 k

feedback

resistor with noninverting input tied to the ground plain.

PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS

Satisfactory performance of a high speed op amp largely depends
on a good PC layout. To achieve the best dynamic performance,
following high frequency layout technique is recommended.

GROUNDING

A good ground plain is essential to achieve the optimum perfor-
mance in high speed applications. It can significantly reduce the
undesirable effects of ground loops and IR drops by providing a
low impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground plain.
To maintain a continuous and low impedance ground, avoid
running any traces on this layer.

POWER SUPPLY CONSIDERATIONS

In high frequency circuits, device lead length introduces an
inductance in series with the circuit. This inductance, combined
with stray capacitance, forms a high frequency resonance circuit.
Poles generated by these circuits will cause gain peaking and
additional phase shift, reducing the op amp's phase margin and
leading to an unstable operation.

A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the amplifier's power
supply rejection.

This is easily done by placing capacitors across the supply line
and the ground plain as close as possible to the device pin. Since
capacitors also have internal parasitic components, such as stray
inductance, selecting the right capacitor is important. To be
effective, they should have low impedance over the frequency
range of interest. Tantalum capacitors are an excellent choice
for their high capacitance/size ratio, but their ESR (Effective
Series Resistance) increases with frequency making them less

effective. On the other hand, ceramic chip capacitors have excel-
lent ESR and ESL (Effective Series Inductance) performance at
higher frequencies, and because of their small size, they can be
placed very close to the device pin, further reducing the stray
inductance. Best results are achieved by using a combination of
these two capacitors. A 5

F10

F tantalum parallel with a

0.1

F ceramic chip caps are recommended. If additional isola-

tion from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass caps and the power supply. A word of
caution, addition of the ferrite bead will introduce a new pole
and zero to frequency response of the circuit and could cause
unstable operation if it is not selected properly.

10 F TANTALUM

0.1 F CERAMIC CHIP

10 F TANTALUM

0.1 F CERAMIC CHIP

Figure 36. Recommended Power Supply Bypass

SIGNAL CONSIDERATIONS

Input and output traces need special attention to assure a mini-
mum stray capacitance. Input nodes are very sensitive to capaci-
tive reactance, particularly when connected to a high impedance
circuit. Stray capacitance can inject undesirable signals from a
noisy line into a high impedance input. Protect high impedance
input traces by providing guard traces around them. This will
also improve the channel separation significantly.

Additionally, any stray capacitance in parallel with the op amp's
input capacitance generates a pole in the frequency response of
the circuit. The additional phase shift caused by this pole will
reduce the circuit's gain margin. If this pole is within the gain
range of the op amp, it will cause unstable performance. To
reduce these undesirable effects, use the lowest impedance
where possible. Lowering the impedance at this node places the
poles at a higher frequency, far above the gain range of the am-
plifier. Stray capacitance on the PC board can be reduced by
making the traces narrow and as short as possible. Further re-
duction can be realized by choosing smaller pad size, increasing
the spacing between the traces, and using PC board material
with a low dielectric constant insulator (Dielectric Constant of
some common insulators: air = 1, Teflon

= 2.2, and FR4 =

4.7; with air being an ideal insulator).

Removing segments of the ground plain directly under the input
and output pads is recommended.

Outputs of high speed amplifiers are very sensitive to capacitive
loads. A capacitive load will introduce a pair of pole and zero to
the circuit's frequency response, reducing the phase margin,
leading to unstable operation or oscillation.

Teflon is a registered trademark of E.I. du Pont Co.

OP467

REV. C

Generally, it is a good design practice to isolate the amplifier's
output from any capacitive load by placing a resistor between
the amplifier's output and the rest of the circuits. A series resis-
tor of 10 to 100 ohms is normally sufficient to isolate the output
from a capacitive load.

The OP467 is internally compensated to provide stable opera-
tion, and is capable of driving large capacitive loads without
oscillation.

Sockets are not recommended since they increase the lead in-
ductance/capacitance and reduce the power dissipation of the
package by increasing the leads thermal resistance. If sockets
must be used, use Teflon or pin sockets with the shortest leads
possible.

PHASE REVERSAL

The OP467 is immune to phase reversal; its inputs can exceed
the supply rails by a diode drop without any phase reversal.

OUTPUT

INPUT

100

200 s

10V

15.8V

Figure 37. No Phase Reversal (A

= +1)

SATURATION RECOVERY TIME

The OP467 has a fast and symmetrical recovery time from ei-
ther rail. This feature is very useful in applications such as high
speed instrumentation and measurement circuits, where the
amplifier is frequently exposed to large signals that overload the
amplifier.

100

DLY 9.842 s

20ns

Figure 38. Saturation Recovery Time, Positive Rail

100

DLY 4.806 s

20ns

Figure 39. Saturation Recovery Time, Negative Rail

HIGH SPEED INSTRUMENTATION AMPLIFIER

The OP467 performance lends itself to a variety of high speed
applications, including high speed precision instrumentation
amplifiers. Figure 40 represents a circuit commonly used for
data acquisition, CCD imaging and other high speed application.

Circuit gain is set by R

. A 2 k

resistor will set the circuit gain

to 2; for unity gain, remove R

. For any other gain settings use

the following formula:

G = 2/R

Resistor Value is in k

is used for adjusting the dc common-mode rejection, and C

is used for ac common-mode rejection adjustments.

OUTPUT

10k

5pF

1.9k

200
10T

Figure 40. A High Speed Instrumentation Amplifier

2.5mV

0.01% 10V STEP
V

= 15V

NEG SLOPE

Figure 41. Instrumentation Amplifier Settling Time to
0.01% for a 10 V Step Input (Negative Slope)

OP467

REV. C

2.5mV

0.01% 10V STEP
V

= 15V

POS SLOPE

Figure 42. Instrumentation Amplifier Settling Time to
0.01% for a 10 V Step Input (Positive Slope)

ERROR
TO
SCOPE

INPUT

IN-AMP

OUTPUT

AD9617

549

61.9

Figure 43. Settling Time Measurement Circuit

2 MHz BIQUAD BANDPASS FILTER

The circuit in Figure 44 is commonly used in medical imaging
ultrasound receivers. The 30 MHz bandwidth is sufficient to
accurately produce the 2 MHz center frequency, as the mea-
sured response shows in Figure 45. When the op amp's band-
width is too close to the filter's center frequency, the amplifier's
internal phase shift causes excess phase shift at 2 MHz, which
alters the filter's response. In fact, if the chosen op amp has a
bandwidth close to 2 MHz, the combined phase shift of the
three op amps will cause the loop to oscillate.

Careful consideration must be given to the layout of this circuit
as with any other high speed circuit.

If the phase shift introduced by the layout is large enough, it
could alter the circuit performance, or worse, it will oscillate.

50pF

OUT

1/4

OP467

1/4

OP467

1/4

OP467

1/4

OP467

Figure 44. 2 MHz Biquad Filter

20

100k

100M

10M

10k

10

40

30

FREQUENCY Hz

GAIN dB

Figure 45. Biquad Filter Response

OP467

REV. C

FAST I-TO-V CONVERTER

The fast slew rate and fast settling time of the OP467 are well
suited to the fast buffers and I-to-V converters used in variety of
applications. The circuit in Figure 46 is a unipolar quad D/A
converter consisting of only two ICs. The current output of the
DAC8408 is converted to a voltage by the OP467 configured as
an I-to-V converter. This circuit is capable of settling to 0.1%
within 200 ns. Figures 47 and 48 show the full-scale settling
time of the outputs. To obtain reliable circuit performance, keep
the traces from the DAC's I

OUT

to the inverting inputs of the

OP467 short to minimize parasitic capacitance.

100

260.0ns

50mV

100ns

Figure 47. Voltage Output Settling Time

REF

OUT

2A/

OUT

REF

DGND

OUT

2C/

OUT

REF

OUT

REF

DAC8408

+5V

+10V

OUT

0.1 F

+15V

15V

C2
10pF

C1
10pF

0.1 F

OP467

+10V

OUT

DIGITAL
CONTROL
SIGNALS

C3
10pF

C4
10pF

OP467

DB0 (LSB)

DB1

DB2

DB3

DB4

DB5

OP467

(MSB) DB7

DB6

DS1

DS2

Figure 46. Quad DAC Unipolar Operation

100

251.0ns

50mV

100ns

Figure 48. Voltage Output Settling Time

OUT

3pF

OP467

I-V

DAC-8408

604

60.4

DC OFFSET

AD847

Figure 49. DAC V

OUT

Settling Time Circuit

OP467

REV. C

OP467 SPICE MACRO-MODEL

* Node assignments

noninverting input

inverting input

positive supply

negative supply

output

*
. SUBCKT OP467

*
* INPUT STAGE
*
I1

10E3

CIN

1E12

IOS

5E9

8 QN

9 QN

185 . 681

180 . 508

EOS

POLY (1) (14,20) 50E6

EREF

(20,0) 1

*
* GAIN STAGE AND DOMINANT POLE AT 1.5 kHz
*
R7

3 . 714E6

28 . 571E12

(5,6) 5 . 386E3

1 . 6

1 . 4E3

12E12

*
* COMMON-MODE STAGE WITH ZERO AT 1.26 kHz
*
ECM

POLY (2) (1,20)

(2,20) 0 0 . 5 0 . 5

1E6

25 . 119

126 . 721E12

*
* POLE AT 400E6
*
R10

1E6

0 . 398E15

(10,20) 1E6

*
* OUTPUT STAGE
*
ISY

8 . 183E3

RMP1

96 . 429E3

RMP2

96 . 429E3

RO1

200

RO2

200

1E7

GO1

(99,15) 5E3

GO2

(15,50) 5E3

(15,26) 5E3

(26,15) 5E3

*
* MODELS USED
*
. MODEL QN NPN (BF=33.333E3)
. MODEL DX D
. MODEL DY D (BV=50)
. ENDS OP467

R10

REF

RMP2

RMP1

G01

R02

R01

G02

+ 

Figure 50. SPICE Macro-Model Output Stage

N+

REF

Figure 51. SPICE Macro-Model Input and Gain Stage

OP467

REV. C

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

C1759c010/98

PRINTED IN U.S.A.

14-Lead Plastic DIP (P Suffix)

(N-14)

PIN 1

0.280 (7.11)
0.240 (6.10)

0.210

(5.33)

MAX

0.160 (4.06)
0.115 (2.92)

0.795 (20.19)
0.725 (18.42)

0.022 (0.558)

0.014 (0.36)

0.100

(2.54)

BSC

0.070 (1.77)
0.045 (1.15)

SEATING
PLANE

0.130
(3.30)
MIN

0.015
(0.381)
MIN

0.325 (8.25)
0.300 (7.62)

0.015 (0.38)
0.008 (0.20)

16-Lead Wide-Body SOL (S Suffix)

(R-16)

0.0500 (1.27 )

0.0157 (0.40 )

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.1043 (2.65)

0.0926 (2.35)

0.4133 (10.50)

0.3977 (10.10)

0.0118 (0.30)

0.0040 (0.10)

PIN 1

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

0.0291 (0.74 )

0.0098 (0.25 )

0.0125 (0.32)

0.0091 (0.23)

SEE

DETAIL
ABOVE

14-Lead Cerdip (Y Suffix)

(Q-14)

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

0.785 (19.94) MAX

0.200

(5.08)

MAX

0.023 (0.58)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

0.200 (5.08)

0.125 (3.18)

0.100

(2.54)

BSC

SEATING
PLANE

0.005 (0.13) MIN

0.098 (2.49) MAX

PIN 1

0.310 (7.87)

0.220 (5.59)

20-Terminal Leadless Ceramic Chip Carrier (RC Suffix)

(E-20A)

NO. 1 PIN INDEX

0.040 x 45

(1.02 x 45 )

REF 3 PLCS

0.020 x 45

(0.51 x 45 )

REF

0.050

(1.27)

BSC

0.358 (9.09)

0.32 (8.69)

0.055 (1.40)
0.045 (1.14)

0.100 (2.54)
0.064 (1.63)

0.028 (0.71)
0.022 (0.56)

BOTTOM

VIEW

0.075 (1.91) REF

Part Number OP467ARC/883